OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [start/] [insight/] [sim/] [d30v/] [sim-main.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom
/*  This file is part of the program psim.
2
 
3
    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
4
    Copyright (C) 1997, 1998, Free Software Foundation
5
 
6
    This program is free software; you can redistribute it and/or modify
7
    it under the terms of the GNU General Public License as published by
8
    the Free Software Foundation; either version 2 of the License, or
9
    (at your option) any later version.
10
 
11
    This program is distributed in the hope that it will be useful,
12
    but WITHOUT ANY WARRANTY; without even the implied warranty of
13
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
    GNU General Public License for more details.
15
 
16
    You should have received a copy of the GNU General Public License
17
    along with this program; if not, write to the Free Software
18
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
 
20
    */
21
 
22
 
23
#ifndef _SIM_MAIN_H_
24
#define _SIM_MAIN_H_
25
 
26
/* This simulator suports watchpoints */
27
#define WITH_WATCHPOINTS 1
28
 
29
#include "sim-basics.h"
30
#include "sim-signal.h"
31
 
32
/* needed */
33
typedef address_word sim_cia;
34
#define INVALID_INSTRUCTION_ADDRESS ((address_word) 0 - 1)
35
 
36
/* This simulator doesn't cache anything so no saving of context is
37
   needed during either of a halt or restart */
38
#define SIM_ENGINE_HALT_HOOK(SD,CPU,CIA) while (0)
39
#define SIM_ENGINE_RESTART_HOOK(SD,CPU,CIA) while (0)
40
 
41
#include "sim-base.h"
42
 
43
/* These are generated files.  */
44
#include "itable.h"
45
#include "s_idecode.h"
46
#include "l_idecode.h"
47
 
48
#include "cpu.h"
49
#include "alu.h"
50
 
51
 
52
struct sim_state {
53
 
54
  sim_event *pending_interrupt;
55
 
56
  /* the processors proper */
57
  sim_cpu cpu[MAX_NR_PROCESSORS];
58
#if (WITH_SMP)
59
#define STATE_CPU(sd, n) (&(sd)->cpu[n])
60
#else
61
#define STATE_CPU(sd, n) (&(sd)->cpu[0])
62
#endif
63
 
64
  /* The base class.  */
65
  sim_state_base base;
66
 
67
};
68
 
69
 
70
/* deliver an interrupt */
71
sim_event_handler d30v_interrupt_event;
72
 
73
 
74
#ifdef HAVE_STRING_H
75
#include <string.h>
76
#else
77
#ifdef HAVE_STRINGS_H
78
#include <strings.h>
79
#endif
80
#endif
81
 
82
#endif /* _SIM_MAIN_H_ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.