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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [cache.cfg] - Blame information for rev 690

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Line No. Rev Author Line
1 484 simons
section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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7 621 simons
  nmemories = 1
8 484 simons
  device 0
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    name = "RAM"
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    ce = 0
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    baseaddr = 0x00000000
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    size = 0x00200000
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    delayr = 1
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    delayw = 2
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  enddevice
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end
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18 631 simons
section sim
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  /* verbose = 1 */
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  debug = 0
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  history = 1
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  exe_log = 0
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  exe_log_fn = "executed.log"
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  clkcycle = 4ns
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end
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27 484 simons
section immu
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  enabled = 0
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  nsets = 32
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  nways = 1
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  pagesize = 8192
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end
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section dmmu
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  enabled = 0
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  nsets = 32
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  nways = 1
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  pagesize = 8192
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end
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section ic
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  enabled = 1
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  nsets = 256
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  nways = 1
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  blocksize = 16
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  ustates = 2
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end
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section dc
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  enabled = 1
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  nsets = 256
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  nways = 1
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  blocksize = 16
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  ustates = 2
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end
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section cpu
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  ver = 0x1200
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  rev = 0x0001
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  /* upr = */
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  superscalar = 0
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  hazards = 0
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  dependstats = 0
64 541 markom
end

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