URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [eth.cfg] - Blame information for rev 1782

Go to most recent revision | Details | Compare with Previous | View Log


include "default.cfg"
 
section sim
  verbose = 0
  debug = 4
end
 
section dma
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end
 
section ethernet
  nethernets = 1
 
  device 0
    baseaddr = 0x88000000
    dma = 0
    irq = 15
    rtx_type = 0
    tx_channel = 0
    rx_channel = 1
    rxfile = "eth0.tx"
    txfile = "eth0.tx"
    sockif = "eth0"
  enddevice
end

Line No.	Rev	Author	Line
1	690	markom	`include "default.cfg"`
2	380	markom
3	311	markom	`section sim`
4			`verbose = 0`
5	418	erez	`debug = 4`
6	311	markom	`end`
7
8			`section dma`
9			`ndmas = 1`
10
11			`device 0`
12			`baseaddr = 0x90000000`
13			`irq = 4`
14			`enddevice`
15			`end`
16
17			`section ethernet`
18			`nethernets = 1`
19
20			`device 0`
21			`baseaddr = 0x88000000`
22			`dma = 0`
23	733	ivang	`irq = 15`
24	837	ivang	`rtx_type = 0`
25	311	markom	`tx_channel = 0`
26			`rx_channel = 1`
27	837	ivang	`rxfile = "eth0.tx"`
28	325	erez	`txfile = "eth0.tx"`
29	733	ivang	`sockif = "eth0"`
30	311	markom	`enddevice`
31			`end`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [eth.cfg] - Blame information for rev 1782