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/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
   The or1ksim have various parameters, which can be set in configuration
   files.  Multiple configurations may be used and switched between at
   or1ksim startup.
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
   all parameters are not defined, default configuration is used.
   Users should not rely on default configuration, but rather redefine all
   critical settings, since default configuration may differ in newer
   versions of the or1ksim.
   If multiple configurations are used, user can switch between them by
   supplying -f  option when starting simulator.
 
   This file may contain (standard C) only comments - no // support.
 
   Like normal configuration file, this file is divided in sections,
   where each section is described in detail also.
 
   Some section also have subsections. One example of such subsection is
   block:
 
   device 
     instance specific parameters...
   enddevice
 
   which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
   This section specifies how is initial memory generated and which blocks
   it consist of.
 
   type = random/unknown/pattern
      specifies the initial memory values. 'random' parameter generate
      random memory using seed 'random_seed' parameter. 'pattern' parameter
      fills memory with 'pattern' parameter and 'unknown' does not specify
      how memory should be generated - the fastest option.
 
   random_seed = 
      random seed for randomizer, used if type = random
 
   pattern = 
      pattern to fill memory, used if type = pattern
 
   nmemories = 
      number of memory instances connected
 
   instance specific:
     baseaddr = 
        memory start address
 
     size = 
        memory size
 
     name = ""
        memory block name
 
     ce = 
        chip enable index of the memory instance
 
     delayr = 
        cycles, required for read access, -1 if instance does not support reading
 
     delayw = 
        cycles, required for write access, -1 if instance does not support writing
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     log = ""
        filename, where to log memory accesses to, no log, if log command is not specified
*/
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  nmemories = 3
  device 0
    name = "RAM1"
    ce = 0
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice
 
  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
 
  device 2
    name = "RAM2"
    ce = 2
    baseaddr = 0x80000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice
end
 
 
/* IMMU SECTION
 
    This section configures Instruction Memory Menangement Unit
 
    enabled = 0/1
       whether IMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of ITLB sets; must be power of two
 
    nways = 
       number of ITLB ways
 
    pagesize = 
       instruction page size; must be power of two
 
    entrysize = 
       instruction entry size in bytes
 
    ustates = 
       number of ITLB usage states (2, 3, 4 etc., max is 4)
*/
 
section immu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
 
/* DMMU SECTION
 
    This section configures Data Memory Menangement Unit
 
    enabled = 0/1
       whether DMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DTLB sets; must be power of two
 
    nways = 
       number of DTLB ways
 
    pagesize = 
       data page size; must be power of two
 
    entrysize = 
       data entry size in bytes
 
    ustates = 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
*/
 
section dmmu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
 
/* IC SECTION
 
    This section configures Instruction Cache
 
    enabled = 0/1
       whether IC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of IC sets; must be power of two
 
    nways = 
       number of IC ways
 
    blocksize = 
       IC block size in bytes; must be power of two
 
    ustates = 
       number of IC usage states (2, 3, 4 etc., max is 4)
*/
 
section ic
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
 
/* DC SECTION
 
    This section configures Data Cache
 
    enabled = 0/1
       whether DC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DC sets; must be power of two
 
    nways = 
       number of DC ways
 
    blocksize = 
       DC block size in bytes; must be power of two
 
    ustates = 
       number of DC usage states (2, 3, 4 etc., max is 4)
*/
 
section dc
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
/* SIM SECTION
 
  This section specifies how should sim behave.
 
  verbose = 0/1
      whether to print out extra messages
 
  debug = 0-9
      = 0 disabled debug messages
      1-9 level of sim debug information, greater the number more verbose is
          the output
 
  profile = 0/1
      whether to generate profiling file 'sim.profile'
 
  prof_fn = ""
      filename, where to generate profiling info, used
      only if 'profile' is set
 
  history = 0/1
      whether instruction execution flow is tracked for
      display by simulator hist command. Useful for
      back-trace debugging.
 
  exe_log = 0/1
      whether execution log should be generated
 
  exe_log_fn = ""
      where to put execution log in, used only if 'exe_log'
      is set
 
  clkcycle = [ps|ns|us|ms]
      specifies time measurement for one cycle
*/
 
section sim
  /* verbose = 1 */
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  history = 1
  exe_log = 0
  exe_log_fn = "executed.log"
  clkcycle = 4ns
end
 
 
/* SECTION VAPI
 
    This section configures Verification API, used for Advanced
    Core Verification.
 
    enabled = 0/1
        whether to start VAPI server
 
    server_port = 
        TCP/IP port to start VAPI server on
 
    log_enabled = 0/1
       whether logging of VAPI requests is enabled
 
    vapi_fn = 
       specifies filename where to log into, if log_enabled is selected
*/
 
section VAPI
  enabled = 0
  server_port = 9998
  log_enabled = 0
  vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
   This section specifies various CPU parameters.
 
   ver = 
   rev = 
      specifies version and revision of the CPU used
 
   upr = 
      changes the upr register
 
   superscalar = 0/1
      whether CPU is scalar or superscalar
      (modify cpu/or32/execute.c to tune superscalar model)
 
   hazards = 0/1
      whether data hazards are tracked in superscalar CPU
      and displayed by the simulator r command
 
   dependstats = 0/1
      whether inter-instruction dependencies are calculated
      and displayed by simulator stats command.
 
   btic = 0/1
      enable branch target instruction cache model
 
   bpb = 0/1
      enable branch prediction buffer model
 
      parameters for CPU analysis
*/
 
section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
end
 
section bpb
  enabled = 0
  btic = 0
end
 
 
/* DEBUG SECTION
 
   This sections specifies how debug unit should behave.
 
   enabled = 0/1
      whether debug unit is enabled
 
   gdb_enabled = 0/1
      whether to start gdb server at 'server_port' port
 
   server_port = 
      TCP/IP port to start gdb server on, used only if gdb_enabled
      is set
 
section debug
  enabled = 0
  gdb_enabled = 0
  server_port = 9999
end
 
 
/* MC SECTION
 
   This section configures the memory controller
 
   enabled = 0/1
      whether memory controller is enabled
 
   baseaddr = 
      address of first MC register
 
   POC = 
      Power On Configuration register
*/
 
section mc
  enabled = 0
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
 
/* UART SECTION
 
   This section configures UARTs
 
   enabled = 0/1
      whether uarts are enabled
 
   nuarts = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first UART register for this device
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     irq = 
        irq number for this device
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     jitter = 
        in msecs... time to block, -1 to disable it
 
     vapi_id = 
        VAPI id of this instance
*/
/*
section uart
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    irq = 2
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
*/
 
/* DMA SECTION
 
   This section configures DMAs
 
   enabled = 0/1
      whether DMAs are enabled
 
   ndmas = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first DMA register for this device
 
     irq = 
        irq number for this device
 
     vapi_id = 
        VAPI id of this instance
*/
/*
section dma
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end
*/
 
/* ETHERNET SECTION
 
   This section configures ethernets
 
   enabled = 0/1
      whether ethernets are enabled
 
   nethernets = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first ethernet register for this device
 
     dma = 
        which controller is this ethernet "connected" to
 
     rx_channel = 
        DMA channel used for RX
 
     tx_channel = 
        DMA channel used for TX
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     vapi_id = 
        VAPI id of this instance
*/
/*
section ethernet
  nethernets = 1
 
  device 0
    baseaddr = 0x88000000
    dma = 0
    tx_channel = 0
    rx_channel = 1
    rxfile = "/tmp/eth0.rx"
    txfile = "/tmp/eth0.tx"
  enddevice
end
*/
/* TICK TIMER SECTION
 
    This section configures tick timer
 
    enabled = 0/1
      whether tick timer is enabled
 
    irq = 
      irq number
*/
 
section tick
  enabled = 1
end

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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [except_test.cfg] - Blame information for rev 608

Line No.	Rev	Author	Line
1	516	markom	`/* sim.cfg -- Simulator configuration script file`
2			`Copyright (C) 2001, Marko Mlinar, markom@opencores.org`
3
4			`This file includes a lot of help about configurations and default one`
5
6			`This file is part of OpenRISC 1000 Architectural Simulator.`
7
8			`This program is free software; you can redistribute it and/or modify`
9			`it under the terms of the GNU General Public License as published by`
10			`the Free Software Foundation; either version 2 of the License, or`
11			`(at your option) any later version.`
12
13			`This program is distributed in the hope that it will be useful,`
14			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`GNU General Public License for more details.`
17
18			`You should have received a copy of the GNU General Public License`
19			`along with this program; if not, write to the Free Software`
20			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
21
22
23			`/* INTRODUCTION`
24
25			`The or1ksim have various parameters, which can be set in configuration`
26			`files. Multiple configurations may be used and switched between at`
27			`or1ksim startup.`
28			`By default, or1ksim loads condfiguration file from './sim.cfg' and if not`
29			`found it checks '~/.or1k/sim.cfg'. If even this file is not found or`
30			`all parameters are not defined, default configuration is used.`
31			`Users should not rely on default configuration, but rather redefine all`
32			`critical settings, since default configuration may differ in newer`
33			`versions of the or1ksim.`
34			`If multiple configurations are used, user can switch between them by`
35			`supplying -f option when starting simulator.`
36
37			`This file may contain (standard C) only comments - no // support.`
38
39			`Like normal configuration file, this file is divided in sections,`
40			`where each section is described in detail also.`
41
42			`Some section also have subsections. One example of such subsection is`
43			`block:`
44
45			`device`
46			`instance specific parameters...`
47			`enddevice`
48
49			`which creates a device instance.`
50			`*/`
51
52
53			`/* MEMORY SECTION`
54
55			`This section specifies how is initial memory generated and which blocks`
56			`it consist of.`
57
58			`type = random/unknown/pattern`
59			`specifies the initial memory values. 'random' parameter generate`
60			`random memory using seed 'random_seed' parameter. 'pattern' parameter`
61			`fills memory with 'pattern' parameter and 'unknown' does not specify`
62			`how memory should be generated - the fastest option.`
63
64			`random_seed =`
65			`random seed for randomizer, used if type = random`
66
67			`pattern =`
68			`pattern to fill memory, used if type = pattern`
69
70			`nmemories =`
71			`number of memory instances connected`
72
73			`instance specific:`
74			`baseaddr =`
75			`memory start address`
76
77			`size =`
78			`memory size`
79
80			`name = ""`
81			`memory block name`
82
83			`ce =`
84			`chip enable index of the memory instance`
85
86			`delayr =`
87			`cycles, required for read access, -1 if instance does not support reading`
88
89			`delayw =`
90			`cycles, required for write access, -1 if instance does not support writing`
91
92			`16550 = 0/1`
93			`0, if this device is uart 16450 and 1, if it is 16550`
94
95			`log = ""`
96			`filename, where to log memory accesses to, no log, if log command is not specified`
97			`*/`
98
99			`section memory`
100			`/*random_seed = 12345`
101			`type = random*/`
102			`pattern = 0x00`
103			`type = unknown /* Fastest */`
104
105	608	simons	`nmemories = 3`
106	516	markom	`device 0`
107	608	simons	`name = "RAM1"`
108	516	markom	`ce = 0`
109			`baseaddr = 0x40000000`
110			`size = 0x00200000`
111			`delayr = 1`
112			`delayw = 2`
113			`enddevice`
114
115			`device 1`
116			`name = "FLASH"`
117			`ce = 1`
118			`baseaddr = 0x00000000`
119			`size = 0x00200000`
120			`delayr = 10`
121			`delayw = -1`
122			`enddevice`
123	608	simons
124			`device 2`
125			`name = "RAM2"`
126			`ce = 2`
127			`baseaddr = 0x80000000`
128			`size = 0x00200000`
129			`delayr = 1`
130			`delayw = 2`
131			`enddevice`
132	516	markom	`end`
133
134
135			`/* IMMU SECTION`
136
137			`This section configures Instruction Memory Menangement Unit`
138
139			`enabled = 0/1`
140			`whether IMMU is enabled`
141			`(NOTE: UPR bit is set)`
142
143			`nsets =`
144			`number of ITLB sets; must be power of two`
145
146			`nways =`
147			`number of ITLB ways`
148
149			`pagesize =`
150			`instruction page size; must be power of two`
151
152			`entrysize =`
153			`instruction entry size in bytes`
154
155			`ustates =`
156			`number of ITLB usage states (2, 3, 4 etc., max is 4)`
157			`*/`
158
159			`section immu`
160			`enabled = 1`
161			`nsets = 32`
162			`nways = 1`
163			`pagesize = 8192`
164			`end`
165
166
167			`/* DMMU SECTION`
168
169			`This section configures Data Memory Menangement Unit`
170
171			`enabled = 0/1`
172			`whether DMMU is enabled`
173			`(NOTE: UPR bit is set)`
174
175			`nsets =`
176			`number of DTLB sets; must be power of two`
177
178			`nways =`
179			`number of DTLB ways`
180
181			`pagesize =`
182			`data page size; must be power of two`
183
184			`entrysize =`
185			`data entry size in bytes`
186
187			`ustates =`
188			`number of DTLB usage states (2, 3, 4 etc., max is 4)`
189			`*/`
190
191			`section dmmu`
192			`enabled = 1`
193			`nsets = 32`
194			`nways = 1`
195			`pagesize = 8192`
196			`end`
197
198
199			`/* IC SECTION`
200
201			`This section configures Instruction Cache`
202
203			`enabled = 0/1`
204			`whether IC is enabled`
205			`(NOTE: UPR bit is set)`
206
207			`nsets =`
208			`number of IC sets; must be power of two`
209
210			`nways =`
211			`number of IC ways`
212
213			`blocksize =`
214			`IC block size in bytes; must be power of two`
215
216			`ustates =`
217			`number of IC usage states (2, 3, 4 etc., max is 4)`
218			`*/`
219
220			`section ic`
221			`enabled = 0`
222			`nsets = 512`
223			`nways = 1`
224			`blocksize = 16`
225			`end`
226
227
228			`/* DC SECTION`
229
230			`This section configures Data Cache`
231
232			`enabled = 0/1`
233			`whether DC is enabled`
234			`(NOTE: UPR bit is set)`
235
236			`nsets =`
237			`number of DC sets; must be power of two`
238
239			`nways =`
240			`number of DC ways`
241
242			`blocksize =`
243			`DC block size in bytes; must be power of two`
244
245			`ustates =`
246			`number of DC usage states (2, 3, 4 etc., max is 4)`
247			`*/`
248
249			`section dc`
250			`enabled = 0`
251			`nsets = 512`
252			`nways = 1`
253			`blocksize = 16`
254			`end`
255
256			`/* SIM SECTION`
257
258			`This section specifies how should sim behave.`
259
260			`verbose = 0/1`
261			`whether to print out extra messages`
262
263			`debug = 0-9`
264			`= 0 disabled debug messages`
265			`1-9 level of sim debug information, greater the number more verbose is`
266			`the output`
267
268			`profile = 0/1`
269			`whether to generate profiling file 'sim.profile'`
270
271			`prof_fn = ""`
272			`filename, where to generate profiling info, used`
273			`only if 'profile' is set`
274
275			`history = 0/1`
276			`whether instruction execution flow is tracked for`
277			`display by simulator hist command. Useful for`
278			`back-trace debugging.`
279
280			`exe_log = 0/1`
281			`whether execution log should be generated`
282
283			`exe_log_fn = ""`
284			`where to put execution log in, used only if 'exe_log'`
285			`is set`
286
287			`clkcycle = [ps\|ns\|us\|ms]`
288			`specifies time measurement for one cycle`
289			`*/`
290
291			`section sim`
292			`/* verbose = 1 */`
293			`debug = 0`
294			`profile = 0`
295			`prof_fn = "sim.profile"`
296
297			`history = 1`
298			`exe_log = 0`
299			`exe_log_fn = "executed.log"`
300			`clkcycle = 4ns`
301			`end`
302
303
304			`/* SECTION VAPI`
305
306			`This section configures Verification API, used for Advanced`
307			`Core Verification.`
308
309			`enabled = 0/1`
310			`whether to start VAPI server`
311
312			`server_port =`
313			`TCP/IP port to start VAPI server on`
314
315			`log_enabled = 0/1`
316			`whether logging of VAPI requests is enabled`
317
318			`vapi_fn =`
319			`specifies filename where to log into, if log_enabled is selected`
320			`*/`
321
322			`section VAPI`
323			`enabled = 0`
324			`server_port = 9998`
325			`log_enabled = 0`
326			`vapi_log_fn = "vapi.log"`
327			`end`
328
329
330			`/* CPU SECTION`
331
332			`This section specifies various CPU parameters.`
333
334			`ver =`
335			`rev =`
336			`specifies version and revision of the CPU used`
337
338			`upr =`
339			`changes the upr register`
340
341			`superscalar = 0/1`
342			`whether CPU is scalar or superscalar`
343			`(modify cpu/or32/execute.c to tune superscalar model)`
344
345			`hazards = 0/1`
346			`whether data hazards are tracked in superscalar CPU`
347			`and displayed by the simulator r command`
348
349			`dependstats = 0/1`
350			`whether inter-instruction dependencies are calculated`
351			`and displayed by simulator stats command.`
352
353			`btic = 0/1`
354			`enable branch target instruction cache model`
355
356			`bpb = 0/1`
357			`enable branch prediction buffer model`
358
359			`parameters for CPU analysis`
360			`*/`
361
362			`section cpu`
363			`ver = 0x1200`
364			`rev = 0x0001`
365			`/* upr = */`
366			`superscalar = 0`
367			`hazards = 0`
368			`dependstats = 0`
369	541	markom	`end`
370
371			`section bpb`
372			`enabled = 0`
373	516	markom	`btic = 0`
374			`end`
375
376
377			`/* DEBUG SECTION`
378
379			`This sections specifies how debug unit should behave.`
380
381			`enabled = 0/1`
382			`whether debug unit is enabled`
383
384			`gdb_enabled = 0/1`
385			`whether to start gdb server at 'server_port' port`
386
387			`server_port =`
388			`TCP/IP port to start gdb server on, used only if gdb_enabled`
389			`is set`
390
391			`section debug`
392			`enabled = 0`
393			`gdb_enabled = 0`
394			`server_port = 9999`
395			`end`
396
397
398			`/* MC SECTION`
399
400			`This section configures the memory controller`
401
402			`enabled = 0/1`
403			`whether memory controller is enabled`
404
405			`baseaddr =`
406			`address of first MC register`
407
408			`POC =`
409			`Power On Configuration register`
410			`*/`
411
412			`section mc`
413			`enabled = 0`
414			`baseaddr = 0xa0000000`
415			`POC = 0x00000008 /* Power on configuration register */`
416			`end`
417
418
419			`/* UART SECTION`
420
421			`This section configures UARTs`
422
423			`enabled = 0/1`
424			`whether uarts are enabled`
425
426			`nuarts =`
427			`make specified number of instances, configure each`
428			`instance within device - enddevice construct.`
429
430			`instance specific:`
431			`baseaddr =`
432			`address of first UART register for this device`
433
434			`rx_file = ""`
435			`filename, where to read data from`
436
437			`tx_file = ""`
438			`filename, where to write data to`
439
440			`irq =`
441			`irq number for this device`
442
443			`16550 = 0/1`
444			`0, if this device is uart 16450 and 1, if it is 16550`
445
446			`jitter =`
447			`in msecs... time to block, -1 to disable it`
448
449			`vapi_id =`
450			`VAPI id of this instance`
451			`*/`
452	608	simons	`/*`
453	516	markom	`section uart`
454			`nuarts = 1`
455
456			`device 0`
457			`baseaddr = 0x80000000`
458			`irq = 2`
459			`rxfile = "/tmp/uart0.rx"`
460			`txfile = "/tmp/uart0.tx"`
461			`jitter = -1 /* async behaviour */`
462			`enddevice`
463			`end`
464	608	simons	`*/`
465	516	markom
466			`/* DMA SECTION`
467
468			`This section configures DMAs`
469
470			`enabled = 0/1`
471			`whether DMAs are enabled`
472
473			`ndmas =`
474			`make specified number of instances, configure each`
475			`instance within device - enddevice construct.`
476
477			`instance specific:`
478			`baseaddr =`
479			`address of first DMA register for this device`
480
481			`irq =`
482			`irq number for this device`
483
484			`vapi_id =`
485			`VAPI id of this instance`
486			`*/`
487	608	simons	`/*`
488	516	markom	`section dma`
489			`ndmas = 1`
490
491			`device 0`
492			`baseaddr = 0x90000000`
493			`irq = 4`
494			`enddevice`
495			`end`
496	608	simons	`*/`
497	516	markom
498			`/* ETHERNET SECTION`
499
500			`This section configures ethernets`
501
502			`enabled = 0/1`
503			`whether ethernets are enabled`
504
505			`nethernets =`
506			`make specified number of instances, configure each`
507			`instance within device - enddevice construct.`
508
509			`instance specific:`
510			`baseaddr =`
511			`address of first ethernet register for this device`
512
513			`dma =`
514			`which controller is this ethernet "connected" to`
515
516			`rx_channel =`
517			`DMA channel used for RX`
518
519			`tx_channel =`
520			`DMA channel used for TX`
521
522			`rx_file = ""`
523			`filename, where to read data from`
524
525			`tx_file = ""`
526			`filename, where to write data to`
527
528			`vapi_id =`
529			`VAPI id of this instance`
530			`*/`
531	608	simons	`/*`
532	516	markom	`section ethernet`
533			`nethernets = 1`
534
535			`device 0`
536			`baseaddr = 0x88000000`
537			`dma = 0`
538			`tx_channel = 0`
539			`rx_channel = 1`
540			`rxfile = "/tmp/eth0.rx"`
541			`txfile = "/tmp/eth0.tx"`
542			`enddevice`
543			`end`
544	608	simons	`*/`
545	516	markom	`/* TICK TIMER SECTION`
546
547			`This section configures tick timer`
548
549			`enabled = 0/1`
550			`whether tick timer is enabled`
551
552			`irq =`
553			`irq number`
554			`*/`
555
556			`section tick`
557	608	simons	`enabled = 1`
558	516	markom	`end`