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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [except_test.cfg] - Blame information for rev 730

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Line No. Rev Author Line
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section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  nmemories = 3
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  device 0
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    name = "RAM1"
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    ce = 0
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    baseaddr = 0x40000000
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    size = 0x00200000
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    delayr = 1
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    delayw = 2
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  enddevice
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  device 1
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    name = "FLASH"
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    ce = 1
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    baseaddr = 0x00000000
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    size = 0x00200000
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    delayr = 10
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    delayw = -1
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  enddevice
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  device 2
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    name = "RAM2"
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    ce = 2
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    baseaddr = 0x80000000
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    size = 0x00200000
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    delayr = 1
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    delayw = 2
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  enddevice
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end
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section immu
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  enabled = 1
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  nsets = 32
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  nways = 1
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  pagesize = 8192
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end
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section dmmu
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  enabled = 1
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  nsets = 32
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  nways = 1
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  pagesize = 8192
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end
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section ic
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  enabled = 0
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  nsets = 512
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  nways = 1
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  blocksize = 16
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end
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section dc
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  enabled = 0
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  nsets = 512
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  nways = 1
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  blocksize = 16
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end
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section sim
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  history = 1
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  exe_log = 1
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  exe_log_fn = "executed.log"
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  clkcycle = 4ns
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end

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