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1254 |
phoenix |
#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors:hmt
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// Travis C. Furrer <furrer@mit.edu>
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// Date: 2000-05-08
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_sa11x0.h>
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#include <cyg/hal/hal_mmu.h>
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//-----------------------------------------------------------------------------
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// FIXME: This definition forces the IO flash driver to use a
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// known-good procedure for fiddling flash before calling flash device
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// driver functions. The procedure breaks on other platform/driver
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// combinations though so is depricated. Hence this definition.
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//
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// If you work on this target, please try to remove this definition
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// and verify that the flash driver still works (both from RAM and
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// flash). If it does, remove the definition and this comment for good
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// [and the old macro definition if this happens to be the last client
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// of that code].
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#if defined(CYGPKG_HAL_ARM_SA11X0_ASSABET) \
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|| defined(CYGPKG_HAL_ARM_SA11X0_SA1100MM)
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# define HAL_FLASH_CACHES_OLD_MACROS
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#endif
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//-----------------------------------------------------------------------------
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// Cache dimensions
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#define HAL_ICACHE_SIZE SA11X0_ICACHE_SIZE
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#define HAL_ICACHE_LINE_SIZE SA11X0_ICACHE_LINESIZE_BYTES
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#define HAL_ICACHE_WAYS SA11X0_ICACHE_WAYS
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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#define HAL_DCACHE_SIZE SA11X0_DCACHE_SIZE
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#define HAL_DCACHE_LINE_SIZE SA11X0_DCACHE_LINESIZE_BYTES
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#define HAL_DCACHE_WAYS SA11X0_DCACHE_WAYS
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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// FIXME: much of the code below should make better use of
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// the definitions from hal_mmu.h
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x1000;" \
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"orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
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/* that MMU and alignment faults */ \
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/* are enabled) */ \
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"mcr p15,0,r1,c1,c0,0" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the instruction cache (and invalidate it, required semanitcs)
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#define HAL_ICACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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/* this macro can discard dirty cache lines (N/A for ICache) */ \
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asm volatile ( \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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"mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// (which includes flushing out pending writes)
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#define HAL_ICACHE_SYNC() \
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CYG_MACRO_START \
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HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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CYG_MACRO_END
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// This feature is not available on the SA11X0.
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// This feature is not available on the SA11X0.
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// This feature is not available on the SA11X0.
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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// This feature is not available on the SA11X0.
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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// This feature is not available on the SA11X0.
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x000F;" /* enable DCache (also ensures */ \
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/* the MMU, alignment faults, and */ \
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/* write buffer are enabled) */ \
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"mcr p15,0,r1,c1,c0,0" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the data cache (and invalidate it, required semanitcs)
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \
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/* but not MMU and alignment faults */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register int reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0;" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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CYG_MACRO_END
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// Flush the entire dcache (and then both TLBs, just in case)
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#define HAL_DCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
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asm volatile ( \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c6,0;" \
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"mcr p15,0,r1,c8,c7,0;" \
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: \
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: \
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: "r1","memory" ); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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/* This is slightly naff in that the only way to force a dirty */ \
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/* line out is by loading other data into its slot, so */ \
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/* invalidating that slot. */ \
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asm volatile ( \
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"mov r0, #0xE0000000;" /* SA11X0 zeros bank (128Mb) */ \
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"add r1, r0, #0x2000;" /* We read 8kB of it */ \
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"667: " \
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"ldr r2, [r0], #32;" \
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"teq r1, r0;" \
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"bne 667b;" \
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"mov r0,#0;" \
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"mcr p15,0,r0,c7,c6,0;" /* flush DCache */ \
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"mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
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: \
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: \
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: "r0","r1","r2" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// This feature is not available on the SA11X0.
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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// This feature is not available on the SA11X0.
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| 289 |
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#define HAL_DCACHE_WRITETHRU_MODE 0
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#define HAL_DCACHE_WRITEBACK_MODE 1
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| 292 |
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// Get the current writeback mode - or only writeback mode if fixed
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| 293 |
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#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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_mode_ = HAL_DCACHE_WRITEBACK_MODE; \
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CYG_MACRO_END
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| 297 |
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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| 299 |
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// This feature is not available on the SA11X0.
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// This feature is not available on the SA11X0.
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| 305 |
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| 306 |
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// Unlock entire cache
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| 307 |
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//#define HAL_DCACHE_UNLOCK_ALL()
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// This feature is not available on the SA11X0.
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| 309 |
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| 310 |
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//-----------------------------------------------------------------------------
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| 311 |
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// Data cache line control
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| 312 |
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| 313 |
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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| 315 |
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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| 316 |
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// This feature is not available on the SA11X0.
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| 317 |
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| 318 |
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// Write dirty cache lines to memory and invalidate the cache entries
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| 319 |
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// for the given address range.
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| 320 |
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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| 321 |
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CYG_MACRO_START \
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| 322 |
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HAL_DCACHE_STORE( _base_ , _size_ ); \
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| 323 |
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HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
|
| 324 |
|
|
CYG_MACRO_END
|
| 325 |
|
|
|
| 326 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 327 |
|
|
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
|
| 328 |
|
|
CYG_MACRO_START \
|
| 329 |
|
|
register int addr, enda; \
|
| 330 |
|
|
for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
|
| 331 |
|
|
enda = (int)(_base_) + (_size_); \
|
| 332 |
|
|
addr < enda ; \
|
| 333 |
|
|
addr += HAL_DCACHE_LINE_SIZE ) \
|
| 334 |
|
|
{ \
|
| 335 |
|
|
asm volatile ( \
|
| 336 |
|
|
"mcr p15,0,%0,c7,c6,1;" /* flush entry away */ \
|
| 337 |
|
|
: \
|
| 338 |
|
|
: "r"(addr) \
|
| 339 |
|
|
: "memory" \
|
| 340 |
|
|
); \
|
| 341 |
|
|
} \
|
| 342 |
|
|
CYG_MACRO_END
|
| 343 |
|
|
|
| 344 |
|
|
// Write dirty cache lines to memory for the given address range.
|
| 345 |
|
|
#define HAL_DCACHE_STORE( _base_ , _size_ ) \
|
| 346 |
|
|
CYG_MACRO_START \
|
| 347 |
|
|
register int addr, enda; \
|
| 348 |
|
|
for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
|
| 349 |
|
|
enda = (int)(_base_) + (_size_); \
|
| 350 |
|
|
addr < enda ; \
|
| 351 |
|
|
addr += HAL_DCACHE_LINE_SIZE ) \
|
| 352 |
|
|
{ \
|
| 353 |
|
|
asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */ \
|
| 354 |
|
|
: \
|
| 355 |
|
|
: "r"(addr) \
|
| 356 |
|
|
: "memory" \
|
| 357 |
|
|
); \
|
| 358 |
|
|
} \
|
| 359 |
|
|
/* and also drain the write buffer */ \
|
| 360 |
|
|
asm volatile ( \
|
| 361 |
|
|
"mov r1,#0;" \
|
| 362 |
|
|
"mcr p15,0,r1,c7,c10,4;" \
|
| 363 |
|
|
: \
|
| 364 |
|
|
: \
|
| 365 |
|
|
: "r1", "memory" /* Clobber list */ \
|
| 366 |
|
|
); \
|
| 367 |
|
|
CYG_MACRO_END
|
| 368 |
|
|
|
| 369 |
|
|
// Preread the given range into the cache with the intention of reading
|
| 370 |
|
|
// from it later.
|
| 371 |
|
|
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
|
| 372 |
|
|
// This feature is available on the SA11X0, but due to tricky
|
| 373 |
|
|
// coherency issues with the read buffer (see SA11X0 developer's
|
| 374 |
|
|
// manual page 6-7) we don't bother to implement it here.
|
| 375 |
|
|
|
| 376 |
|
|
// Preread the given range into the cache with the intention of writing
|
| 377 |
|
|
// to it later.
|
| 378 |
|
|
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
|
| 379 |
|
|
// This feature is not available on the SA11X0.
|
| 380 |
|
|
|
| 381 |
|
|
// Allocate and zero the cache lines associated with the given range.
|
| 382 |
|
|
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
|
| 383 |
|
|
// This feature is not available on the SA11X0.
|
| 384 |
|
|
|
| 385 |
|
|
//-----------------------------------------------------------------------------
|
| 386 |
|
|
// Now include the details of the platform's Memory Map setup:
|
| 387 |
|
|
|
| 388 |
|
|
#include <cyg/hal/plf_mmap.h>
|
| 389 |
|
|
|
| 390 |
|
|
// and define the (considerably less efficient) routines that are available
|
| 391 |
|
|
// for testing the actual memory map in force.
|
| 392 |
|
|
|
| 393 |
|
|
externC cyg_uint32 hal_virt_to_phys_address( cyg_uint32 vaddr );
|
| 394 |
|
|
externC cyg_uint32 hal_phys_to_virt_address( cyg_uint32 paddr );
|
| 395 |
|
|
externC cyg_uint32 hal_virt_to_uncached_address( cyg_uint32 vaddr );
|
| 396 |
|
|
|
| 397 |
|
|
//-----------------------------------------------------------------------------
|
| 398 |
|
|
#endif // ifndef CYGONCE_HAL_CACHE_H
|
| 399 |
|
|
// End of hal_cache.h
|
