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phoenix |
#ifndef CYGONCE_HAL_IOP310_H
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#define CYGONCE_HAL_IOP310_H
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/*=============================================================================
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//
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// hal_iop310.h
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//
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// HAL Description of IOP310 (IQ80200/IQ80310) control registers, etc.
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors: msalter, gthomas
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// Date: 2000-10-10
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// Purpose: Intel IOP310 hardware description
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// Description:
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// Usage: #include <cyg/hal/hal_iop310.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <cyg/hal/hal_xscale.h>
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#ifndef __ASSEMBLER__
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// Platform specific initializations
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extern void hal_plf_hardware_init(void);
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#endif
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// Serial ports
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#define IOP310_SERIAL_PORT_A 0xFE800000
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#define IOP310_SERIAL_PORT_B 0xFE810000
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#define DCACHE_FLUSH_AREA 0xc0000000
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// Addresses of the left and right 7-segment display
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#define DISPLAY_LEFT 0xFE840000
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#define DISPLAY_RIGHT 0xFE850000
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// 7-segment encodings for the hex display
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#define DISPLAY_0 0xc0
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#define DISPLAY_1 0xf9
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#define DISPLAY_2 0xa4
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#define DISPLAY_3 0xb0
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#define DISPLAY_4 0x99
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#define DISPLAY_5 0x92
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#define DISPLAY_6 0x82
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#define DISPLAY_7 0xF8
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#define DISPLAY_8 0x80
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#define DISPLAY_9 0x90
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#define DISPLAY_A 0x88
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#define DISPLAY_B 0x83
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#define DISPLAY_C 0xa7
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#define DISPLAY_D 0xa1
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#define DISPLAY_E 0x86
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#define DISPLAY_F 0x8e
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#ifndef iop310_is_host
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/* Backplane Detect Register */
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#define BACKPLANE_DET_REG ((volatile unsigned char *)0xfe870000)
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# define BP_HOST_BIT 0x1
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#define iop310_is_host() (*BACKPLANE_DET_REG & BP_HOST_BIT)
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#endif
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// XINT3 mask register
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#define X3ISR_REG ((volatile unsigned char *)0xfe820000)
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#define X3MASK_REG ((volatile unsigned char *)0xfe860000)
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# define XINT3_TIMER 0x01
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# define XINT3_ETHERNET 0x02
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# define XINT3_UART_1 0x04
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# define XINT3_UART_2 0x08
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# define XINT3_PCI_INTD 0x10
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/* PAL-based external timer definitions */
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#define TIMER_LA0_REG_ADDR ((volatile unsigned char *)0xfe880000)
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#define TIMER_LA1_REG_ADDR ((volatile unsigned char *)0xfe890000)
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#define TIMER_LA2_REG_ADDR ((volatile unsigned char *)0xfe8a0000)
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#define TIMER_LA3_REG_ADDR ((volatile unsigned char *)0xfe8b0000)
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#define TIMER_ENABLE_REG_ADDR ((volatile unsigned char *)0xfe8c0000)
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#define TIMER_COUNT_MASK 0x5f /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
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#define TIMER_CNT_ENAB 0x1
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#define TIMER_INT_ENAB 0x2
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#define EXT_TIMER_CLK_FREQ 33000000 /* external timer runs at 33 MHz */
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#define TICKS_10MSEC 100 /* 10msec = 100 ticks/sec */
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#define EXT_TIMER_10MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
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#define TICKS_5MSEC 200 /* 5msec = 200 ticks/sec */
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#define EXT_TIMER_5MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_5MSEC)
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#define EXT_TIMER_CNT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
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#define EXT_TIMER_CNT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
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#define EXT_TIMER_INT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
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#define EXT_TIMER_INT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)
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// Companion chip MCU registers
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#define MMR_BASE 0x00001500
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#define SDIR_OFF 0x00000000
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#define SDCR_OFF 0x00000004
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#define SDBR_OFF 0x00000008
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#define SBR0_OFF 0x0000000C
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#define SBR1_OFF 0x00000010
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#define ECCR_OFF 0x00000034
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#define FEBR1_OFF 0x00000050
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#define FBSR1_OFF 0x00000058
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#define FWSR0_OFF 0x0000005C
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#define FWSR1_OFF 0x00000060
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#define RFR_OFF 0x00000068
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// MCU Register Values
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#define MRS_CAS_LAT_2 0x00000000
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#define MRS_CAS_LAT_3 0x00000001
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#define MRS_PRECHRG 0x00000002
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#define MRS_NO_OP 0x00000003
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#define MRS_AUTO_RFRSH 0x00000004
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#define MRS_NORM_OP 0x00000006
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#define MRS_NOP_DELAY 0x00004000
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#define SDCR_INIT_VAL 0x00000aa0 // was 0x14
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#define SBR0_INIT_VAL 0x00000008 // 32 Meg Boundary (64 mbit device)
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#define SBR1_INIT_VAL 0x00000008 // 32 Meg Boundary (64 mbit device)
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#define ECCR_INIT_VAL 0x0000000C // ECC enabled, correction on and no reporting
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#define RFR_INIT_VAL 0x00000600 // Initial Refresh Rate
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#define FBSR1_INIT_VAL 0x00000040 // 8MB Bank Size
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#define FWSR0_INIT_VAL 0x00000001 // 1ws add-data (needed for PP state machine), 0ws recovery
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#define FWSR1_INIT_VAL 0x00000000 // 0ws add-data, 0ws recovery
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/**************************
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* I2C Bus Interface Unit *
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**************************/
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/* Processor I2C Device ID */
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#define I2C_DEVID 0x02 /* I2C slave address to which the unit responds when in slave-receive mode */
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/* Timeout limit for SDRAM EEPROM to respond */
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#define I2C_TIMOUT 0x1000000 /* bumped this way up...used to be 0x100000*/
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/* Control Register */
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#define ICR_ADDR 0x00001680 /* Address */
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#define ICR_START 0x0001 /* 1:send a Start condition to the I2C when in master mode */
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#define ICR_STOP 0x0002 /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
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#define ICR_ACK 0x0004 /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
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#define ICR_TRANSFER 0x0008 /* 1:send/receive byte, 0:cleared by I2C unit when done */
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#define ICR_ABORT 0x0010 /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
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#define ICR_SCLENB 0x0020 /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
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#define ICR_ENB 0x0040 /* I2C unit: 1:Enabled, 0:Disabled */
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#define ICR_GCALL 0x0080 /* General Call: 1:Disabled, 0:Enabled */
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#define ICR_IEMPTY 0x0100 /* 1: IDBR Transmit Empty Interrupt Enable */
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#define ICR_IFULL 0x0200 /* 1: IDBR Receive Full Interrupt Enable */
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#define ICR_IERR 0x0400 /* 1: Bus Error Interrupt Enable */
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#define ICR_ISTOP 0x0800 /* 1: Slave Stop Detected Interrupt Enable */
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#define ICR_IARB 0x1000 /* 1: Arbitration Loss Detected Interrupt Enable */
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#define ICR_ISADDR 0x2000 /* 1: Slave Address Detected Interrupt Enable */
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#define ICR_RESET 0x4000 /* 1: I2C unit reset */
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/* Status Register */
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#define ISR_ADDR 0x00001684 /* Address */
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#define ISR_RWMODE 0x0001 /* 1: I2C in master receive = slave transmit mode */
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#define ISR_ACK 0x0002 /* 1: I2C received/sent a Nack, 0: Ack */
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#define ISR_BUSY 0x0004 /* 1: Processor's I2C unit busy */
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#define ISR_BUSBUSY 0x0008 /* 1: I2C bus busy. Processor's I2C unit not involved */
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#define ISR_STOP 0x0010 /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
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#define ISR_ARB 0x0020 /* 1: Arbitration Loss Detected */
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#define ISR_EMPTY 0x0040 /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
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#define ISR_FULL 0x0080 /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
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#define ISR_GCALL 0x0100 /* 1: I2C unit received a General Call address */
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#define ISR_SADDR 0x0200 /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
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#define ISR_ERROR 0x0400 /* Bit set by unit when a Bus Error detected */
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#define ISAR_ADDR 0x00001688 /* Address of the I2C Slave Address Register */
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#define IDBR_ADDR 0x0000168C /* Address of the I2C Data Buffer Register */
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#define IDBR_MASK 0x000000ff
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#define IDBR_MODE 0x01
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#define ICCR_ADDR 0x00001690 /* Address of the I2C Clock Control Register */
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#define IBMR_ADDR 0x00001694 /* Address of the I2C Bus Monitor Register */
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/* SDRAM configuration */
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/* SDRAM bank size values (SPD << 2) */
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#define RAM_0MEG
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#define RAM_4MEG 4
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#define RAM_8MEG 8
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#define RAM_16MEG 16
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#define RAM_32MEG 32
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#define RAM_64MEG 64
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#define RAM_128MEG 128
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#define RAM_256MEG 256
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/* SBR register definitions (valid bits are [7:3])*/
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#define SBR_32MEG 0x08
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#define SBR_64MEG 0x10
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#define SBR_128MEG 0x20
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#define SBR_256MEG 0x40
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/* Drive Strengths - assume single DIMM configuration */
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#define SDCR_1BANK_X16 0x0aa0
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#define SDCR_2BANK_X16 0x12c8
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#define SDCR_1BANK_X8 0x1520
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#define SDCR_2BANK_X8 0x1548
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/* SDRAM PD bytes */
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#define BANKCNT_BYTE 0x06 /* Byte #5 of SPD: number of module banks */
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#define SDRAM_WIDTH_BYTE 0x0e /* Byte #13 of SPD: DRAM width */
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#define BANKSZ_BYTE 0x20 /* Byte #31 of SPD: module bank density */
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#define CHECKSUM_BYTE 0x40 /* Byte #63 of SPD: checksum for bytes 0-62 */
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#define CONFIG_BYTE 0x0C /* Byte #11 of SPD: DIMM configuration type (Parity or not, EEC) */
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#define SDRAM_DEVID 0xA2 /* SDRAM Device ID */
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// Yavapai PCI and Peripheral Interrupt Unit
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/*** Yavapai Registers ***/
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/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
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#define VIDR_ADDR 0x00001000
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#define DIDR_ADDR 0x00001002
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#define PCR_ADDR 0x00001004
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#define PSR_ADDR 0x00001006
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#define RIDR_ADDR 0x00001008
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#define CCR_ADDR 0x00001009
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#define CLSR_ADDR 0x0000100C
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#define PLTR_ADDR 0x0000100D
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#define HTR_ADDR 0x0000100E
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/* Reserved 0x0000100F through 0x00001017 */
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#define PBNR_ADDR 0x00001018
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#define SBNR_ADDR 0x00001019
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#define SUBBNR_ADDR 0x0000101A
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#define SLTR_ADDR 0x0000101B
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#define IOBR_ADDR 0x0000101C
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#define IOLR_ADDR 0x0000101D
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#define SSR_ADDR 0x0000101E
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#define MBR_ADDR 0x00001020
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#define MLR_ADDR 0x00001022
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#define PMBR_ADDR 0x00001024
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#define PMLR_ADDR 0x00001026
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/* Reserved 0x00001028 through 0x00001033 */
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#define BSVIR_ADDR 0x00001034
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#define BSIR_ADDR 0x00001036
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/* Reserved 0x00001038 through 0x0000103D */
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#define BCR_ADDR 0x0000103E
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#define EBCR_ADDR 0x00001040
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#define SISR_ADDR 0x00001042
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#define PBISR_ADDR 0x00001044
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#define SBISR_ADDR 0x00001048
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#define SACR_ADDR 0x0000104C
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#define PIRSR_ADDR 0x00001050
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#define SIOBR_ADDR 0x00001054
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#define SIOLR_ADDR 0x00001055
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#define SCCR_ADDR 0x00001056 /* EAS inconsistent */
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#define SMBR_ADDR 0x00001058
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#define SMLR_ADDR 0x0000105A
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#define SDER_ADDR 0x0000105C
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#define QCR_ADDR 0x0000105E
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#define CDTR_ADDR 0x00001060 /* EAS inconsistent */
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/* Reserved 0x00001064 through 0x000010FFH */
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/* Performance Monitoring Unit 0000 1100H through 0000 11FFH */
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#define GTMR_ADDR 0x00001100
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#define ESR_ADDR 0x00001104
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#define EMISR_ADDR 0x00001108
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/* Reserved 0x0000110C */ /* EAS inconsistent */
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#define GTSR_ADDR 0x00001110 /* EAS inconsistent */
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#define PECR1_ADDR 0x00001114 /* EAS inconsistent */
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#define PECR2_ADDR 0x00001118 /* EAS inconsistent */
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#define PECR3_ADDR 0x0000111C /* EAS inconsistent */
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#define PECR4_ADDR 0x00001120 /* EAS inconsistent */
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#define PECR5_ADDR 0x00001124 /* EAS inconsistent */
|
301 |
|
|
#define PECR6_ADDR 0x00001128 /* EAS inconsistent */
|
302 |
|
|
#define PECR7_ADDR 0x0000112C /* EAS inconsistent */
|
303 |
|
|
#define PECR8_ADDR 0x00001130 /* EAS inconsistent */
|
304 |
|
|
#define PECR9_ADDR 0x00001134 /* EAS inconsistent */
|
305 |
|
|
#define PECR10_ADDR 0x00001138 /* EAS inconsistent */
|
306 |
|
|
#define PECR11_ADDR 0x0000113C /* EAS inconsistent */
|
307 |
|
|
#define PECR12_ADDR 0x00001140 /* EAS inconsistent */
|
308 |
|
|
#define PECR13_ADDR 0x00001144 /* EAS inconsistent */
|
309 |
|
|
#define PECR14_ADDR 0x00001148 /* EAS inconsistent */
|
310 |
|
|
/* Reserved 0x0000104C through 0x000011FFH */ /* EAS inconsistent */
|
311 |
|
|
|
312 |
|
|
/* Address Translation Unit 0000 1200H through 0000 12FFH */
|
313 |
|
|
#define ATUVID_ADDR 0x00001200
|
314 |
|
|
#define ATUDID_ADDR 0x00001202
|
315 |
|
|
#define PATUCMD_ADDR 0x00001204
|
316 |
|
|
#define PATUSR_ADDR 0x00001206
|
317 |
|
|
#define ATURID_ADDR 0x00001208
|
318 |
|
|
#define ATUCCR_ADDR 0x00001209
|
319 |
|
|
#define ATUCLSR_ADDR 0x0000120C
|
320 |
|
|
#define ATULT_ADDR 0x0000120D
|
321 |
|
|
#define ATUHTR_ADDR 0x0000120E
|
322 |
|
|
#define ATUBISTR_ADDR 0x0000120F
|
323 |
|
|
#define PIABAR_ADDR 0x00001210
|
324 |
|
|
/* Reserved 0x00001214 through 0x0000122B */
|
325 |
|
|
#define ASVIR_ADDR 0x0000122C
|
326 |
|
|
#define ASIR_ADDR 0x0000122E
|
327 |
|
|
#define ERBAR_ADDR 0x00001230
|
328 |
|
|
/* Reserved 0x00001234 */
|
329 |
|
|
/* Reserved 0x00001238 */
|
330 |
|
|
#define ATUILR_ADDR 0x0000123C
|
331 |
|
|
#define ATUIPR_ADDR 0x0000123D
|
332 |
|
|
#define ATUMGNT_ADDR 0x0000123E
|
333 |
|
|
#define ATUMLAT_ADDR 0x0000123F
|
334 |
|
|
#define PIALR_ADDR 0x00001240
|
335 |
|
|
#define PIATVR_ADDR 0x00001244
|
336 |
|
|
#define SIABAR_ADDR 0x00001248
|
337 |
|
|
#define SIALR_ADDR 0x0000124C
|
338 |
|
|
#define SIATVR_ADDR 0x00001250
|
339 |
|
|
#define POMWVR_ADDR 0x00001254
|
340 |
|
|
/* Reserved 0x00001258 */
|
341 |
|
|
#define POIOWVR_ADDR 0x0000125C
|
342 |
|
|
#define PODWVR_ADDR 0x00001260
|
343 |
|
|
#define POUDR_ADDR 0x00001264
|
344 |
|
|
#define SOMWVR_ADDR 0x00001268
|
345 |
|
|
#define SOIOWVR_ADDR 0x0000126C
|
346 |
|
|
/* Reserved 0x00001270 */
|
347 |
|
|
#define ERLR_ADDR 0x00001274
|
348 |
|
|
#define ERTVR_ADDR 0x00001278
|
349 |
|
|
/* Reserved 0x0000127C */
|
350 |
|
|
/* Reserved 0x00001280 */
|
351 |
|
|
/* Reserved 0x00001284 */
|
352 |
|
|
#define ATUCR_ADDR 0x00001288
|
353 |
|
|
/* Reserved 0x0000128C */
|
354 |
|
|
#define PATUISR_ADDR 0x00001290
|
355 |
|
|
#define SATUISR_ADDR 0x00001294
|
356 |
|
|
#define SATUCMD_ADDR 0x00001298
|
357 |
|
|
#define SATUSR_ADDR 0x0000129A
|
358 |
|
|
#define SODWVR_ADDR 0x0000129C
|
359 |
|
|
#define SOUDR_ADDR 0x000012A0
|
360 |
|
|
#define POCCAR_ADDR 0x000012A4
|
361 |
|
|
#define SOCCAR_ADDR 0x000012A8
|
362 |
|
|
#define POCCDR_ADDR 0x000012AC
|
363 |
|
|
#define SOCCDR_ADDR 0x000012B0
|
364 |
|
|
#define PAQCR_ADDR 0x000012B4
|
365 |
|
|
#define SAQCR_ADDR 0x000012B8
|
366 |
|
|
#define PAIMR_ADDR 0x000012BC
|
367 |
|
|
#define SAIMR_ADDR 0x000012C0
|
368 |
|
|
/* Reserved 0x000012C4 through 0x000012FF */
|
369 |
|
|
|
370 |
|
|
/* Messaging Unit 0000 1300H through 0000 130FH */
|
371 |
|
|
#define IMR0_ADDR 0x00001310
|
372 |
|
|
#define IMR1_ADDR 0x00001314
|
373 |
|
|
#define OMR0_ADDR 0x00001318
|
374 |
|
|
#define OMR1_ADDR 0x0000131C
|
375 |
|
|
#define IDR_ADDR 0x00001320
|
376 |
|
|
#define IISR_ADDR 0x00001324
|
377 |
|
|
#define IIMR_ADDR 0x00001328
|
378 |
|
|
#define ODR_ADDR 0x0000132C
|
379 |
|
|
#define OISR_ADDR 0x00001330
|
380 |
|
|
#define OIMR_ADDR 0x00001334
|
381 |
|
|
/* Reserved 0x00001338 through 0x0000134F */
|
382 |
|
|
#define MUCR_ADDR 0x00001350
|
383 |
|
|
#define QBAR_ADDR 0x00001354
|
384 |
|
|
/* Reserved 0x00001358 */
|
385 |
|
|
/* Reserved 0x0000135C */
|
386 |
|
|
#define IFHPR_ADDR 0x00001360
|
387 |
|
|
#define IFTPR_ADDR 0x00001364
|
388 |
|
|
#define IPHPR_ADDR 0x00001368
|
389 |
|
|
#define IPTPR_ADDR 0x0000136C
|
390 |
|
|
#define OFHPR_ADDR 0x00001370
|
391 |
|
|
#define OFTPR_ADDR 0x00001374
|
392 |
|
|
#define OPHPR_ADDR 0x00001378
|
393 |
|
|
#define OPTPR_ADDR 0x0000137C
|
394 |
|
|
#define IAR_ADDR 0x00001380
|
395 |
|
|
/* Reserved 0x00001384 through 0x000013FF */
|
396 |
|
|
|
397 |
|
|
/* DMA Controller 0000 1400H through 0000 14FFH */
|
398 |
|
|
#define CCR0_ADDR 0x00001400
|
399 |
|
|
#define CSR0_ADDR 0x00001404
|
400 |
|
|
/* Reserved 0x00001408 */
|
401 |
|
|
#define DAR0_ADDR 0x0000140C
|
402 |
|
|
#define NDAR0_ADDR 0x00001410
|
403 |
|
|
#define PADR0_ADDR 0x00001414
|
404 |
|
|
#define PUADR0_ADDR 0x00001418
|
405 |
|
|
#define LADR0_ADDR 0x0000141C
|
406 |
|
|
#define BCR0_ADDR 0x00001420
|
407 |
|
|
#define DCR0_ADDR 0x00001424
|
408 |
|
|
/* Reserved 0x00001428 through 0x0000143F */
|
409 |
|
|
#define CCR1_ADDR 0x00001440
|
410 |
|
|
#define CSR1_ADDR 0x00001444
|
411 |
|
|
/* Reserved 0x00001448 */
|
412 |
|
|
#define DAR1_ADDR 0x0000144C
|
413 |
|
|
#define NDAR1_ADDR 0x00001450
|
414 |
|
|
#define PADR1_ADDR 0x00001454
|
415 |
|
|
#define PUADR1_ADDR 0x00001458
|
416 |
|
|
#define LADR1_ADDR 0x0000145C
|
417 |
|
|
#define BCR1_ADDR 0x00001460
|
418 |
|
|
#define DCR1_ADDR 0x00001464
|
419 |
|
|
/* Reserved 0x00001468 through 0x0000147F */
|
420 |
|
|
#define CCR2_ADDR 0x00001480
|
421 |
|
|
#define CSR2_ADDR 0x00001484
|
422 |
|
|
/* Reserved 0x00001488 */
|
423 |
|
|
#define DAR2_ADDR 0x0000148C
|
424 |
|
|
#define NDAR2_ADDR 0x00001490
|
425 |
|
|
#define PADR2_ADDR 0x00001494
|
426 |
|
|
#define PUADR2_ADDR 0x00001498
|
427 |
|
|
#define LADR2_ADDR 0x0000149C
|
428 |
|
|
#define BCR2_ADDR 0x000014A0
|
429 |
|
|
#define DCR2_ADDR 0x000014A4
|
430 |
|
|
/* Reserved 0x000014A8 through 0x000014FF */
|
431 |
|
|
|
432 |
|
|
/* Memory Controller 0000 1500H through 0000 15FFH */
|
433 |
|
|
#define SDIR_ADDR 0x00001500
|
434 |
|
|
#define SDCR_ADDR 0x00001504
|
435 |
|
|
#define SDBR_ADDR 0x00001508
|
436 |
|
|
#define SBR0_ADDR 0x0000150C
|
437 |
|
|
#define SBR1_ADDR 0x00001510
|
438 |
|
|
#define SDPR0_ADDR 0x00001514
|
439 |
|
|
#define SDPR1_ADDR 0x00001518
|
440 |
|
|
#define SDPR2_ADDR 0x0000151C
|
441 |
|
|
#define SDPR3_ADDR 0x00001520
|
442 |
|
|
#define SDPR4_ADDR 0x00001524
|
443 |
|
|
#define SDPR5_ADDR 0x00001528
|
444 |
|
|
#define SDPR6_ADDR 0x0000152C
|
445 |
|
|
#define SDPR7_ADDR 0x00001530
|
446 |
|
|
#define ECCR_ADDR 0x00001534
|
447 |
|
|
#define ELOG0_ADDR 0x00001538
|
448 |
|
|
#define ELOG1_ADDR 0x0000153C
|
449 |
|
|
#define ECAR0_ADDR 0x00001540
|
450 |
|
|
#define ECAR1_ADDR 0x00001544
|
451 |
|
|
#define ECTST_ADDR 0x00001548
|
452 |
|
|
#define FEBR0_ADDR 0x0000154C
|
453 |
|
|
#define FEBR1_ADDR 0x00001550
|
454 |
|
|
#define FBSR0_ADDR 0x00001554
|
455 |
|
|
#define FBSR1_ADDR 0x00001558
|
456 |
|
|
#define FWSR0_ADDR 0x0000155C
|
457 |
|
|
#define FWSR1_ADDR 0x00001560
|
458 |
|
|
#define MCISR_ADDR 0x00001564
|
459 |
|
|
#define RFR_ADDR 0x00001568
|
460 |
|
|
/* Reserved 0x0000156C through 0x000015FF */
|
461 |
|
|
|
462 |
|
|
/* Arbitration Control Unit 0000 1600H through 0000 167FH */
|
463 |
|
|
#define IACR_ADDR 0x00001600
|
464 |
|
|
#define MLTR_ADDR 0x00001604
|
465 |
|
|
#define MTTR_ADDR 0x00001608
|
466 |
|
|
/* Reserved 0x0000160C through 0x0000163F */
|
467 |
|
|
|
468 |
|
|
/* Bus Interface Control Unit 0000 1640H through 0000 167FH */
|
469 |
|
|
#define BIUCR_ADDR 0x00001640
|
470 |
|
|
#define BIUISR_ADDR 0x00001644
|
471 |
|
|
/* Reserved 0x00001648 through 0x0000167F */
|
472 |
|
|
|
473 |
|
|
/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
|
474 |
|
|
#define ICR_ADDR 0x00001680
|
475 |
|
|
#define ISR_ADDR 0x00001684
|
476 |
|
|
#define ISAR_ADDR 0x00001688
|
477 |
|
|
#define IDBR_ADDR 0x0000168C
|
478 |
|
|
#define ICCR_ADDR 0x00001690
|
479 |
|
|
#define IBMR_ADDR 0x00001694
|
480 |
|
|
/* Reserved 0x00001698 through 0x000016FF */
|
481 |
|
|
|
482 |
|
|
/* PCI And Peripheral Interrupt Controller 0000 1700H through 0000 17FFH */
|
483 |
|
|
#define NISR_ADDR 0x00001700
|
484 |
|
|
#define X7ISR_ADDR 0x00001704
|
485 |
|
|
#define X6ISR_ADDR 0x00001708
|
486 |
|
|
#define PDIDR_ADDR 0x00001710 /* EAS inconsistent */
|
487 |
|
|
/* Reserved 0x00001714 through 0x0000177F */
|
488 |
|
|
|
489 |
|
|
/* Application Accelerator Unit 0000 1800H through 0000 18FFH */
|
490 |
|
|
#define ACR_ADDR 0x00001800
|
491 |
|
|
#define ASR_ADDR 0x00001804
|
492 |
|
|
#define ADAR_ADDR 0x00001808
|
493 |
|
|
#define ANDAR_ADDR 0x0000180C
|
494 |
|
|
#define SAR1_ADDR 0x00001810
|
495 |
|
|
#define SAR2_ADDR 0x00001814
|
496 |
|
|
#define SAR3_ADDR 0x00001818
|
497 |
|
|
#define SAR4_ADDR 0x0000181C
|
498 |
|
|
#define DAR_ADDR 0x00001820
|
499 |
|
|
#define ABCR_ADDR 0x00001824
|
500 |
|
|
#define ADCR_ADDR 0x00001828
|
501 |
|
|
#define SAR5_ADDR 0x0000182C
|
502 |
|
|
#define SAR6_ADDR 0x00001830
|
503 |
|
|
#define SAR7_ADDR 0x00001834
|
504 |
|
|
#define SAR8_ADDR 0x00001838
|
505 |
|
|
|
506 |
|
|
/* Reserved 0x0000183C through 0x000018FF */
|
507 |
|
|
|
508 |
|
|
#define X6ISR_REG ((volatile cyg_uint32 *)X6ISR_ADDR)
|
509 |
|
|
# define X6ISR_DIP0 0x01
|
510 |
|
|
# define X6ISR_DIP1 0x02
|
511 |
|
|
# define X6ISR_DIP2 0x04
|
512 |
|
|
# define X6ISR_EMIP 0x10
|
513 |
|
|
# define X6ISR_AAIP 0x20
|
514 |
|
|
|
515 |
|
|
#define X7ISR_REG ((volatile cyg_uint32 *)X7ISR_ADDR)
|
516 |
|
|
# define X7ISR_ISQC 0x02
|
517 |
|
|
# define X7ISR_INDB 0x04
|
518 |
|
|
# define X7ISR_BIST 0x08
|
519 |
|
|
|
520 |
|
|
#define NISR_REG ((volatile cyg_uint32 *)NISR_ADDR)
|
521 |
|
|
# define NISR_MCU 0x01
|
522 |
|
|
# define NISR_PATU 0x02
|
523 |
|
|
# define NISR_SATU 0x04
|
524 |
|
|
# define NISR_PBDG 0x08
|
525 |
|
|
# define NISR_SBDG 0x10
|
526 |
|
|
# define NISR_DMA0 0x20
|
527 |
|
|
# define NISR_DMA1 0x40
|
528 |
|
|
# define NISR_DMA2 0x80
|
529 |
|
|
# define NISR_MU 0x100
|
530 |
|
|
# define NISR_AAU 0x400
|
531 |
|
|
# define NISR_BIU 0x800
|
532 |
|
|
|
533 |
|
|
#define PIRSR_REG REG32(0,PIRSR_ADDR)
|
534 |
|
|
#define IISR_REG REG32(0,IISR_ADDR)
|
535 |
|
|
#define IIMR_REG REG32(0,IIMR_ADDR)
|
536 |
|
|
#define OISR_REG REG32(0,OISR_ADDR)
|
537 |
|
|
#define OIMR_REG REG32(0,OIMR_ADDR)
|
538 |
|
|
#define EMISR_REG REG32(0,EMISR_ADDR)
|
539 |
|
|
#define ISR_REG REG32(0,ISR_ADDR)
|
540 |
|
|
#define GTMR_REG REG32(0,GTMR_ADDR)
|
541 |
|
|
#define ESR_REG REG32(0,ESR_ADDR)
|
542 |
|
|
#define ADCR_REG REG32(0,ADCR_ADDR)
|
543 |
|
|
#define ICR_REG REG32(0,ICR_ADDR)
|
544 |
|
|
#define ATUCR_REG REG32(0,ATUCR_ADDR)
|
545 |
|
|
|
546 |
|
|
#define DCR0_REG REG32(0,DCR0_ADDR)
|
547 |
|
|
#define DCR1_REG REG32(0,DCR1_ADDR)
|
548 |
|
|
#define DCR2_REG REG32(0,DCR2_ADDR)
|
549 |
|
|
|
550 |
|
|
#define ECCR_REG REG32(0,ECCR_ADDR)
|
551 |
|
|
#define MCISR_REG REG32(0,MCISR_ADDR)
|
552 |
|
|
#define ELOG0_REG REG32(0,ELOG0_ADDR)
|
553 |
|
|
#define ELOG1_REG REG32(0,ELOG1_ADDR)
|
554 |
|
|
#define ECAR0_REG REG32(0,ECAR0_ADDR)
|
555 |
|
|
#define ECAR1_REG REG32(0,ECAR1_ADDR)
|
556 |
|
|
|
557 |
|
|
#define PATUISR_REG REG32(0,PATUISR_ADDR)
|
558 |
|
|
#define SATUISR_REG REG32(0,SATUISR_ADDR)
|
559 |
|
|
#define PBISR_REG REG32(0,PBISR_ADDR)
|
560 |
|
|
#define SBISR_REG REG32(0,SBISR_ADDR)
|
561 |
|
|
#define CSR0_REG REG32(0,CSR0_ADDR)
|
562 |
|
|
#define CSR1_REG REG32(0,CSR1_ADDR)
|
563 |
|
|
#define CSR2_REG REG32(0,CSR2_ADDR)
|
564 |
|
|
#define IISR_REG REG32(0,IISR_ADDR)
|
565 |
|
|
#define ASR_REG REG32(0,ASR_ADDR)
|
566 |
|
|
#define BIUISR_REG REG32(0,BIUISR_ADDR)
|
567 |
|
|
|
568 |
|
|
#define PATUSR_REG REG16(0,PATUSR_ADDR)
|
569 |
|
|
#define SATUSR_REG REG16(0,SATUSR_ADDR)
|
570 |
|
|
#define PSR_REG REG16(0,PSR_ADDR)
|
571 |
|
|
#define SSR_REG REG16(0,SSR_ADDR)
|
572 |
|
|
|
573 |
|
|
#define PCR_REG REG16(0,PCR_ADDR)
|
574 |
|
|
#define PBNR_REG REG8(0,PBNR_ADDR)
|
575 |
|
|
#define SBNR_REG REG8(0,SBNR_ADDR)
|
576 |
|
|
#define SUBBNR_REG REG8(0,SUBBNR_ADDR)
|
577 |
|
|
#define BCR_REG REG16(0,BCR_ADDR)
|
578 |
|
|
#define PATUCMD_REG REG32(0,PATUCMD_ADDR)
|
579 |
|
|
#define PIABAR_REG REG32(0,PIABAR_ADDR)
|
580 |
|
|
#define SIABAR_REG REG32(0,SIABAR_ADDR)
|
581 |
|
|
#define SIALR_REG REG32(0,SIALR_ADDR)
|
582 |
|
|
#define SIATVR_REG REG32(0,SIATVR_ADDR)
|
583 |
|
|
#define POMWVR_REG REG32(0,POMWVR_ADDR)
|
584 |
|
|
#define POIOWVR_REG REG32(0,POIOWVR_ADDR)
|
585 |
|
|
#define PODWVR_REG REG32(0,PODWVR_ADDR)
|
586 |
|
|
#define SOMWVR_REG REG32(0,SOMWVR_ADDR)
|
587 |
|
|
#define SOIOWVR_REG REG32(0,SOIOWVR_ADDR)
|
588 |
|
|
#define SATUCMD_REG REG16(0,SATUCMD_ADDR)
|
589 |
|
|
#define SODWVR_REG REG32(0,SODWVR_ADDR)
|
590 |
|
|
|
591 |
|
|
|
592 |
|
|
#define MEMBASE_DRAM 0xa0000000
|
593 |
|
|
|
594 |
|
|
/* primary PCI bus definitions */
|
595 |
|
|
#define PRIMARY_BUS_NUM 0
|
596 |
|
|
#define PRIMARY_MEM_BASE 0x80000000
|
597 |
|
|
#define PRIMARY_DAC_BASE 0x84000000
|
598 |
|
|
#define PRIMARY_IO_BASE 0x90000000
|
599 |
|
|
#define PRIMARY_MEM_LIMIT 0x83ffffff
|
600 |
|
|
#define PRIMARY_DAC_LIMIT 0x87ffffff
|
601 |
|
|
#define PRIMARY_IO_LIMIT 0x9000ffff
|
602 |
|
|
|
603 |
|
|
/* secondary PCI bus definitions */
|
604 |
|
|
#define SECONDARY_BUS_NUM 1
|
605 |
|
|
#define SECONDARY_MEM_BASE 0x88000000
|
606 |
|
|
#define SECONDARY_DAC_BASE 0x8c000000
|
607 |
|
|
#define SECONDARY_IO_BASE 0x90010000
|
608 |
|
|
#define SECONDARY_MEM_LIMIT 0x8bffffff
|
609 |
|
|
#define SECONDARY_DAC_LIMIT 0x8fffffff
|
610 |
|
|
#define SECONDARY_IO_LIMIT 0x9001ffff
|
611 |
|
|
|
612 |
|
|
#ifndef __ASSEMBLER__
|
613 |
|
|
extern unsigned int _80312_EMISR; // Only valid for PEC ISR
|
614 |
|
|
#endif
|
615 |
|
|
|
616 |
|
|
// ------------------------------------------------------------------------
|
617 |
|
|
#ifdef __ASSEMBLER__
|
618 |
|
|
// Macro to perform early setup (in hal_platform_setup.h) of some PCI
|
619 |
|
|
// registers. This should be used prior to the ECC scrup loop to prevent
|
620 |
|
|
// timeouts with some Plug 'n Play PC BIOSes. Before the 'retry' bit is
|
621 |
|
|
// cleared, this macro must setup the vendor/device ID and the primary
|
622 |
|
|
// inbound window BAR to allow primary side access to SDRAM.
|
623 |
|
|
//
|
624 |
|
|
// Input: reg, reg1 -- scratch registers
|
625 |
|
|
// reg_dram_size -- register holding size of SDRAM
|
626 |
|
|
// vendor_id -- PCI vendor ID
|
627 |
|
|
// device_id -- PCI device ID
|
628 |
|
|
|
629 |
|
|
.macro IOP310_EARLY_PCI_SETUP reg0, reg1, reg_dram_size, vendor_id, device_id
|
630 |
|
|
// Setup vendor/device ID for 80312
|
631 |
|
|
ldr \reg0, =ASVIR_ADDR
|
632 |
|
|
ldr \reg1, =\vendor_id
|
633 |
|
|
strh \reg1, [\reg0]
|
634 |
|
|
ldr \reg0, =ASIR_ADDR
|
635 |
|
|
ldr \reg1, =\device_id
|
636 |
|
|
strh \reg1, [\reg0]
|
637 |
|
|
// Make all secondary bus devices private
|
638 |
|
|
ldr \reg0, =SISR_ADDR
|
639 |
|
|
ldr \reg1, =0x03FF
|
640 |
|
|
strh \reg1, [\reg0]
|
641 |
|
|
// Setup primary inbound window into SDRAM
|
642 |
|
|
ldr \reg0, =PIATVR_ADDR
|
643 |
|
|
mov \reg1, #0xa0000000
|
644 |
|
|
str \reg1, [\reg0]
|
645 |
|
|
ldr \reg0, =PIALR_ADDR
|
646 |
|
|
sub \reg1, \reg_dram_size, #1 // dram_size - 1
|
647 |
|
|
mvn \reg1, \reg1 // 1s complement
|
648 |
|
|
str \reg1, [\reg0]
|
649 |
|
|
#ifdef CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY
|
650 |
|
|
ldr \reg0, =EBCR_ADDR
|
651 |
|
|
mov \reg1, #0x0008
|
652 |
|
|
strh \reg1, [\reg0]
|
653 |
|
|
#endif
|
654 |
|
|
.endm
|
655 |
|
|
|
656 |
|
|
#endif // __ASSEMBLER__
|
657 |
|
|
|
658 |
|
|
// ------------------------------------------------------------------------
|
659 |
|
|
|
660 |
|
|
// Override the default MMU off code. This is intended
|
661 |
|
|
// to be included in an inline asm statement.
|
662 |
|
|
#define CYGARC_HAL_MMU_OFF(__paddr__) \
|
663 |
|
|
" mrc p15,0,r0,c1,c0,0\n" \
|
664 |
|
|
" bic r0,r0,#0x05\n" \
|
665 |
|
|
" b 99f\n" \
|
666 |
|
|
" .p2align 5\n" \
|
667 |
|
|
"99:\n" \
|
668 |
|
|
" mcr p15,0,r0,c1,c0,0\n" \
|
669 |
|
|
" mrc p15,0,r0,c2,c0,0\n" \
|
670 |
|
|
" mov r0,r0\n" \
|
671 |
|
|
" sub pc,pc,#4\n" \
|
672 |
|
|
" mov pc," #__paddr__ "\n"
|
673 |
|
|
|
674 |
|
|
|
675 |
|
|
/*---------------------------------------------------------------------------*/
|
676 |
|
|
/* end of hal_iop310.h */
|
677 |
|
|
#endif /* CYGONCE_HAL_IOP310_H */
|