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1254 |
phoenix |
/*=============================================================================
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//
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// hal_diag.c
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//
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// HAL diagnostic output code
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors:msalter, gthomas
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// Date: 2000-10-10
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// Purpose: HAL diagnostic output
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// Description: Implementations of HAL diagnostic output support.
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/hal.h>
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#include <pkgconf/system.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include <cyg/infra/cyg_type.h> // base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/hal_arch.h> // basic machine info
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#include <cyg/hal/hal_intr.h> // interrupt macros
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_if.h> // calling interface API
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#include <cyg/hal/hal_misc.h> // helper functions
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_iop310.h> // Hardware definitions
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#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
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static void cyg_hal_plf_serial_init(void);
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void
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cyg_hal_plf_comms_init(void)
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{
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static int initialized = 0;
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if (initialized)
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return;
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initialized = 1;
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cyg_hal_plf_serial_init();
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}
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//=============================================================================
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// Serial driver
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//=============================================================================
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//-----------------------------------------------------------------------------
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// Based on 3.6864 MHz xtal
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struct baud_config {
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cyg_int32 baud_rate;
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cyg_uint8 msb;
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cyg_uint8 lsb;
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};
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struct baud_config baud_conf[] = {
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{9600, 0x00, 0x0c},
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{19200, 0x00, 0x06},
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{38400, 0x00, 0x03},
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{57600, 0x00, 0x02},
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{115200, 0x00, 0x01}};
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//-----------------------------------------------------------------------------
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// Define the serial registers. The Cogent board is equipped with a 16552
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// serial chip.
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#define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0
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#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
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#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
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#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
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#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
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#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
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#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
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#define CYG_DEV_SERIAL_LCR 0x03 // line control register, write
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#define CYG_DEV_SERIAL_MCR 0x04 // modem control register, write
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#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
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#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
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#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
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// The interrupt enable register bits.
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#define SIO_IER_ERDAI 0x01 // enable received data available irq
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#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
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#define SIO_IER_ELSI 0x04 // enable receiver line status irq
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#define SIO_IER_EMSI 0x08 // enable modem status interrupt
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// The interrupt identification register bits.
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#define SIO_IIR_IP 0x01 // 0 if interrupt pending
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#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
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#define ISR_Tx 0x02
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#define ISR_Rx 0x04
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// The line status register bits.
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#define SIO_LSR_DR 0x01 // data ready
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#define SIO_LSR_OE 0x02 // overrun error
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#define SIO_LSR_PE 0x04 // parity error
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#define SIO_LSR_FE 0x08 // framing error
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#define SIO_LSR_BI 0x10 // break interrupt
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#define SIO_LSR_THRE 0x20 // transmitter holding register empty
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#define SIO_LSR_TEMT 0x40 // transmitter register empty
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#define SIO_LSR_ERR 0x80 // any error condition
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// The modem status register bits.
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#define SIO_MSR_DCTS 0x01 // delta clear to send
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#define SIO_MSR_DDSR 0x02 // delta data set ready
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#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
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#define SIO_MSR_DDCD 0x08 // delta data carrier detect
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#define SIO_MSR_CTS 0x10 // clear to send
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#define SIO_MSR_DSR 0x20 // data set ready
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#define SIO_MSR_RI 0x40 // ring indicator
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#define SIO_MSR_DCD 0x80 // data carrier detect
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// The line control register bits.
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#define SIO_LCR_WLS0 0x01 // word length select bit 0
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#define SIO_LCR_WLS1 0x02 // word length select bit 1
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#define SIO_LCR_STB 0x04 // number of stop bits
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#define SIO_LCR_PEN 0x08 // parity enable
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#define SIO_LCR_EPS 0x10 // even parity select
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#define SIO_LCR_SP 0x20 // stick parity
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#define SIO_LCR_SB 0x40 // set break
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#define SIO_LCR_DLAB 0x80 // divisor latch access bit
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// The FIFO control register
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#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
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#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
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#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
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//-----------------------------------------------------------------------------
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typedef struct {
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cyg_uint8* base;
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cyg_int32 msec_timeout;
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int isr_vector;
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cyg_int32 baud_rate;
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} channel_data_t;
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//-----------------------------------------------------------------------------
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static int
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set_baud( channel_data_t *chan )
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{
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cyg_uint8* base = chan->base;
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cyg_uint8 i;
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for (i=0; i<(sizeof(baud_conf)/sizeof(baud_conf[0])); i++)
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{
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if (chan->baud_rate == baud_conf[i].baud_rate) {
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cyg_uint8 lcr;
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HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr|SIO_LCR_DLAB);
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, baud_conf[i].lsb);
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, baud_conf[i].msb);
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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return 1;
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}
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}
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return -1;
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}
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static void
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init_serial_channel(channel_data_t* __ch_data)
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{
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cyg_uint8* base = __ch_data->base;
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channel_data_t* chan = (channel_data_t*)__ch_data;
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// 8-1-no parity.
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
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chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
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set_baud( chan );
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
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}
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static cyg_bool
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cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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{
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cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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cyg_uint8 lsr;
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HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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if ((lsr & SIO_LSR_DR) == 0)
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return false;
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HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
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return true;
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}
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cyg_uint8
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cyg_hal_plf_serial_getc(void* __ch_data)
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{
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cyg_uint8 ch;
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CYGARC_HAL_SAVE_GP();
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while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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CYGARC_HAL_RESTORE_GP();
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return ch;
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}
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void
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cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
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{
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cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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cyg_uint8 lsr;
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CYGARC_HAL_SAVE_GP();
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do {
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HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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} while ((lsr & SIO_LSR_THRE) == 0);
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HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
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// Hang around until the character has been safely sent.
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do {
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HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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} while ((lsr & SIO_LSR_THRE) == 0);
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CYGARC_HAL_RESTORE_GP();
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}
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static channel_data_t channels[2] = {
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263 |
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#if CYGHWR_HAL_ARM_IOP310_SERIAL_PORTA != 0
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{ (cyg_uint8*)IOP310_SERIAL_PORT_A, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_A},
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#endif
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#if CYGHWR_HAL_ARM_IOP310_SERIAL_PORTB != 0
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{ (cyg_uint8*)IOP310_SERIAL_PORT_B, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_B},
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#endif
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};
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270 |
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271 |
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static void
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272 |
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cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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273 |
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cyg_uint32 __len)
|
274 |
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{
|
275 |
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CYGARC_HAL_SAVE_GP();
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276 |
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277 |
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while(__len-- > 0)
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278 |
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cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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279 |
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280 |
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CYGARC_HAL_RESTORE_GP();
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281 |
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}
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282 |
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283 |
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static void
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284 |
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cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
|
285 |
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{
|
286 |
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CYGARC_HAL_SAVE_GP();
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287 |
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288 |
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while(__len-- > 0)
|
289 |
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*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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290 |
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291 |
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CYGARC_HAL_RESTORE_GP();
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292 |
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}
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293 |
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294 |
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cyg_bool
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295 |
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cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
|
296 |
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{
|
297 |
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int delay_count;
|
298 |
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channel_data_t* chan = (channel_data_t*)__ch_data;
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299 |
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cyg_bool res;
|
300 |
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CYGARC_HAL_SAVE_GP();
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301 |
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delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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303 |
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for(;;) {
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304 |
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res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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305 |
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if (res || 0 == delay_count--)
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306 |
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break;
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307 |
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308 |
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CYGACC_CALL_IF_DELAY_US(100);
|
309 |
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}
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310 |
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311 |
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CYGARC_HAL_RESTORE_GP();
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312 |
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return res;
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313 |
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}
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314 |
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315 |
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static int
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316 |
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cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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317 |
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{
|
318 |
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static int irq_state = 0;
|
319 |
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channel_data_t* chan = (channel_data_t*)__ch_data;
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320 |
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cyg_uint8 ier;
|
321 |
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int ret = 0;
|
322 |
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CYGARC_HAL_SAVE_GP();
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323 |
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|
324 |
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switch (__func) {
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325 |
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case __COMMCTL_IRQ_ENABLE:
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326 |
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HAL_INTERRUPT_UNMASK(chan->isr_vector);
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327 |
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HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
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328 |
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HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
|
329 |
|
|
ier |= SIO_IER_ERDAI;
|
330 |
|
|
HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
|
331 |
|
|
irq_state = 1;
|
332 |
|
|
break;
|
333 |
|
|
case __COMMCTL_IRQ_DISABLE:
|
334 |
|
|
ret = irq_state;
|
335 |
|
|
irq_state = 0;
|
336 |
|
|
HAL_INTERRUPT_MASK(chan->isr_vector);
|
337 |
|
|
HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
|
338 |
|
|
ier &= ~SIO_IER_ERDAI;
|
339 |
|
|
HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
|
340 |
|
|
break;
|
341 |
|
|
case __COMMCTL_DBG_ISR_VECTOR:
|
342 |
|
|
ret = chan->isr_vector;
|
343 |
|
|
break;
|
344 |
|
|
case __COMMCTL_SET_TIMEOUT:
|
345 |
|
|
{
|
346 |
|
|
va_list ap;
|
347 |
|
|
|
348 |
|
|
va_start(ap, __func);
|
349 |
|
|
|
350 |
|
|
ret = chan->msec_timeout;
|
351 |
|
|
chan->msec_timeout = va_arg(ap, cyg_uint32);
|
352 |
|
|
|
353 |
|
|
va_end(ap);
|
354 |
|
|
}
|
355 |
|
|
case __COMMCTL_GETBAUD:
|
356 |
|
|
ret = chan->baud_rate;
|
357 |
|
|
break;
|
358 |
|
|
case __COMMCTL_SETBAUD:
|
359 |
|
|
{
|
360 |
|
|
va_list ap;
|
361 |
|
|
va_start(ap, __func);
|
362 |
|
|
chan->baud_rate = va_arg(ap, cyg_int32);
|
363 |
|
|
va_end(ap);
|
364 |
|
|
ret = set_baud(chan);
|
365 |
|
|
break;
|
366 |
|
|
}
|
367 |
|
|
default:
|
368 |
|
|
break;
|
369 |
|
|
}
|
370 |
|
|
CYGARC_HAL_RESTORE_GP();
|
371 |
|
|
return ret;
|
372 |
|
|
}
|
373 |
|
|
|
374 |
|
|
static int
|
375 |
|
|
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
|
376 |
|
|
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
|
377 |
|
|
{
|
378 |
|
|
channel_data_t* chan = (channel_data_t*)__ch_data;
|
379 |
|
|
cyg_uint8 _iir;
|
380 |
|
|
int res = 0;
|
381 |
|
|
CYGARC_HAL_SAVE_GP();
|
382 |
|
|
|
383 |
|
|
HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir);
|
384 |
|
|
_iir &= SIO_IIR_ID_MASK;
|
385 |
|
|
|
386 |
|
|
*__ctrlc = 0;
|
387 |
|
|
if ( ISR_Rx == _iir ) {
|
388 |
|
|
cyg_uint8 c, lsr;
|
389 |
|
|
HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr);
|
390 |
|
|
if (lsr & SIO_LSR_DR) {
|
391 |
|
|
|
392 |
|
|
HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c);
|
393 |
|
|
|
394 |
|
|
if( cyg_hal_is_break( &c , 1 ) )
|
395 |
|
|
*__ctrlc = 1;
|
396 |
|
|
}
|
397 |
|
|
|
398 |
|
|
// Acknowledge the interrupt
|
399 |
|
|
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
|
400 |
|
|
res = CYG_ISR_HANDLED;
|
401 |
|
|
}
|
402 |
|
|
|
403 |
|
|
CYGARC_HAL_RESTORE_GP();
|
404 |
|
|
return res;
|
405 |
|
|
}
|
406 |
|
|
|
407 |
|
|
static void
|
408 |
|
|
cyg_hal_plf_serial_init(void)
|
409 |
|
|
{
|
410 |
|
|
hal_virtual_comm_table_t* comm;
|
411 |
|
|
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
|
412 |
|
|
|
413 |
|
|
// Disable interrupts.
|
414 |
|
|
HAL_INTERRUPT_MASK(channels[0].isr_vector);
|
415 |
|
|
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
|
416 |
|
|
HAL_INTERRUPT_MASK(channels[1].isr_vector);
|
417 |
|
|
#endif
|
418 |
|
|
|
419 |
|
|
// Init channels
|
420 |
|
|
init_serial_channel(&channels[0]);
|
421 |
|
|
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
|
422 |
|
|
init_serial_channel(&channels[1]);
|
423 |
|
|
#endif
|
424 |
|
|
|
425 |
|
|
// Setup procs in the vector table
|
426 |
|
|
|
427 |
|
|
// Set channel 0
|
428 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
|
429 |
|
|
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
|
430 |
|
|
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
|
431 |
|
|
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
|
432 |
|
|
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
|
433 |
|
|
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
|
434 |
|
|
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
|
435 |
|
|
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
|
436 |
|
|
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
|
437 |
|
|
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
|
438 |
|
|
|
439 |
|
|
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
|
440 |
|
|
// Set channel 1
|
441 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
|
442 |
|
|
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
|
443 |
|
|
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
|
444 |
|
|
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
|
445 |
|
|
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
|
446 |
|
|
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
|
447 |
|
|
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
|
448 |
|
|
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
|
449 |
|
|
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
|
450 |
|
|
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
|
451 |
|
|
#endif
|
452 |
|
|
|
453 |
|
|
// Restore original console
|
454 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
|
455 |
|
|
}
|
456 |
|
|
|
457 |
|
|
/*---------------------------------------------------------------------------*/
|
458 |
|
|
/* End of hal_diag.c */
|