OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [ecos-2.0/] [packages/] [hal/] [frv/] [arch/] [v2_0/] [ChangeLog] - Blame information for rev 1773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1254 phoenix
2003-04-10  Nick Garnett  
2
 
3
        * src/frv.ld:
4
        Added .eh_frame to data section. This is a stopgap fix to allow
5
        C++ programs that define exceptions to link and run. It does not
6
        allow them to actually throw exceptions, since that depends on
7
        compiler changes that have not been made. Further, more
8
        far-reaching, linker script changes will also be needs when that
9
        happens.
10
        Added libsupc++.a to GROUP() directive for GCC versions later than
11
        3.0.
12
 
13
2003-01-31  Mark Salter  
14
 
15
        * src/hal_syscall.c (hal_syscall_handler): Let generic syscall code
16
        handle exit.
17
 
18
2002-04-15  Jonathan Larmour  
19
 
20
        * src/hal_syscall.c (hal_syscall_handler): Add extra sig argument to
21
        __do_syscall.
22
 
23
2001-12-10  Richard Sandiford  
24
 
25
        * src/vectors.S (save_state): Remove unnecessary DDR diddling when
26
        handling breaks.  Use BPCSR rather than BPCSR-4 as the break address.
27
        (restore_state): Take two new arguments: the register that the
28
        PC should be loaded into, and the argument to the rett instruction.
29
        (_break): If handling a break instruction, return to the following
30
        instruction using a normal "ret".  Ignore other kinds of break if
31
        they were triggered when traps were disabled; assume that an
32
        interrupt or exception handler has triggered a stack watchpoint
33
        accidentally.  Correct GP calculation.  Return using "rett #1"
34
        rather than "rett #0".
35
 
36
2001-11-28  Hugo Tyson  
37
 
38
        * src/vectors.S (_vectors): if defined(CYGPKG_HAL_FRV_FRV400) &&
39
        defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS), add macro break_VSR
40
        to create a VSR entry which leaps to _break; rearrange the
41
        initialization of the VSR table so that the counts are correct;
42
        use break_VSR in slot 255; define _break which calls break_handler()
43
        much akin to exception handler().
44
 
45
        Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for
46
        the FRV_FRV400 target; while we do use Hardware Debug, we don't
47
        use *that* sort of hardware debug, specifically we do not use
48
        hardware single-step, because it breaks as soon as we exit debug
49
        mode, ie whilst we are still within the stub.  But vectors.S does
50
        the same tidy-up of machine state, conditioned on FVR400 instead.
51
 
52
2001-10-17  Gary Thomas  
53
 
54
        * src/frv_stub.c: Slight cleanup - only need |VLIW|+1 possible
55
        breakpoint locations.
56
 
57
2001-10-16  Gary Thomas  
58
 
59
        * src/vectors.S (_exception_return): Remove *bad* workaround code
60
        now that single step VLIW works properly.
61
 
62
        * src/frv_stub.c (__clear_single_step):
63
        (__single_step): Restructure to support VLIW sequences.
64
 
65
2001-10-15  Gary Thomas  
66
 
67
        * include/hal_arch.h: Remove [bogus] CYG_HAL_TABLE macros since
68
        the common ones work fine on this architecture.
69
 
70
        * src/vectors.S:
71
        * src/frv_stub.c:
72
        * cdl/hal_frv.cdl: Add CDL to describe various [hardware] debug
73
        options.
74
 
75
2001-10-01  Gary Thomas  
76
 
77
        * src/vectors.S: [FRV400] can't return from exception to a packed
78
        instruction - this yields illegal instruction.
79
 
80
2001-10-11  Gary Thomas  
81
 
82
        * cdl/hal_frv.cdl:
83
        * include/basetype.h:
84
        * include/hal_arch.h:
85
        * include/hal_intr.h:
86
        * include/frv_stub.h:
87
        * include/hal_io.h:
88
        * include/hal_cache.h:
89
        * src/frv_stub.c:
90
        * src/hal_mk_defs.c:
91
        * src/frv.ld:
92
        * src/hal_misc.c:
93
        * src/vectors.S:
94
        * src/context.S:
95
        * src/hal_syscall.c: New port for FRV architecture.
96
 
97
//===========================================================================
98
//####ECOSGPLCOPYRIGHTBEGIN####
99
// -------------------------------------------
100
// This file is part of eCos, the Embedded Configurable Operating System.
101
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
102
//
103
// eCos is free software; you can redistribute it and/or modify it under
104
// the terms of the GNU General Public License as published by the Free
105
// Software Foundation; either version 2 or (at your option) any later version.
106
//
107
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
108
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
109
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
110
// for more details.
111
//
112
// You should have received a copy of the GNU General Public License along
113
// with eCos; if not, write to the Free Software Foundation, Inc.,
114
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
115
//
116
// As a special exception, if other files instantiate templates or use macros
117
// or inline functions from this file, or you compile this file and link it
118
// with other works to produce a work based on this file, this file does not
119
// by itself cause the resulting work to be covered by the GNU General Public
120
// License. However the source code for this file must still be made available
121
// in accordance with section (3) of the GNU General Public License.
122
//
123
// This exception does not invalidate any other reasons why a work based on
124
// this file might be covered by the GNU General Public License.
125
//
126
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
127
// at http://sources.redhat.com/ecos/ecos-license/
128
// -------------------------------------------
129
//####ECOSGPLCOPYRIGHTEND####
130
//===========================================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.