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phoenix |
#ifndef _CYGONCE_PLATFORM_INC_H_
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#define _CYGONCE_PLATFORM_INC_H_
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// #========================================================================
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// #
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// # platform.inc
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// #
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// # Fujitsu platform specific setups (assembler macros)
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// #
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// #========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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// #========================================================================
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// ######DESCRIPTIONBEGIN####
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// #
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// # Author(s): gthomas
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// # Contributors: gthomas
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// # Date: 2001-09-16
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// # Purpose: Fujitsu (FRV400) platform specific setups
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// # Description: This file defines various macros used by the generic
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// # HAL startup code.
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// #
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// #####DESCRIPTIONEND####
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// #
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// #========================================================================
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// Display a value in the system LEDs
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.macro LED n
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sethi #(_FRV400_MB_LEDS>>16),gr15
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setlo #(_FRV400_MB_LEDS&0xFFFF),gr15
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setlos #\n,gr14
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not gr14,gr14
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sti gr14,@(gr15,0)
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.endm
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// Platform initialization - only the necessary bits required to get the
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// board started from a cold reset.
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.macro platform_init
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li 0x7FFF,gr4 // First, a good long spin
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05: nop
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subi gr4,1,gr4
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cmp gr4,gr0,icc0
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bne icc0,0,05b
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call 10f // position independent way to get @_platform_tab
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_platform_tab:
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//
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// SDRAM setups
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//
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.long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
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.long _FRV400_SDRAM_AM0,0x0FF00000
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//
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// LOCAL bus setups
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//
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.long _FRV400_LBUS_CR0,0x03010D01 // ROM/FLASH 0xFF000000..0xFFFFFFFF
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// 16 bits wide, 13 wait states, 1 idle
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.long _FRV400_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
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.long _FRV400_LBUS_AM1,0x000FFFFF
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.long _FRV400_LBUS_CR1,0x00000000
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.long _FRV400_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
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.long _FRV400_LBUS_AM2,0x0FFFFFFF
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.long _FRV400_LBUS_CR2,0x00000000
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.long _FRV400_LBUS_BR3,0x00000000 // SDRAM?
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.long _FRV400_LBUS_AM3,0xFFFFFFFF
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.long _FRV400_LBUS_CR3,0x00000F07
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.long _FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
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.long _FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
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.long _FRV400_SDRAM_CTL,0x05022000 // SDRAM mode/control
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.long _FRV400_SDRAM_AN0,0x00010101
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.long _FRV400_SDRAM_ART,0x00000820
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.long _FRV400_SDRAM_RCN,0x00000000
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.long _FRV400_SDRAM_MS, 0x00020200
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.long _FRV400_SDRAM_CFG,0x80000000
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//? .long _FRV400_CLK_CTRL,0x00000001 // External clock divisor (/2)
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//
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// PCI controller/bridge
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//
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.long _FRV400_PCI_SLBUS_CONFIG, 0x000800E2 // This matches the docs
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// .long _FRV400_PCI_SLBUS_CONFIG, 0x000000E0 // This matches the samples
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.long _FRV400_PCI_ECS0_CONFIG, 0x00000000
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.long _FRV400_PCI_ECS1_CONFIG, 0x000003C1
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.long _FRV400_PCI_ECS2_CONFIG, 0x000001C1
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.long _FRV400_PCI_ECS0_RANGE, 0x00000000
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.long _FRV400_PCI_ECS0_ADDR, 0x00000000
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.long _FRV400_PCI_ECS1_RANGE, 0x00007FFE
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.long _FRV400_PCI_ECS1_ADDR, 0x08108000
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.long _FRV400_PCI_ECS2_RANGE, 0x00007FFE
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.long _FRV400_PCI_ECS2_ADDR, 0x08100000
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.long _FRV400_PCI_PCIIO_RANGE, 0x0001FFFE
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.long _FRV400_PCI_PCIIO_ADDR, 0x00120000
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.long _FRV400_PCI_PCIMEM_RANGE, 0x0003FFFE
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.long _FRV400_PCI_PCIMEM_ADDR, 0x00140000
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.long _FRV400_PCI_PCIIO_PCI_ADDR, 0x24000001
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.long _FRV400_PCI_PCIMEM_PCI_ADDR, 0x28000000
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.long _FRV400_MB_PCI_ARBITER, 0x00000001
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.long _FRV400_MB_PCI_ARBITER, 0x00000001
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.long _FRV400_PCI_SLBUS_CONFIG, 0x800800E2
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// .long _FRV400_PCI_SLBUS_CONFIG, 0x800000E0
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.long 0
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.long _FRV400_SDRAM_STS
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10: movsg lr,gr4 // _platform_tab -> list of initializations
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20: ldi @(gr4,0),gr5 // Register
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ldi @(gr4,4),gr6 // Value
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cmp gr5,gr0,icc0 // End of list?
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beq icc0,0,30f
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sti gr6,@(gr5,0)
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addi gr4,2*4,gr4
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bra 20b // Next item
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30: ldi @(gr6,0),gr5 // gr6 == _FRV400_SDRAM_STS
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cmp gr5,gr0,icc0
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bne icc0,0,30b // Wait for SDRAM ready
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//
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// Note: it is unclear from the documentation if this works at all. There is no
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// description of how these registers are searched and what would happen if they
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// overlap. If it turns out that they are not allowed to overlap, then this setup
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// will have to be restructured.
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//
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li 0x03F0003D,gr4 // Set 0x03FXXXXX supervisor only, no cache - PCI window (1MB)
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movgs gr4,DAMPR0
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li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
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movgs gr4,DAMPR1
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li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
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movgs gr4,DAMPR6
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li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
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movgs gr4,DAMPR7
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movsg hsr0,gr4
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li (1<<25),gr5 // Enable data MMU
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or gr4,gr5,gr4
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movgs gr4,hsr0
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.endm
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#endif // _CYGONCE_PLATFORM_INC_H_
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