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//==========================================================================

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// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

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//==========================================================================

#include <cyg/infra/cyg_type.h>

#include <pkgconf/hal.h>

#include <cyg/hal/hal_startup.h>

#include <cyg/hal/hal_memmap.h>

#include <cyg/hal/hal_arch.h>

/*****************************************************************************

plf_init_cache_acr -- Initialize the cache and access control registers

     The var_init_cache_acr routine already invalidated the cache and ACRs.

This routine only needs to enable the ACRs that it will use.

INPUT:

OUTPUT:

RETURN VALUE:

     None

*****************************************************************************/

void plf_init_cache_acr(void)

{

    // Enable the instruction cache with the following options:

    // Enable CPUSHL invalidation.

    // No freeze.

    // Invalidate all cache lines (flush).

    // No external arbiter control.

    // Disable non-cacheable instruction bursting.

    // Default memory is cacheable.

    // Enable buffered writes.

    // Read and write access permitted by default.

    // Instruction fetch size is cache line.

    mcf52xx_wr_cacr((CYG_WORD32)0x81000102);

    //   Leave the access control registers disabled by default.

}

/*****************************************************************************

plf_reset -- Platform-specific reset vector initialization routine

     This routine must be called with interrupts disabled.

INPUT:

OUTPUT:

RETURN VALUE:

     None

*****************************************************************************/

void plf_reset(void)

{

}