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phoenix |
##
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#=============================================================================
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## platform.S
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##
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## MIPS Atlas platform code
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): dmoseley
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## Contributors: dmoseley
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## Date: 2000-06-06
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## Purpose: MIPS Atlas platform code
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## Description: Platform specific code for Atlas board.
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##
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##
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#ifdef CYGPKG_KERNEL
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# include
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#endif
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#include
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#include
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#include
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##-----------------------------------------------------------------------------
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##-----------------------------------------------------------------------------
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# Platform Initialization.
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# This code performs platform specific initialization.
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##-----------------------------------------------------------------------------
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## MEMC initialization.
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##
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
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.text
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.set noreorder
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.macro MASK_WRITE_PCI_REG regnum, devnum, mask
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.set noreorder
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# First, read the appropriate register
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li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
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sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
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lw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
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# Now, mask in the appropriate bits
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li t2, \mask
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or t1, t2
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# Write the updated value
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li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
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sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
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sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
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.endm
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.macro WRITE_PCI_REG regnum, devnum, base
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.set noreorder
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li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
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li t1, \base
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sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
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sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
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.endm
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#define NO_MASK 0
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#define NO_ERROR_CHECK 0
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#define ERROR_CHECK 1
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.macro READ_SPD_VALUE func, mask, ret_reg, err_check
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.set noreorder
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jal read_spd_value
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li a0, \func # delay slot
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.if \err_check
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beq v0, zero, error
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nop
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.endif
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move \ret_reg, v0
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.if \mask
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and \ret_reg, \mask
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.endif
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.endm
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##-----------------------------------------------------------------------------
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##
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## Initialize the RAM.
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##
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## To do that, we need to first initialize the Galileo PCI stuff to gain access
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## to the SAA9730.
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## From there, use the I2C bus of the SAA9730 to read the SPD SDRAM
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## config data. We then setup the Galileo SDRAM configuration
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##
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## Returns
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## v0 = Error Code
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## v1 = SDRAM size
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##
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FUNC_START(hal_atlas_init_sdram)
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.set noreorder
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# Save the return address
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move s8, ra
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# Setup the base address registers
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li s7, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE)
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# Setup the Galileo controller Endian configuration
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li t0, (HAL_GALILEO_BYTE_SWAP)
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sw t0, HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET(s7)
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# Setup the PCI_0 Timeout and retry configuration
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li t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE
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sw t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET(s7)
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# Setup Galileo as PCI Master
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MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM, HAL_ATLAS_NULL_DEVNUM, \
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(HAL_GALILEO_PCI0_CONFIG_MEMEn | HAL_GALILEO_PCI0_CONFIG_MasEn | HAL_GALILEO_PCI0_CONFIG_SErrEn)
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# Setup Galileo PCI latency timer
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MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_BIST_REGNUM, HAL_ATLAS_NULL_DEVNUM, \
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HAL_GALILEO_PCI0_LAT_TIMER_VAL
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# Setup base address for SAA9730
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WRITE_PCI_REG HAL_GALILEO_PCI0_SCS32_BASE_REGNUM, HAL_ATLAS_SAA9730_DEVNUM, \
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CYGARC_PHYSICAL_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)
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# Setup SAA9730 command and status register
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MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM, HAL_ATLAS_SAA9730_DEVNUM, \
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(HAL_GALILEO_PCI0_CONFIG_MEMEn | HAL_GALILEO_PCI0_CONFIG_SErrEn)
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# Init the I2C controller
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li t0, HAL_SAA9730_I2CSC_I2CCC_6400
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li t1, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)
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sw t0, HAL_SAA9730_I2CSC_OFFSET(t1)
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##=====================================================================================
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##
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## Read the SPD device parameters and determine memory size
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##
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READ_SPD_VALUE HAL_SPD_GET_NUM_ROW_BITS, 0xf, s0, ERROR_CHECK
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READ_SPD_VALUE HAL_SPD_GET_NUM_COL_BITS, 0xf, s1, ERROR_CHECK
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READ_SPD_VALUE HAL_SPD_GET_NUM_DEVICE_BANKS, NO_MASK, s2, ERROR_CHECK
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READ_SPD_VALUE HAL_SPD_GET_SDRAM_WIDTH, 0x7f, s3, ERROR_CHECK
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READ_SPD_VALUE HAL_SPD_GET_NUM_MODULE_BANKS, NO_MASK, s4, ERROR_CHECK
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READ_SPD_VALUE HAL_SPD_GET_ROW_DENSITY, NO_MASK, s5, ERROR_CHECK
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#
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# Determine Size
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# SIZE = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
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#
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addu t0, s0, s1 # t0 = (NUM_ROW_BITS + NUM_COL_BITS)
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li t1, 1 # t1 = 2 ^ 0
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sll t1, t0 # t1 = 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
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multu s2, t1
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mflo s6 # s6 = NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
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nop
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nop
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nop
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multu s6, s3
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mflo s6 # s6 = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
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nop
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nop
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nop
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#
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# Determine size of Bank 0
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#
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li s0, HAL_ATLAS_MAX_BANKSIZE
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0:
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and t1, s5, BIT7
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bnez t1, 8f
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sll s5, 1
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b 0b
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srl s0, 1
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8:
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#
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# Determine if Bank 1 exists
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#
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li t0, 1
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beq s4, t0, 8f
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move s1, zero
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#
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# Determine if Bank 1 is different than Bank 0
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#
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and t1, s5, 0xFF
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beq t1, zero, 8f
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move s1, s0
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#
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# Determine size of Bank 1
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#
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li s1, HAL_ATLAS_MAX_BANKSIZE
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0:
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and t1, s5, BIT7
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bnez t1, 8f
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sll s5, 1
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b 0b
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srl s1, 1
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8:
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#
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# FIXME: We should probably do some validation on the various
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# memory parameters here at some point.
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#
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#
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# Set the base SDRAM bank configuration value.
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# All other fields are zero, and the proper value is masked
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# in when they are known
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#
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li s5, HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C | \
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HAL_GALILEO_SDRAM_WIDTH_64BIT | \
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HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C
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| 256 |
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| 257 |
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#
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| 258 |
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# Setup the CASLAT value.
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# Support only CASLAT = 2
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#
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READ_SPD_VALUE HAL_SPD_GET_CAS_LAT, NO_MASK, v0, NO_ERROR_CHECK
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| 262 |
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and t0, v0, 2
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beqz t0, error
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| 264 |
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nop
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| 265 |
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ori s5, HAL_GALILEO_SDRAM_BANK0_CASLAT_2
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| 266 |
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| 267 |
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#
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| 268 |
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# Setup SDRAM device size
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#
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li t0, SZ_16M
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| 271 |
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beq s6, t0, 8f
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| 272 |
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nop
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| 273 |
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ori s5, HAL_GALILEO_SDRAM_BANK0_SZ_64M
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| 274 |
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8:
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| 275 |
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| 276 |
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#
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| 277 |
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# Setup burst length: Support only 8
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| 278 |
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#
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| 279 |
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READ_SPD_VALUE HAL_SPD_GET_BURST_LENGTH, NO_MASK, v0, NO_ERROR_CHECK
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| 280 |
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and t0, v0, 8
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| 281 |
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beqz t0, error
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| 282 |
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nop
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| 283 |
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| 284 |
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#
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| 285 |
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# Setup Parity.
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| 286 |
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# Only support Parity/Noparity. Don't support ECC.
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| 287 |
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#
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| 288 |
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READ_SPD_VALUE HAL_SPD_GET_CONFIG_TYPE, NO_MASK, v0, NO_ERROR_CHECK
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| 289 |
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li t0, HAL_SPD_CONFIG_TYPE_PARITY
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| 290 |
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beq t0, v0, 0f
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| 291 |
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nop
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| 292 |
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li t0, HAL_SPD_CONFIG_TYPE_ECC
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| 293 |
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beq t0, v0, error
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| 294 |
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nop
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| 295 |
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b 8f
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| 296 |
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li v1, 0
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| 297 |
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0:
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| 298 |
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ori s5, HAL_GALILEO_SDRAM_BANK0_PARITY
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| 299 |
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li v1, 1
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| 300 |
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8:
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| 301 |
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| 302 |
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#
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| 303 |
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# Setup number of device banks
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| 304 |
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# Only support 2 or 4 banks
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| 305 |
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#
|
| 306 |
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li t0, 2
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| 307 |
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beq s2, t0, 8f
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| 308 |
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nop
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| 309 |
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li t0, 4
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| 310 |
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beq s2, t0, 0f
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| 311 |
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nop
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| 312 |
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b error
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| 313 |
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nop
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| 314 |
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0:
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| 315 |
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ori s5, HAL_GALILEO_SDRAM_NUM_BANKS_4
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| 316 |
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8:
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| 317 |
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| 318 |
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#
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| 319 |
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# Now actually store the bank config register
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| 320 |
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#
|
| 321 |
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sw s5, HAL_GALILEO_SDRAM_BANK0_OFFSET(s7)
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| 322 |
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sw s5, HAL_GALILEO_SDRAM_BANK2_OFFSET(s7)
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| 323 |
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| 324 |
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#
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| 325 |
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# Setup the SDRAM configuration register
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| 326 |
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# All other fields are zero, and the proper value is masked
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| 327 |
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# in when they are known
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| 328 |
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#
|
| 329 |
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li s5, HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR | HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS
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| 330 |
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|
| 331 |
|
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#
|
| 332 |
|
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# Setup the Refresh Rate
|
| 333 |
|
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#
|
| 334 |
|
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READ_SPD_VALUE HAL_SPD_GET_REFRESH_RATE, 0x7f, v0, NO_ERROR_CHECK
|
| 335 |
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|
| 336 |
|
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li t0, HAL_SPD_REFRESH_RATE_125
|
| 337 |
|
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beq t0, v0, 8f
|
| 338 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_125
|
| 339 |
|
|
|
| 340 |
|
|
li t0, HAL_SPD_REFRESH_RATE_62_5
|
| 341 |
|
|
beq t0, v0, 8f
|
| 342 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_62_5
|
| 343 |
|
|
|
| 344 |
|
|
li t0, HAL_SPD_REFRESH_RATE_31_3
|
| 345 |
|
|
beq t0, v0, 8f
|
| 346 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_31_3
|
| 347 |
|
|
|
| 348 |
|
|
li t0, HAL_SPD_REFRESH_RATE_15_625
|
| 349 |
|
|
beq t0, v0, 8f
|
| 350 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_15_625
|
| 351 |
|
|
|
| 352 |
|
|
li t0, HAL_SPD_REFRESH_RATE_7_8
|
| 353 |
|
|
beq t0, v0, 8f
|
| 354 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_7_8
|
| 355 |
|
|
|
| 356 |
|
|
# Unknown: assume 3.9 microseconds
|
| 357 |
|
|
li t0, HAL_SPD_REFRESH_COUNTER_3_9
|
| 358 |
|
|
8:
|
| 359 |
|
|
|
| 360 |
|
|
or s5, t0
|
| 361 |
|
|
|
| 362 |
|
|
#
|
| 363 |
|
|
# Setup RAM_WIDTH
|
| 364 |
|
|
#
|
| 365 |
|
|
beqz v1, 8f
|
| 366 |
|
|
nop
|
| 367 |
|
|
READ_SPD_VALUE HAL_SPD_GET_ERROR_CHECK_WIDTH, 0x7f, v0, NO_ERROR_CHECK
|
| 368 |
|
|
beq v0, zero, 8f
|
| 369 |
|
|
nop
|
| 370 |
|
|
ori s5, HAL_GALILEO_SDRAM_CFG_RAM_WIDTH
|
| 371 |
|
|
8:
|
| 372 |
|
|
|
| 373 |
|
|
#
|
| 374 |
|
|
# Store the SDRAM configuration register
|
| 375 |
|
|
#
|
| 376 |
|
|
sw s5, HAL_GALILEO_SDRAM_CONFIG_OFFSET(s7)
|
| 377 |
|
|
|
| 378 |
|
|
#
|
| 379 |
|
|
# Reset SAA9730 now that we are done with the I2C unit.
|
| 380 |
|
|
# This allows the generic PCI library to start with a clean
|
| 381 |
|
|
# slate of devices on the PCI bus.
|
| 382 |
|
|
#
|
| 383 |
|
|
li a0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)
|
| 384 |
|
|
li t0, HAL_SAA9730_SYSRESET_ALL
|
| 385 |
|
|
sw t0, HAL_SAA9730_SYSRESET_OFFSET(a0)
|
| 386 |
|
|
|
| 387 |
|
|
#
|
| 388 |
|
|
# Change the Galileo Base address to HAL_ATLAS_CONTROLLER_BASE
|
| 389 |
|
|
#
|
| 390 |
|
|
li t0, HAL_ATLAS_CONTROLLER_BASE_ISD_CONFIG
|
| 391 |
|
|
sw t0, HAL_GALILEO_INT_SPACE_DECODE_OFFSET(s7)
|
| 392 |
|
|
li s7, CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE)
|
| 393 |
|
|
|
| 394 |
|
|
#
|
| 395 |
|
|
# Setup SDRAM Bank 0 Address Decoding
|
| 396 |
|
|
#
|
| 397 |
|
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE) # Physical bottom of Bank 0
|
| 398 |
|
|
add a1, s0, a0
|
| 399 |
|
|
subu a1, 1 # Physical top of Bank 0
|
| 400 |
|
|
|
| 401 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[1:0]
|
| 402 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
|
| 403 |
|
|
sw t0, HAL_GALILEO_SCS10_LD_OFFSET(s7) # (ie Processor Decode Region)
|
| 404 |
|
|
sw t1, HAL_GALILEO_SCS10_HD_OFFSET(s7) #
|
| 405 |
|
|
|
| 406 |
|
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS0
|
| 407 |
|
|
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
|
| 408 |
|
|
sw t0, HAL_GALILEO_SCS0_LD_OFFSET(s7) # (ie Device Sub-decode Region)
|
| 409 |
|
|
sw t1, HAL_GALILEO_SCS0_HD_OFFSET(s7) #
|
| 410 |
|
|
|
| 411 |
|
|
#
|
| 412 |
|
|
# Setup SDRAM Bank 1 Address Decoding
|
| 413 |
|
|
#
|
| 414 |
|
|
add a0, s0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE) # Physical bottom of Bank 1
|
| 415 |
|
|
add a1, a0, s1
|
| 416 |
|
|
subu a1, 1 # Physical top of Bank 1
|
| 417 |
|
|
|
| 418 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[3:2]
|
| 419 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
|
| 420 |
|
|
sw t0, HAL_GALILEO_SCS32_LD_OFFSET(s7) # (ie Processor Decode Region)
|
| 421 |
|
|
sw t1, HAL_GALILEO_SCS32_HD_OFFSET(s7) #
|
| 422 |
|
|
|
| 423 |
|
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS2
|
| 424 |
|
|
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
|
| 425 |
|
|
sw t0, HAL_GALILEO_SCS2_LD_OFFSET(s7) # (ie Device Sub-decode Region)
|
| 426 |
|
|
sw t1, HAL_GALILEO_SCS2_HD_OFFSET(s7) #
|
| 427 |
|
|
|
| 428 |
|
|
#
|
| 429 |
|
|
# Setup PCI windows
|
| 430 |
|
|
#
|
| 431 |
|
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE)
|
| 432 |
|
|
add a1, a0, HAL_ATLAS_PCI_MEM0_SIZE
|
| 433 |
|
|
subu a1, 1 # Physical top of Bank 1
|
| 434 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 435 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 436 |
|
|
sw t0, HAL_GALILEO_PCIMEM0_LD_OFFSET(s7)
|
| 437 |
|
|
sw t1, HAL_GALILEO_PCIMEM0_HD_OFFSET(s7)
|
| 438 |
|
|
|
| 439 |
|
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM1_BASE)
|
| 440 |
|
|
add a1, a0, HAL_ATLAS_PCI_MEM1_SIZE
|
| 441 |
|
|
subu a1, 1 # Physical top of Bank 1
|
| 442 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 443 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 444 |
|
|
sw t0, HAL_GALILEO_PCIMEM1_LD_OFFSET(s7)
|
| 445 |
|
|
sw t1, HAL_GALILEO_PCIMEM1_HD_OFFSET(s7)
|
| 446 |
|
|
|
| 447 |
|
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE)
|
| 448 |
|
|
add a1, a0, HAL_ATLAS_PCI_IO_SIZE
|
| 449 |
|
|
subu a1, 1 # Physical top of Bank 1
|
| 450 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 451 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
|
| 452 |
|
|
sw t0, HAL_GALILEO_PCIIO_LD_OFFSET(s7)
|
| 453 |
|
|
sw t1, HAL_GALILEO_PCIIO_HD_OFFSET(s7)
|
| 454 |
|
|
|
| 455 |
|
|
#
|
| 456 |
|
|
# Setup FLASH Address Decoding
|
| 457 |
|
|
#
|
| 458 |
|
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_FLASH_BASE) # Physical bottom of Flash Bank
|
| 459 |
|
|
add a1, a0, HAL_ATLAS_FLASH_SIZE
|
| 460 |
|
|
subu a1, 1 # Physical top of Flash Bank
|
| 461 |
|
|
|
| 462 |
|
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup CS[2:0]
|
| 463 |
|
|
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
|
| 464 |
|
|
sw t0, HAL_GALILEO_CS20_LD_OFFSET(s7) # (ie Processor Decode Region)
|
| 465 |
|
|
sw t1, HAL_GALILEO_CS20_HD_OFFSET(s7) #
|
| 466 |
|
|
|
| 467 |
|
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup CS0
|
| 468 |
|
|
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
|
| 469 |
|
|
sw t0, HAL_GALILEO_CS0_LD_OFFSET(s7) # (ie Device Sub-decode Region)
|
| 470 |
|
|
sw t1, HAL_GALILEO_CS0_HD_OFFSET(s7) #
|
| 471 |
|
|
|
| 472 |
|
|
#
|
| 473 |
|
|
# Now disable all unused decodes
|
| 474 |
|
|
# (SCS1, SCS3, PCI1xx, CS1, CS2)
|
| 475 |
|
|
#
|
| 476 |
|
|
li t0, 0xffff
|
| 477 |
|
|
move t1, zero
|
| 478 |
|
|
sw t0, HAL_GALILEO_SCS1_LD_OFFSET(s7)
|
| 479 |
|
|
sw t1, HAL_GALILEO_SCS1_HD_OFFSET(s7)
|
| 480 |
|
|
sw t0, HAL_GALILEO_SCS3_LD_OFFSET(s7)
|
| 481 |
|
|
sw t1, HAL_GALILEO_SCS3_HD_OFFSET(s7)
|
| 482 |
|
|
sw t0, HAL_GALILEO_PCI1IO_LD_OFFSET(s7)
|
| 483 |
|
|
sw t1, HAL_GALILEO_PCI1IO_HD_OFFSET(s7)
|
| 484 |
|
|
sw t0, HAL_GALILEO_PCI1MEM0_LD_OFFSET(s7)
|
| 485 |
|
|
sw t1, HAL_GALILEO_PCI1MEM0_HD_OFFSET(s7)
|
| 486 |
|
|
sw t0, HAL_GALILEO_PCI1MEM1_LD_OFFSET(s7)
|
| 487 |
|
|
sw t1, HAL_GALILEO_PCI1MEM1_HD_OFFSET(s7)
|
| 488 |
|
|
sw t0, HAL_GALILEO_CS1_LD_OFFSET(s7)
|
| 489 |
|
|
sw t1, HAL_GALILEO_CS1_HD_OFFSET(s7)
|
| 490 |
|
|
sw t0, HAL_GALILEO_CS2_LD_OFFSET(s7)
|
| 491 |
|
|
sw t1, HAL_GALILEO_CS2_HD_OFFSET(s7)
|
| 492 |
|
|
|
| 493 |
|
|
noerror:
|
| 494 |
|
|
move v0, zero
|
| 495 |
|
|
add v1, s0, s1
|
| 496 |
|
|
move ra, s8
|
| 497 |
|
|
jr ra
|
| 498 |
|
|
nop
|
| 499 |
|
|
|
| 500 |
|
|
error:
|
| 501 |
|
|
li v0, HAL_ATLAS_MEMERROR
|
| 502 |
|
|
move ra, s8
|
| 503 |
|
|
jr ra
|
| 504 |
|
|
nop
|
| 505 |
|
|
|
| 506 |
|
|
FUNC_END(hal_atlas_init_sdram)
|
| 507 |
|
|
|
| 508 |
|
|
##
|
| 509 |
|
|
## Read a value from the SDRAM SPD device.
|
| 510 |
|
|
##
|
| 511 |
|
|
## Parameters: a0 = subaddress
|
| 512 |
|
|
## Returns: v0 = SPD value read
|
| 513 |
|
|
##
|
| 514 |
|
|
FUNC_START(read_spd_value)
|
| 515 |
|
|
#
|
| 516 |
|
|
# Setup a base address register
|
| 517 |
|
|
#
|
| 518 |
|
|
li a1, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)
|
| 519 |
|
|
|
| 520 |
|
|
#
|
| 521 |
|
|
# Write the I2C command
|
| 522 |
|
|
#
|
| 523 |
|
|
sll a0, 16
|
| 524 |
|
|
li t0, (HAL_SAA9730_I2CTFR_ATTR1_CONT | \
|
| 525 |
|
|
((0xa0 << 24) | HAL_SAA9730_I2CTFR_ATTR2_START) | \
|
| 526 |
|
|
((0xa1 << 8) | HAL_SAA9730_I2CTFR_ATTR0_START))
|
| 527 |
|
|
or a0, t0
|
| 528 |
|
|
sw a0, HAL_SAA9730_I2CTFR_OFFSET(a1)
|
| 529 |
|
|
1: lw t0, HAL_SAA9730_I2CTFR_OFFSET(a1)
|
| 530 |
|
|
and t0, 0x1
|
| 531 |
|
|
bnez t0, 1b
|
| 532 |
|
|
nop
|
| 533 |
|
|
|
| 534 |
|
|
#
|
| 535 |
|
|
# Read the SPD value
|
| 536 |
|
|
#
|
| 537 |
|
|
li a0, HAL_SAA9730_I2CTFR_ATTR2_STOP
|
| 538 |
|
|
sw a0, HAL_SAA9730_I2CTFR_OFFSET(a1)
|
| 539 |
|
|
1: lw t0, HAL_SAA9730_I2CTFR_OFFSET(a1)
|
| 540 |
|
|
and t0, 0x1
|
| 541 |
|
|
bnez t0, 1b
|
| 542 |
|
|
nop
|
| 543 |
|
|
|
| 544 |
|
|
#
|
| 545 |
|
|
# Setup the return value.
|
| 546 |
|
|
#
|
| 547 |
|
|
lw v0, HAL_SAA9730_I2CTFR_OFFSET(a1)
|
| 548 |
|
|
srl v0, 24
|
| 549 |
|
|
|
| 550 |
|
|
jr ra
|
| 551 |
|
|
nop
|
| 552 |
|
|
FUNC_END(read_spd_value)
|
| 553 |
|
|
#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */
|
| 554 |
|
|
|
| 555 |
|
|
##-----------------------------------------------------------------------------
|
| 556 |
|
|
# Interrupt vector tables.
|
| 557 |
|
|
# These tables contain the isr, data and object pointers used to deliver
|
| 558 |
|
|
# interrupts to user code.
|
| 559 |
|
|
|
| 560 |
|
|
.extern hal_default_isr
|
| 561 |
|
|
|
| 562 |
|
|
.data
|
| 563 |
|
|
|
| 564 |
|
|
.globl hal_interrupt_handlers
|
| 565 |
|
|
hal_interrupt_handlers:
|
| 566 |
|
|
.rept 25
|
| 567 |
|
|
.long hal_default_isr
|
| 568 |
|
|
.endr
|
| 569 |
|
|
|
| 570 |
|
|
.globl hal_interrupt_data
|
| 571 |
|
|
hal_interrupt_data:
|
| 572 |
|
|
.rept 25
|
| 573 |
|
|
.long 0
|
| 574 |
|
|
.endr
|
| 575 |
|
|
|
| 576 |
|
|
.globl hal_interrupt_objects
|
| 577 |
|
|
hal_interrupt_objects:
|
| 578 |
|
|
.rept 25
|
| 579 |
|
|
.long 0
|
| 580 |
|
|
.endr
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
##-----------------------------------------------------------------------------
|
| 584 |
|
|
## end of platform.S
|
