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phoenix |
#ifndef CYGONCE_HAL_VARIANT_INC
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#define CYGONCE_HAL_VARIANT_INC
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##=============================================================================
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##
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## variant.inc
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##
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## VR4300 assembler header file
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors: nickg
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## Date: 1999-04-06
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## Purpose: VR4300 definitions.
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the VR4300 CPU.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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.set mips3
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#include
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#include
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#include
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#------------------------------------------------------------------------------
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# Initial SR value
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# Set the KX bit to enable 64bit accesses in kernel mode.
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#define INITIAL_SR_VAR 0x00000080
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#------------------------------------------------------------------------------
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# Set up initial value for config register. Sets endian mode and
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# disables the cache on kseg0.
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#if defined(CYGPKG_HAL_MIPS_MSBFIRST)
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# define INITIAL_CONFIG0 0x00008002
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#elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
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# define INITIAL_CONFIG0 0x00000002
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#else
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# error MIPS endianness not set by configuration
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#endif
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#------------------------------------------------------------------------------
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# Set up initial value for FPU FCR31 register. We set the FS bit to flush
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# denormalized results to zero.
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#ifndef CYG_HAL_MIPS_FCSR_INIT
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#define CYG_HAL_MIPS_FCSR_INIT 0x01000000
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#endif
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#------------------------------------------------------------------------------
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# Cache macros.
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#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
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.macro hal_cache_init
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#ifndef CYG_HAL_STARTUP_RAM
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mfc0 v0,config0 # disable Kseg0 caching in config0 register
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nop
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nop
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la v1,0xfffffff8
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and v0,v0,v1
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ori v0,v0,2
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mtc0 v0,config0
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nop
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nop
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nop
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.set mips3 # Set ISA to MIPS 3 to allow cache insns
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# Now ensure the caches are invalidated. The caches are NOT cleared or
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# invalidated on non-power-up resets and may come up in a random state
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# on power-up. Hence they may contain stale or randomly bogus data.
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# Here we use the index-store-tag cache operation to clear all the cache
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# tags and states to zero. This will render them all invalid on the
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# VR4300.
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# D-cache:
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la t0,0x80000000
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addi t1,t0,0x2000
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1:
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mtc0 zero,$28
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mtc0 zero,$29
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cache 0x09,0(t0)
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addi t0,t0,0x10
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sub v0,t1,t0
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bgez v0,1b
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nop # delay slot
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# I-cache:
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la a0,0x80000000
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addi a1,a0,0x4000
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1:
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mtc0 zero,$28
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mtc0 zero,$29
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cache 0x08,0(a0)
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addi a0,a0,0x20
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sub v0,a1,a0
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bgez v0,1b
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nop # delay slot
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.set mips0 # reset ISA to default
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#endif
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.endm
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#define CYGPKG_HAL_MIPS_CACHE_DEFINED
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#endif
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#------------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_VARIANT_INC
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# end of variant.inc
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