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[/] [or1k/] [trunk/] [gdb-5.0/] [gdb/] [config/] [arm/] [tm-arm.h] - Blame information for rev 106

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1 106 markom
/* Definitions to target GDB to ARM targets.
2
   Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3
 
4
   This file is part of GDB.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 59 Temple Place - Suite 330,
19
   Boston, MA 02111-1307, USA.  */
20
 
21
#ifndef TM_ARM_H
22
#define TM_ARM_H
23
 
24
/* Forward declarations for prototypes.  */
25
struct type;
26
struct value;
27
 
28
/* Target byte order on ARM defaults to selectable, and defaults to
29
   little endian.  */
30
#define TARGET_BYTE_ORDER_SELECTABLE_P  1
31
#define TARGET_BYTE_ORDER_DEFAULT       LITTLE_ENDIAN
32
 
33
/* IEEE format floating point.  */
34
#define IEEE_FLOAT
35
#define TARGET_DOUBLE_FORMAT  (target_byte_order == BIG_ENDIAN \
36
                               ? &floatformat_ieee_double_big    \
37
                               : &floatformat_ieee_double_littlebyte_bigword)
38
 
39
/* When reading symbols, we need to zap the low bit of the address,
40
   which may be set to 1 for Thumb functions.  */
41
 
42
#define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1)
43
 
44
/* Remove useless bits from addresses in a running program.  */
45
 
46
CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
47
 
48
#define ADDR_BITS_REMOVE(val)   (arm_addr_bits_remove (val))
49
 
50
/* Offset from address of function to start of its code.  Zero on most
51
   machines.  */
52
 
53
#define FUNCTION_START_OFFSET   0
54
 
55
/* Advance PC across any function entry prologue instructions to reach
56
   some "real" code.  */
57
 
58
extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
59
 
60
#define SKIP_PROLOGUE(pc)  (arm_skip_prologue (pc))
61
 
62
/* Immediately after a function call, return the saved pc.  Can't
63
   always go through the frames for this because on some machines the
64
   new frame is not set up until the new function executes some
65
   instructions.  */
66
 
67
#define SAVED_PC_AFTER_CALL(frame)  arm_saved_pc_after_call (frame)
68
struct frame_info;
69
extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
70
 
71
/* The following define instruction sequences that will cause ARM
72
   cpu's to take an undefined instruction trap.  These are used to
73
   signal a breakpoint to GDB.
74
 
75
   The newer ARMv4T cpu's are capable of operating in ARM or Thumb
76
   modes.  A different instruction is required for each mode.  The ARM
77
   cpu's can also be big or little endian.  Thus four different
78
   instructions are needed to support all cases.
79
 
80
   Note: ARMv4 defines several new instructions that will take the
81
   undefined instruction trap.  ARM7TDMI is nominally ARMv4T, but does
82
   not in fact add the new instructions.  The new undefined
83
   instructions in ARMv4 are all instructions that had no defined
84
   behaviour in earlier chips.  There is no guarantee that they will
85
   raise an exception, but may be treated as NOP's.  In practice, it
86
   may only safe to rely on instructions matching:
87
 
88
   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
89
   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
90
   C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
91
 
92
   Even this may only true if the condition predicate is true. The
93
   following use a condition predicate of ALWAYS so it is always TRUE.
94
 
95
   There are other ways of forcing a breakpoint.  ARM Linux, RisciX,
96
   and I suspect NetBSD will all use a software interrupt rather than
97
   an undefined instruction to force a trap.  This can be handled by
98
   redefining some or all of the following in a target dependent
99
   fashion.  */
100
 
101
#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
102
#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
103
#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
104
#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
105
 
106
/* Stack grows downward.  */
107
 
108
#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
109
 
110
/* !!!! if we're using RDP, then we're inserting breakpoints and
111
   storing their handles instread of what was in memory.  It is nice
112
   that this is the same size as a handle - otherwise remote-rdp will
113
   have to change. */
114
 
115
/* BREAKPOINT_FROM_PC uses the program counter value to determine
116
   whether a 16- or 32-bit breakpoint should be used.  It returns a
117
   pointer to a string of bytes that encode a breakpoint instruction,
118
   stores the length of the string to *lenptr, and adjusts the pc (if
119
   necessary) to point to the actual memory location where the
120
   breakpoint should be inserted.  */
121
 
122
extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
123
#define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
124
 
125
/* Amount PC must be decremented by after a breakpoint.  This is often
126
   the number of bytes in BREAKPOINT but not always.  */
127
 
128
#define DECR_PC_AFTER_BREAK 0
129
 
130
/* Code to execute to print interesting information about the floating
131
   point processor (if any) or emulator.  No need to define if there
132
   is nothing to do. */
133
extern void arm_float_info (void);
134
 
135
#define FLOAT_INFO      { arm_float_info (); }
136
 
137
/* Say how long (ordinary) registers are.  This is a piece of bogosity
138
   used in push_word and a few other places; REGISTER_RAW_SIZE is the
139
   real way to know how big a register is.  */
140
 
141
#define REGISTER_SIZE   4
142
 
143
/* Say how long FP registers are.  Used for documentation purposes and
144
   code readability in this header.  IEEE extended doubles are 80
145
   bits.  DWORD aligned they use 96 bits.  */
146
#define FP_REGISTER_RAW_SIZE    12
147
 
148
/* GCC doesn't support long doubles (extended IEEE values).  The FP
149
   register virtual size is therefore 64 bits.  Used for documentation
150
   purposes and code readability in this header.  */
151
#define FP_REGISTER_VIRTUAL_SIZE        8
152
 
153
/* Status registers are the same size as general purpose registers.
154
   Used for documentation purposes and code readability in this
155
   header.  */
156
#define STATUS_REGISTER_SIZE    REGISTER_SIZE
157
 
158
/* Number of machine registers.  The only define actually required
159
   is NUM_REGS.  The other definitions are used for documentation
160
   purposes and code readability.  */
161
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
162
   (and called PS for processor status) so the status bits can be cleared
163
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
164
   in PS.  */
165
#define NUM_FREGS       8       /* Number of floating point registers.  */
166
#define NUM_SREGS       2       /* Number of status registers.  */
167
#define NUM_GREGS       16      /* Number of general purpose registers.  */
168
#define NUM_REGS        (NUM_GREGS + NUM_FREGS + NUM_SREGS)
169
 
170
/* An array of names of registers. */
171
extern char **arm_register_names;
172
 
173
#define REGISTER_NAME(i) arm_register_names[i]
174
 
175
/* Register numbers of various important registers.  Note that some of
176
   these values are "real" register numbers, and correspond to the
177
   general registers of the machine, and some are "phony" register
178
   numbers which are too large to be actual register numbers as far as
179
   the user is concerned but do serve to get the desired values when
180
   passed to read_register.  */
181
 
182
#define A1_REGNUM 0             /* first integer-like argument */
183
#define A4_REGNUM 3             /* last integer-like argument */
184
#define AP_REGNUM 11
185
#define FP_REGNUM 11            /* Contains address of executing stack frame */
186
#define SP_REGNUM 13            /* Contains address of top of stack */
187
#define LR_REGNUM 14            /* address to return to from a function call */
188
#define PC_REGNUM 15            /* Contains program counter */
189
#define F0_REGNUM 16            /* first floating point register */
190
#define F3_REGNUM 19            /* last floating point argument register */
191
#define F7_REGNUM 23            /* last floating point register */
192
#define FPS_REGNUM 24           /* floating point status register */
193
#define PS_REGNUM 25            /* Contains processor status */
194
 
195
#define THUMB_FP_REGNUM 7       /* R7 is frame register on Thumb */
196
 
197
#define ARM_NUM_ARG_REGS        4
198
#define ARM_LAST_ARG_REGNUM     A4_REGNUM
199
#define ARM_NUM_FP_ARG_REGS     4
200
#define ARM_LAST_FP_ARG_REGNUM  F3_REGNUM
201
 
202
/* Instruction condition field values.  */
203
#define INST_EQ         0x0
204
#define INST_NE         0x1
205
#define INST_CS         0x2
206
#define INST_CC         0x3
207
#define INST_MI         0x4
208
#define INST_PL         0x5
209
#define INST_VS         0x6
210
#define INST_VC         0x7
211
#define INST_HI         0x8
212
#define INST_LS         0x9
213
#define INST_GE         0xa
214
#define INST_LT         0xb
215
#define INST_GT         0xc
216
#define INST_LE         0xd
217
#define INST_AL         0xe
218
#define INST_NV         0xf
219
 
220
#define FLAG_N          0x80000000
221
#define FLAG_Z          0x40000000
222
#define FLAG_C          0x20000000
223
#define FLAG_V          0x10000000
224
 
225
 
226
 
227
/* Total amount of space needed to store our copies of the machine's
228
   register state, the array `registers'.  */
229
 
230
#define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
231
                        (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
232
                        (NUM_SREGS * STATUS_REGISTER_SIZE))
233
 
234
/* Index within `registers' of the first byte of the space for
235
   register N.  */
236
 
237
#define REGISTER_BYTE(N) \
238
     ((N) < F0_REGNUM \
239
      ? (N) * REGISTER_SIZE \
240
      : ((N) < PS_REGNUM \
241
         ? (NUM_GREGS * REGISTER_SIZE + \
242
            ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
243
         : (NUM_GREGS * REGISTER_SIZE + \
244
            NUM_FREGS * FP_REGISTER_RAW_SIZE + \
245
            ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
246
 
247
/* Number of bytes of storage in the actual machine representation for
248
   register N.  All registers are 4 bytes, except fp0 - fp7, which are
249
   12 bytes in length.  */
250
#define REGISTER_RAW_SIZE(N) \
251
     ((N) < F0_REGNUM ? REGISTER_SIZE : \
252
      (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
253
 
254
/* Number of bytes of storage in a program's representation
255
   for register N.  */
256
#define REGISTER_VIRTUAL_SIZE(N) \
257
        ((N) < F0_REGNUM ? REGISTER_SIZE : \
258
         (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
259
 
260
/* Largest value REGISTER_RAW_SIZE can have.  */
261
 
262
#define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
263
 
264
/* Largest value REGISTER_VIRTUAL_SIZE can have.  */
265
#define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
266
 
267
/* Nonzero if register N requires conversion from raw format to
268
   virtual format. */
269
extern int arm_register_convertible (unsigned int);
270
#define REGISTER_CONVERTIBLE(REGNUM) (arm_register_convertible (REGNUM))
271
 
272
/* Convert data from raw format for register REGNUM in buffer FROM to
273
   virtual format with type TYPE in buffer TO. */
274
 
275
extern void arm_register_convert_to_virtual (unsigned int regnum,
276
                                             struct type *type,
277
                                             void *from, void *to);
278
#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
279
     arm_register_convert_to_virtual (REGNUM, TYPE, FROM, TO)
280
 
281
/* Convert data from virtual format with type TYPE in buffer FROM to
282
   raw format for register REGNUM in buffer TO.  */
283
 
284
extern void arm_register_convert_to_raw (unsigned int regnum,
285
                                         struct type *type,
286
                                         void *from, void *to);
287
#define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
288
     arm_register_convert_to_raw (REGNUM, TYPE, FROM, TO)
289
 
290
/* Return the GDB type object for the "standard" data type of data in
291
   register N.  */
292
 
293
#define REGISTER_VIRTUAL_TYPE(N) \
294
     (((unsigned)(N) - F0_REGNUM) < NUM_FREGS \
295
      ? builtin_type_double : builtin_type_int)
296
 
297
/* The system C compiler uses a similar structure return convention to gcc */
298
extern use_struct_convention_fn arm_use_struct_convention;
299
#define USE_STRUCT_CONVENTION(gcc_p, type) \
300
     arm_use_struct_convention (gcc_p, type)
301
 
302
/* Store the address of the place in which to copy the structure the
303
   subroutine will return.  This is called from call_function. */
304
 
305
#define STORE_STRUCT_RETURN(ADDR, SP) \
306
     write_register (A1_REGNUM, (ADDR))
307
 
308
/* Extract from an array REGBUF containing the (raw) register state a
309
   function return value of type TYPE, and copy that, in virtual
310
   format, into VALBUF.  */
311
 
312
extern void arm_extract_return_value (struct type *, char[], char *);
313
#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
314
     arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
315
 
316
/* Write into appropriate registers a function return value of type
317
   TYPE, given in virtual format.  */
318
 
319
extern void convert_to_extended (void *dbl, void *ptr);
320
#define STORE_RETURN_VALUE(TYPE,VALBUF) \
321
  if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) {                              \
322
    char _buf[MAX_REGISTER_RAW_SIZE];                                   \
323
    convert_to_extended (VALBUF, _buf);                                         \
324
    write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
325
  } else                                                                \
326
    write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
327
 
328
/* Extract from an array REGBUF containing the (raw) register state
329
   the address in which a function should return its structure value,
330
   as a CORE_ADDR (or an expression that can be used as one).  */
331
 
332
#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
333
  (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
334
 
335
/* Specify that for the native compiler variables for a particular
336
   lexical context are listed after the beginning LBRAC instead of
337
   before in the executables list of symbols.  */
338
#define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
339
 
340
 
341
/* Define other aspects of the stack frame.  We keep the offsets of
342
   all saved registers, 'cause we need 'em a lot!  We also keep the
343
   current size of the stack frame, and the offset of the frame
344
   pointer from the stack pointer (for frameless functions, and when
345
   we're still in the prologue of a function with a frame) */
346
 
347
#define EXTRA_FRAME_INFO        \
348
  struct frame_saved_regs fsr;  \
349
  int framesize;                \
350
  int frameoffset;              \
351
  int framereg;
352
 
353
extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi);
354
#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
355
        arm_init_extra_frame_info ((fromleaf), (fi))
356
 
357
/* Return the frame address.  On ARM, it is R11; on Thumb it is R7.  */
358
CORE_ADDR arm_target_read_fp (void);
359
#define TARGET_READ_FP() arm_target_read_fp ()
360
 
361
/* Describe the pointer in each stack frame to the previous stack
362
   frame (its caller).  */
363
 
364
/* FRAME_CHAIN takes a frame's nominal address and produces the
365
   frame's chain-pointer.
366
 
367
   However, if FRAME_CHAIN_VALID returns zero,
368
   it means the given frame is the outermost one and has no caller.  */
369
 
370
#define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe)
371
extern CORE_ADDR arm_frame_chain (struct frame_info *);
372
 
373
extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *);
374
#define FRAME_CHAIN_VALID(chain, thisframe) \
375
     arm_frame_chain_valid (chain, thisframe)
376
 
377
/* Define other aspects of the stack frame.  */
378
 
379
/* A macro that tells us whether the function invocation represented
380
   by FI does not have a frame on the stack associated with it.  If it
381
   does not, FRAMELESS is set to 1, else 0.
382
 
383
   Sometimes we have functions that do a little setup (like saving the
384
   vN registers with the stmdb instruction, but DO NOT set up a frame.
385
   The symbol table will report this as a prologue.  However, it is
386
   important not to try to parse these partial frames as frames, or we
387
   will get really confused.
388
 
389
   So I will demand 3 instructions between the start & end of the
390
   prologue before I call it a real prologue, i.e. at least
391
         mov ip, sp,
392
         stmdb sp!, {}
393
         sub sp, ip, #4. */
394
 
395
extern int arm_frameless_function_invocation (struct frame_info *fi);
396
#define FRAMELESS_FUNCTION_INVOCATION(FI) \
397
(arm_frameless_function_invocation (FI))
398
 
399
/* Saved Pc.  */
400
 
401
#define FRAME_SAVED_PC(FRAME)   arm_frame_saved_pc (FRAME)
402
extern CORE_ADDR arm_frame_saved_pc (struct frame_info *);
403
 
404
#define FRAME_ARGS_ADDRESS(fi) (fi->frame)
405
 
406
#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
407
 
408
/* Return number of args passed to a frame.
409
   Can return -1, meaning no way to tell.  */
410
 
411
#define FRAME_NUM_ARGS(fi) (-1)
412
 
413
/* Return number of bytes at start of arglist that are not really args. */
414
 
415
#define FRAME_ARGS_SKIP 0
416
 
417
/* Put here the code to store, into a struct frame_saved_regs, the
418
   addresses of the saved registers of frame described by FRAME_INFO.
419
   This includes special registers such as pc and fp saved in special
420
   ways in the stack frame.  sp is even more special: the address we
421
   return for it IS the sp for the next frame.  */
422
 
423
struct frame_saved_regs;
424
struct frame_info;
425
void arm_frame_find_saved_regs (struct frame_info * fi,
426
                                struct frame_saved_regs * fsr);
427
 
428
#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
429
        arm_frame_find_saved_regs (frame_info, &(frame_saved_regs));
430
 
431
/* Things needed for making the inferior call functions.  */
432
 
433
#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
434
     sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr))
435
extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int,
436
                                     CORE_ADDR);
437
 
438
/* Push an empty stack frame, to record the current PC, etc.  */
439
 
440
void arm_push_dummy_frame (void);
441
 
442
#define PUSH_DUMMY_FRAME arm_push_dummy_frame ()
443
 
444
/* Discard from the stack the innermost frame, restoring all registers.  */
445
 
446
void arm_pop_frame (void);
447
 
448
#define POP_FRAME arm_pop_frame ()
449
 
450
/* This sequence of words is the instructions
451
 
452
   mov  lr,pc
453
   mov  pc,r4
454
   illegal
455
 
456
   Note this is 12 bytes.  */
457
 
458
#define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe}
459
#define CALL_DUMMY_START_OFFSET  0      /* Start execution at beginning of dummy */
460
 
461
#define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
462
extern int arm_call_dummy_breakpoint_offset (void);
463
 
464
/* Insert the specified number of args and function address into a
465
   call sequence of the above form stored at DUMMYNAME.  */
466
 
467
#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
468
   arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
469
 
470
void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
471
                         int nargs, struct value ** args,
472
                         struct type * type, int gcc_p);
473
 
474
CORE_ADDR arm_get_next_pc (CORE_ADDR pc);
475
 
476
/* Macros for setting and testing a bit in a minimal symbol that marks
477
   it as Thumb function.  The MSB of the minimal symbol's "info" field
478
   is used for this purpose. This field is already being used to store
479
   the symbol size, so the assumption is that the symbol size cannot
480
   exceed 2^31.
481
 
482
   COFF_MAKE_MSYMBOL_SPECIAL
483
   ELF_MAKE_MSYMBOL_SPECIAL
484
 
485
   These macros test whether the COFF or ELF symbol corresponds to a
486
   thumb function, and set a "special" bit in a minimal symbol to
487
   indicate that it does.
488
 
489
   MSYMBOL_SET_SPECIAL  Actually sets the "special" bit.
490
   MSYMBOL_IS_SPECIAL   Tests the "special" bit in a minimal symbol.
491
   MSYMBOL_SIZE         Returns the size of the minimal symbol,
492
                        i.e. the "info" field with the "special" bit
493
                        masked out
494
   */
495
 
496
extern int coff_sym_is_thumb (int val);
497
 
498
#define MSYMBOL_SET_SPECIAL(msym) \
499
        MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000)
500
#define MSYMBOL_IS_SPECIAL(msym) \
501
  (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
502
#define MSYMBOL_SIZE(msym) \
503
  ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
504
 
505
/* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */
506
#define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
507
        { if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \
508
                MSYMBOL_SET_SPECIAL(msym); }
509
 
510
#define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \
511
 { if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); }
512
 
513
/* The first 0x20 bytes are the trap vectors.  */
514
#define LOWEST_PC       0x20
515
 
516
#endif /* TM_ARM_H */

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