OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.0/] [gdb/] [config/] [i386/] [tm-i386sco5.h] - Blame information for rev 106

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom
/* Macro definitions for GDB on an Intel i386 running SCO Open Server 5.
2
   Copyright (C) 1998 Free Software Foundation, Inc.
3
   Written by J. Kean Johnston (jkj@sco.com).
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 2 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 59 Temple Place - Suite 330,
20
   Boston, MA 02111-1307, USA.  */
21
 
22
#ifndef TM_I386SCO5_H
23
#define TM_I386SCO5_H 1
24
 
25
/* Pick up most of what we need from the generic i386 target include file. */
26
 
27
#include "i386/tm-i386.h"
28
 
29
/* Pick up more stuff from the generic SYSV and SVR4 host include files. */
30
#include "i386/tm-i386v.h"
31
#include "tm-sysv4.h"
32
 
33
#define KERNEL_U_SIZE kernel_u_size()
34
 
35
/*
36
 * SCO is unlike other SVR3 targets in that it has SVR4 style shared
37
 * libs, with a slight twist. We expect 3 traps (2 for the exec and
38
 * one for the dynamic loader).  After the third trap we insert the
39
 * SOLIB breakpoints, then wait for the 4th trap.
40
 */
41
#undef START_INFERIOR_TRAPS_EXPECTED
42
#define START_INFERIOR_TRAPS_EXPECTED 3
43
 
44
/* We can also do hardware watchpoints */
45
#define TARGET_HAS_HARDWARE_WATCHPOINTS
46
#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) 1
47
 
48
/* After a watchpoint trap, the PC points to the instruction which
49
   caused the trap.  But we can continue over it without disabling the
50
   trap. */
51
#define HAVE_CONTINUABLE_WATCHPOINT
52
#define HAVE_STEPPABLE_WATCHPOINT
53
 
54
#define STOPPED_BY_WATCHPOINT(W)  \
55
  i386_stopped_by_watchpoint (inferior_pid)
56
 
57
#define target_insert_watchpoint(addr, len, type)  \
58
  i386_insert_watchpoint (inferior_pid, addr, len, type)
59
 
60
#define target_remove_watchpoint(addr, len, type)  \
61
  i386_remove_watchpoint (inferior_pid, addr, len)
62
 
63
#endif /* ifndef TM_I386SCO5_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.