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/* Parameters for execution on an HP PA-RISC machine running OSF1, for GDB.
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Contributed by the Center for Software Science at the
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University of Utah (pa-gdb-bugs@cs.utah.edu). */
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/* Define offsets to access CPROC stack when it does not have
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* a kernel thread.
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*/
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#define MACHINE_CPROC_SP_OFFSET 20
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#define MACHINE_CPROC_PC_OFFSET 16
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#define MACHINE_CPROC_FP_OFFSET 12
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/*
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* Software defined PSW masks.
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*/
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#define PSW_SS 0x10000000 /* Kernel managed single step */
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/* Thread flavors used in re-setting the T bit.
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* @@ this is also bad for cross debugging.
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*/
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#define TRACE_FLAVOR HP800_THREAD_STATE
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#define TRACE_FLAVOR_SIZE HP800_THREAD_STATE_COUNT
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#define TRACE_SET(x,state) \
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((struct hp800_thread_state *)state)->cr22 |= PSW_SS
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#define TRACE_CLEAR(x,state) \
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((((struct hp800_thread_state *)state)->cr22 &= ~PSW_SS), 1)
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/* For OSF1 (Should be close if not identical to BSD, but I haven't
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tested it yet):
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The signal context structure pointer is always saved at the base
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of the frame + 0x4.
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We get the PC & SP directly from the sigcontext structure itself.
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For other registers we have to dive in a little deeper:
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The hardware save state pointer is at offset 0x10 within the
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signal context structure.
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Within the hardware save state, registers are found in the same order
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as the register numbers in GDB. */
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#define FRAME_SAVED_PC_IN_SIGTRAMP(FRAME, TMP) \
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{ \
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*(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \
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*(TMP) = read_memory_integer (*(TMP) + 0x18, 4); \
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}
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#define FRAME_BASE_BEFORE_SIGTRAMP(FRAME, TMP) \
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{ \
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*(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \
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*(TMP) = read_memory_integer (*(TMP) + 0x8, 4); \
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}
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#define FRAME_FIND_SAVED_REGS_IN_SIGTRAMP(FRAME, FSR) \
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{ \
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int i; \
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CORE_ADDR TMP; \
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TMP = read_memory_integer ((FRAME)->frame + 0x4, 4); \
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TMP = read_memory_integer (TMP + 0x10, 4); \
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for (i = 0; i < NUM_REGS; i++) \
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{ \
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if (i == SP_REGNUM) \
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(FSR)->regs[SP_REGNUM] = read_memory_integer (TMP + SP_REGNUM * 4, 4); \
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else \
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(FSR)->regs[i] = TMP + i * 4; \
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} \
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}
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/* OSF1 does not need the pc space queue restored. */
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#define NO_PC_SPACE_QUEUE_RESTORE
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/* The mach kernel uses the recovery counter to implement single
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stepping. While this greatly simplifies the kernel support
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necessary for single stepping, it unfortunately does the wrong
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thing in the presense of a nullified instruction (gives control
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back two insns after the nullifed insn). This is an artifact
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of the HP architecture (recovery counter doesn't tick for
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nullified insns).
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Do our best to avoid losing in such situations. */
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#define INSTRUCTION_NULLIFIED \
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(({ \
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int ipsw = (int)read_register(IPSW_REGNUM); \
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if (ipsw & PSW_N) \
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{ \
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int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \
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write_register(PCOQ_HEAD_REGNUM, pcoqt); \
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write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \
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write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \
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stop_pc = pcoqt; \
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} \
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}), 0)
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/* It's mostly just the common stuff. */
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#include "pa/tm-hppa.h"
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