OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.0/] [gdb/] [d10v-tdep.c] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 104 markom
/* Target-dependent code for Mitsubishi D10V, for GDB.
2
   Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc.
3
 
4
   This file is part of GDB.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 59 Temple Place - Suite 330,
19
   Boston, MA 02111-1307, USA.  */
20
 
21
/*  Contributed by Martin Hunt, hunt@cygnus.com */
22
 
23
#include "defs.h"
24
#include "frame.h"
25
#include "obstack.h"
26
#include "symtab.h"
27
#include "gdbtypes.h"
28
#include "gdbcmd.h"
29
#include "gdbcore.h"
30
#include "gdb_string.h"
31
#include "value.h"
32
#include "inferior.h"
33
#include "dis-asm.h"
34
#include "symfile.h"
35
#include "objfiles.h"
36
#include "language.h"
37
 
38
#include "sim-d10v.h"
39
 
40
#undef XMALLOC
41
#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
42
 
43
struct frame_extra_info
44
  {
45
    CORE_ADDR return_pc;
46
    int frameless;
47
    int size;
48
  };
49
 
50
struct gdbarch_tdep
51
  {
52
    int a0_regnum;
53
    int nr_dmap_regs;
54
    unsigned long (*dmap_register) (int nr);
55
    unsigned long (*imap_register) (int nr);
56
    int (*register_sim_regno) (int nr);
57
  };
58
 
59
/* These are the addresses the D10V-EVA board maps data and
60
   instruction memory to. */
61
 
62
#define DMEM_START      0x2000000
63
#define IMEM_START      0x1000000
64
#define STACK_START     0x0007ffe
65
 
66
/* d10v register names. */
67
 
68
enum
69
  {
70
    R0_REGNUM = 0,
71
    LR_REGNUM = 13,
72
    PSW_REGNUM = 16,
73
    NR_IMAP_REGS = 2,
74
    NR_A_REGS = 2
75
  };
76
#define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
77
#define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
78
 
79
/* d10v calling convention. */
80
 
81
#define ARG1_REGNUM R0_REGNUM
82
#define ARGN_REGNUM 3
83
#define RET1_REGNUM R0_REGNUM
84
 
85
/* Local functions */
86
 
87
extern void _initialize_d10v_tdep PARAMS ((void));
88
 
89
static void d10v_eva_prepare_to_trace PARAMS ((void));
90
 
91
static void d10v_eva_get_trace_data PARAMS ((void));
92
 
93
static int prologue_find_regs PARAMS ((unsigned short op, struct frame_info * fi, CORE_ADDR addr));
94
 
95
extern void d10v_frame_init_saved_regs PARAMS ((struct frame_info *));
96
 
97
static void do_d10v_pop_frame PARAMS ((struct frame_info * fi));
98
 
99
int
100
d10v_frame_chain_valid (chain, frame)
101
     CORE_ADDR chain;
102
     struct frame_info *frame;  /* not used here */
103
{
104
  return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START);
105
}
106
 
107
CORE_ADDR
108
d10v_stack_align (CORE_ADDR len)
109
{
110
  return (len + 1) & ~1;
111
}
112
 
113
/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
114
   EXTRACT_RETURN_VALUE?  GCC_P is true if compiled with gcc
115
   and TYPE is the type (which is known to be struct, union or array).
116
 
117
   The d10v returns anything less than 8 bytes in size in
118
   registers. */
119
 
120
int
121
d10v_use_struct_convention (gcc_p, type)
122
     int gcc_p;
123
     struct type *type;
124
{
125
  return (TYPE_LENGTH (type) > 8);
126
}
127
 
128
 
129
unsigned char *
130
d10v_breakpoint_from_pc (pcptr, lenptr)
131
     CORE_ADDR *pcptr;
132
     int *lenptr;
133
{
134
  static unsigned char breakpoint[] =
135
  {0x2f, 0x90, 0x5e, 0x00};
136
  *lenptr = sizeof (breakpoint);
137
  return breakpoint;
138
}
139
 
140
/* Map the REG_NR onto an ascii name.  Return NULL or an empty string
141
   when the reg_nr isn't valid. */
142
 
143
enum ts2_regnums
144
  {
145
    TS2_IMAP0_REGNUM = 32,
146
    TS2_DMAP_REGNUM = 34,
147
    TS2_NR_DMAP_REGS = 1,
148
    TS2_A0_REGNUM = 35
149
  };
150
 
151
static char *
152
d10v_ts2_register_name (int reg_nr)
153
{
154
  static char *register_names[] =
155
  {
156
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
157
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
158
    "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
159
    "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
160
    "imap0", "imap1", "dmap", "a0", "a1"
161
  };
162
  if (reg_nr < 0)
163
    return NULL;
164
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
165
    return NULL;
166
  return register_names[reg_nr];
167
}
168
 
169
enum ts3_regnums
170
  {
171
    TS3_IMAP0_REGNUM = 36,
172
    TS3_DMAP0_REGNUM = 38,
173
    TS3_NR_DMAP_REGS = 4,
174
    TS3_A0_REGNUM = 32
175
  };
176
 
177
static char *
178
d10v_ts3_register_name (int reg_nr)
179
{
180
  static char *register_names[] =
181
  {
182
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184
    "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
185
    "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
186
    "a0", "a1",
187
    "spi", "spu",
188
    "imap0", "imap1",
189
    "dmap0", "dmap1", "dmap2", "dmap3"
190
  };
191
  if (reg_nr < 0)
192
    return NULL;
193
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
194
    return NULL;
195
  return register_names[reg_nr];
196
}
197
 
198
/* Access the DMAP/IMAP registers in a target independant way. */
199
 
200
static unsigned long
201
d10v_ts2_dmap_register (int reg_nr)
202
{
203
  switch (reg_nr)
204
    {
205
    case 0:
206
    case 1:
207
      return 0x2000;
208
    case 2:
209
      return read_register (TS2_DMAP_REGNUM);
210
    default:
211
      return 0;
212
    }
213
}
214
 
215
static unsigned long
216
d10v_ts3_dmap_register (int reg_nr)
217
{
218
  return read_register (TS3_DMAP0_REGNUM + reg_nr);
219
}
220
 
221
static unsigned long
222
d10v_dmap_register (int reg_nr)
223
{
224
  return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
225
}
226
 
227
static unsigned long
228
d10v_ts2_imap_register (int reg_nr)
229
{
230
  return read_register (TS2_IMAP0_REGNUM + reg_nr);
231
}
232
 
233
static unsigned long
234
d10v_ts3_imap_register (int reg_nr)
235
{
236
  return read_register (TS3_IMAP0_REGNUM + reg_nr);
237
}
238
 
239
static unsigned long
240
d10v_imap_register (int reg_nr)
241
{
242
  return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
243
}
244
 
245
/* MAP GDB's internal register numbering (determined by the layout fo
246
   the REGISTER_BYTE array) onto the simulator's register
247
   numbering. */
248
 
249
static int
250
d10v_ts2_register_sim_regno (int nr)
251
{
252
  if (nr >= TS2_IMAP0_REGNUM
253
      && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
254
    return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
255
  if (nr == TS2_DMAP_REGNUM)
256
    return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
257
  if (nr >= TS2_A0_REGNUM
258
      && nr < TS2_A0_REGNUM + NR_A_REGS)
259
    return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
260
  return nr;
261
}
262
 
263
static int
264
d10v_ts3_register_sim_regno (int nr)
265
{
266
  if (nr >= TS3_IMAP0_REGNUM
267
      && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
268
    return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
269
  if (nr >= TS3_DMAP0_REGNUM
270
      && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
271
    return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
272
  if (nr >= TS3_A0_REGNUM
273
      && nr < TS3_A0_REGNUM + NR_A_REGS)
274
    return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
275
  return nr;
276
}
277
 
278
int
279
d10v_register_sim_regno (int nr)
280
{
281
  return gdbarch_tdep (current_gdbarch)->register_sim_regno (nr);
282
}
283
 
284
/* Index within `registers' of the first byte of the space for
285
   register REG_NR.  */
286
 
287
int
288
d10v_register_byte (reg_nr)
289
     int reg_nr;
290
{
291
  if (reg_nr < A0_REGNUM)
292
    return (reg_nr * 2);
293
  else if (reg_nr < (A0_REGNUM + NR_A_REGS))
294
    return (A0_REGNUM * 2
295
            + (reg_nr - A0_REGNUM) * 8);
296
  else
297
    return (A0_REGNUM * 2
298
            + NR_A_REGS * 8
299
            + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
300
}
301
 
302
/* Number of bytes of storage in the actual machine representation for
303
   register REG_NR.  */
304
 
305
int
306
d10v_register_raw_size (reg_nr)
307
     int reg_nr;
308
{
309
  if (reg_nr < A0_REGNUM)
310
    return 2;
311
  else if (reg_nr < (A0_REGNUM + NR_A_REGS))
312
    return 8;
313
  else
314
    return 2;
315
}
316
 
317
/* Number of bytes of storage in the program's representation
318
   for register N.  */
319
 
320
int
321
d10v_register_virtual_size (reg_nr)
322
     int reg_nr;
323
{
324
  return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr));
325
}
326
 
327
/* Return the GDB type object for the "standard" data type
328
   of data in register N.  */
329
 
330
struct type *
331
d10v_register_virtual_type (reg_nr)
332
     int reg_nr;
333
{
334
  if (reg_nr >= A0_REGNUM
335
      && reg_nr < (A0_REGNUM + NR_A_REGS))
336
    return builtin_type_int64;
337
  else if (reg_nr == PC_REGNUM
338
           || reg_nr == SP_REGNUM)
339
    return builtin_type_int32;
340
  else
341
    return builtin_type_int16;
342
}
343
 
344
/* convert $pc and $sp to/from virtual addresses */
345
int
346
d10v_register_convertible (nr)
347
     int nr;
348
{
349
  return ((nr) == PC_REGNUM || (nr) == SP_REGNUM);
350
}
351
 
352
void
353
d10v_register_convert_to_virtual (regnum, type, from, to)
354
     int regnum;
355
     struct type *type;
356
     char *from;
357
     char *to;
358
{
359
  ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum));
360
  if (regnum == PC_REGNUM)
361
    x = (x << 2) | IMEM_START;
362
  else
363
    x |= DMEM_START;
364
  store_unsigned_integer (to, TYPE_LENGTH (type), x);
365
}
366
 
367
void
368
d10v_register_convert_to_raw (type, regnum, from, to)
369
     struct type *type;
370
     int regnum;
371
     char *from;
372
     char *to;
373
{
374
  ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type));
375
  x &= 0x3ffff;
376
  if (regnum == PC_REGNUM)
377
    x >>= 2;
378
  store_unsigned_integer (to, 2, x);
379
}
380
 
381
 
382
CORE_ADDR
383
d10v_make_daddr (x)
384
     CORE_ADDR x;
385
{
386
  return ((x) | DMEM_START);
387
}
388
 
389
CORE_ADDR
390
d10v_make_iaddr (x)
391
     CORE_ADDR x;
392
{
393
  return (((x) << 2) | IMEM_START);
394
}
395
 
396
int
397
d10v_daddr_p (x)
398
     CORE_ADDR x;
399
{
400
  return (((x) & 0x3000000) == DMEM_START);
401
}
402
 
403
int
404
d10v_iaddr_p (x)
405
     CORE_ADDR x;
406
{
407
  return (((x) & 0x3000000) == IMEM_START);
408
}
409
 
410
 
411
CORE_ADDR
412
d10v_convert_iaddr_to_raw (x)
413
     CORE_ADDR x;
414
{
415
  return (((x) >> 2) & 0xffff);
416
}
417
 
418
CORE_ADDR
419
d10v_convert_daddr_to_raw (x)
420
     CORE_ADDR x;
421
{
422
  return ((x) & 0xffff);
423
}
424
 
425
/* Store the address of the place in which to copy the structure the
426
   subroutine will return.  This is called from call_function.
427
 
428
   We store structs through a pointer passed in the first Argument
429
   register. */
430
 
431
void
432
d10v_store_struct_return (addr, sp)
433
     CORE_ADDR addr;
434
     CORE_ADDR sp;
435
{
436
  write_register (ARG1_REGNUM, (addr));
437
}
438
 
439
/* Write into appropriate registers a function return value
440
   of type TYPE, given in virtual format.
441
 
442
   Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
443
 
444
void
445
d10v_store_return_value (type, valbuf)
446
     struct type *type;
447
     char *valbuf;
448
{
449
  write_register_bytes (REGISTER_BYTE (RET1_REGNUM),
450
                        valbuf,
451
                        TYPE_LENGTH (type));
452
}
453
 
454
/* Extract from an array REGBUF containing the (raw) register state
455
   the address in which a function should return its structure value,
456
   as a CORE_ADDR (or an expression that can be used as one).  */
457
 
458
CORE_ADDR
459
d10v_extract_struct_value_address (regbuf)
460
     char *regbuf;
461
{
462
  return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM),
463
                           REGISTER_RAW_SIZE (ARG1_REGNUM))
464
          | DMEM_START);
465
}
466
 
467
CORE_ADDR
468
d10v_frame_saved_pc (frame)
469
     struct frame_info *frame;
470
{
471
  return ((frame)->extra_info->return_pc);
472
}
473
 
474
CORE_ADDR
475
d10v_frame_args_address (fi)
476
     struct frame_info *fi;
477
{
478
  return (fi)->frame;
479
}
480
 
481
CORE_ADDR
482
d10v_frame_locals_address (fi)
483
     struct frame_info *fi;
484
{
485
  return (fi)->frame;
486
}
487
 
488
/* Immediately after a function call, return the saved pc.  We can't
489
   use frame->return_pc beause that is determined by reading R13 off
490
   the stack and that may not be written yet. */
491
 
492
CORE_ADDR
493
d10v_saved_pc_after_call (frame)
494
     struct frame_info *frame;
495
{
496
  return ((read_register (LR_REGNUM) << 2)
497
          | IMEM_START);
498
}
499
 
500
/* Discard from the stack the innermost frame, restoring all saved
501
   registers.  */
502
 
503
void
504
d10v_pop_frame ()
505
{
506
  generic_pop_current_frame (do_d10v_pop_frame);
507
}
508
 
509
static void
510
do_d10v_pop_frame (fi)
511
     struct frame_info *fi;
512
{
513
  CORE_ADDR fp;
514
  int regnum;
515
  char raw_buffer[8];
516
 
517
  fp = FRAME_FP (fi);
518
  /* fill out fsr with the address of where each */
519
  /* register was stored in the frame */
520
  d10v_frame_init_saved_regs (fi);
521
 
522
  /* now update the current registers with the old values */
523
  for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
524
    {
525
      if (fi->saved_regs[regnum])
526
        {
527
          read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
528
          write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
529
        }
530
    }
531
  for (regnum = 0; regnum < SP_REGNUM; regnum++)
532
    {
533
      if (fi->saved_regs[regnum])
534
        {
535
          write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
536
        }
537
    }
538
  if (fi->saved_regs[PSW_REGNUM])
539
    {
540
      write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
541
    }
542
 
543
  write_register (PC_REGNUM, read_register (LR_REGNUM));
544
  write_register (SP_REGNUM, fp + fi->extra_info->size);
545
  target_store_registers (-1);
546
  flush_cached_frames ();
547
}
548
 
549
static int
550
check_prologue (op)
551
     unsigned short op;
552
{
553
  /* st  rn, @-sp */
554
  if ((op & 0x7E1F) == 0x6C1F)
555
    return 1;
556
 
557
  /* st2w  rn, @-sp */
558
  if ((op & 0x7E3F) == 0x6E1F)
559
    return 1;
560
 
561
  /* subi  sp, n */
562
  if ((op & 0x7FE1) == 0x01E1)
563
    return 1;
564
 
565
  /* mv  r11, sp */
566
  if (op == 0x417E)
567
    return 1;
568
 
569
  /* nop */
570
  if (op == 0x5E00)
571
    return 1;
572
 
573
  /* st  rn, @sp */
574
  if ((op & 0x7E1F) == 0x681E)
575
    return 1;
576
 
577
  /* st2w  rn, @sp */
578
  if ((op & 0x7E3F) == 0x3A1E)
579
    return 1;
580
 
581
  return 0;
582
}
583
 
584
CORE_ADDR
585
d10v_skip_prologue (pc)
586
     CORE_ADDR pc;
587
{
588
  unsigned long op;
589
  unsigned short op1, op2;
590
  CORE_ADDR func_addr, func_end;
591
  struct symtab_and_line sal;
592
 
593
  /* If we have line debugging information, then the end of the */
594
  /* prologue should the first assembly instruction of  the first source line */
595
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
596
    {
597
      sal = find_pc_line (func_addr, 0);
598
      if (sal.end && sal.end < func_end)
599
        return sal.end;
600
    }
601
 
602
  if (target_read_memory (pc, (char *) &op, 4))
603
    return pc;                  /* Can't access it -- assume no prologue. */
604
 
605
  while (1)
606
    {
607
      op = (unsigned long) read_memory_integer (pc, 4);
608
      if ((op & 0xC0000000) == 0xC0000000)
609
        {
610
          /* long instruction */
611
          if (((op & 0x3FFF0000) != 0x01FF0000) &&      /* add3 sp,sp,n */
612
              ((op & 0x3F0F0000) != 0x340F0000) &&      /* st  rn, @(offset,sp) */
613
              ((op & 0x3F1F0000) != 0x350F0000))        /* st2w  rn, @(offset,sp) */
614
            break;
615
        }
616
      else
617
        {
618
          /* short instructions */
619
          if ((op & 0xC0000000) == 0x80000000)
620
            {
621
              op2 = (op & 0x3FFF8000) >> 15;
622
              op1 = op & 0x7FFF;
623
            }
624
          else
625
            {
626
              op1 = (op & 0x3FFF8000) >> 15;
627
              op2 = op & 0x7FFF;
628
            }
629
          if (check_prologue (op1))
630
            {
631
              if (!check_prologue (op2))
632
                {
633
                  /* if the previous opcode was really part of the prologue */
634
                  /* and not just a NOP, then we want to break after both instructions */
635
                  if (op1 != 0x5E00)
636
                    pc += 4;
637
                  break;
638
                }
639
            }
640
          else
641
            break;
642
        }
643
      pc += 4;
644
    }
645
  return pc;
646
}
647
 
648
/* Given a GDB frame, determine the address of the calling function's frame.
649
   This will be used to create a new GDB frame struct, and then
650
   INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
651
 */
652
 
653
CORE_ADDR
654
d10v_frame_chain (fi)
655
     struct frame_info *fi;
656
{
657
  d10v_frame_init_saved_regs (fi);
658
 
659
  if (fi->extra_info->return_pc == IMEM_START
660
      || inside_entry_file (fi->extra_info->return_pc))
661
    return (CORE_ADDR) 0;
662
 
663
  if (!fi->saved_regs[FP_REGNUM])
664
    {
665
      if (!fi->saved_regs[SP_REGNUM]
666
          || fi->saved_regs[SP_REGNUM] == STACK_START)
667
        return (CORE_ADDR) 0;
668
 
669
      return fi->saved_regs[SP_REGNUM];
670
    }
671
 
672
  if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
673
                                     REGISTER_RAW_SIZE (FP_REGNUM)))
674
    return (CORE_ADDR) 0;
675
 
676
  return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
677
                                            REGISTER_RAW_SIZE (FP_REGNUM)));
678
}
679
 
680
static int next_addr, uses_frame;
681
 
682
static int
683
prologue_find_regs (op, fi, addr)
684
     unsigned short op;
685
     struct frame_info *fi;
686
     CORE_ADDR addr;
687
{
688
  int n;
689
 
690
  /* st  rn, @-sp */
691
  if ((op & 0x7E1F) == 0x6C1F)
692
    {
693
      n = (op & 0x1E0) >> 5;
694
      next_addr -= 2;
695
      fi->saved_regs[n] = next_addr;
696
      return 1;
697
    }
698
 
699
  /* st2w  rn, @-sp */
700
  else if ((op & 0x7E3F) == 0x6E1F)
701
    {
702
      n = (op & 0x1E0) >> 5;
703
      next_addr -= 4;
704
      fi->saved_regs[n] = next_addr;
705
      fi->saved_regs[n + 1] = next_addr + 2;
706
      return 1;
707
    }
708
 
709
  /* subi  sp, n */
710
  if ((op & 0x7FE1) == 0x01E1)
711
    {
712
      n = (op & 0x1E) >> 1;
713
      if (n == 0)
714
        n = 16;
715
      next_addr -= n;
716
      return 1;
717
    }
718
 
719
  /* mv  r11, sp */
720
  if (op == 0x417E)
721
    {
722
      uses_frame = 1;
723
      return 1;
724
    }
725
 
726
  /* nop */
727
  if (op == 0x5E00)
728
    return 1;
729
 
730
  /* st  rn, @sp */
731
  if ((op & 0x7E1F) == 0x681E)
732
    {
733
      n = (op & 0x1E0) >> 5;
734
      fi->saved_regs[n] = next_addr;
735
      return 1;
736
    }
737
 
738
  /* st2w  rn, @sp */
739
  if ((op & 0x7E3F) == 0x3A1E)
740
    {
741
      n = (op & 0x1E0) >> 5;
742
      fi->saved_regs[n] = next_addr;
743
      fi->saved_regs[n + 1] = next_addr + 2;
744
      return 1;
745
    }
746
 
747
  return 0;
748
}
749
 
750
/* Put here the code to store, into fi->saved_regs, the addresses of
751
   the saved registers of frame described by FRAME_INFO.  This
752
   includes special registers such as pc and fp saved in special ways
753
   in the stack frame.  sp is even more special: the address we return
754
   for it IS the sp for the next frame. */
755
 
756
void
757
d10v_frame_init_saved_regs (fi)
758
     struct frame_info *fi;
759
{
760
  CORE_ADDR fp, pc;
761
  unsigned long op;
762
  unsigned short op1, op2;
763
  int i;
764
 
765
  fp = fi->frame;
766
  memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
767
  next_addr = 0;
768
 
769
  pc = get_pc_function_start (fi->pc);
770
 
771
  uses_frame = 0;
772
  while (1)
773
    {
774
      op = (unsigned long) read_memory_integer (pc, 4);
775
      if ((op & 0xC0000000) == 0xC0000000)
776
        {
777
          /* long instruction */
778
          if ((op & 0x3FFF0000) == 0x01FF0000)
779
            {
780
              /* add3 sp,sp,n */
781
              short n = op & 0xFFFF;
782
              next_addr += n;
783
            }
784
          else if ((op & 0x3F0F0000) == 0x340F0000)
785
            {
786
              /* st  rn, @(offset,sp) */
787
              short offset = op & 0xFFFF;
788
              short n = (op >> 20) & 0xF;
789
              fi->saved_regs[n] = next_addr + offset;
790
            }
791
          else if ((op & 0x3F1F0000) == 0x350F0000)
792
            {
793
              /* st2w  rn, @(offset,sp) */
794
              short offset = op & 0xFFFF;
795
              short n = (op >> 20) & 0xF;
796
              fi->saved_regs[n] = next_addr + offset;
797
              fi->saved_regs[n + 1] = next_addr + offset + 2;
798
            }
799
          else
800
            break;
801
        }
802
      else
803
        {
804
          /* short instructions */
805
          if ((op & 0xC0000000) == 0x80000000)
806
            {
807
              op2 = (op & 0x3FFF8000) >> 15;
808
              op1 = op & 0x7FFF;
809
            }
810
          else
811
            {
812
              op1 = (op & 0x3FFF8000) >> 15;
813
              op2 = op & 0x7FFF;
814
            }
815
          if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc))
816
            break;
817
        }
818
      pc += 4;
819
    }
820
 
821
  fi->extra_info->size = -next_addr;
822
 
823
  if (!(fp & 0xffff))
824
    fp = D10V_MAKE_DADDR (read_register (SP_REGNUM));
825
 
826
  for (i = 0; i < NUM_REGS - 1; i++)
827
    if (fi->saved_regs[i])
828
      {
829
        fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
830
      }
831
 
832
  if (fi->saved_regs[LR_REGNUM])
833
    {
834
      CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM));
835
      fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc);
836
    }
837
  else
838
    {
839
      fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM));
840
    }
841
 
842
  /* th SP is not normally (ever?) saved, but check anyway */
843
  if (!fi->saved_regs[SP_REGNUM])
844
    {
845
      /* if the FP was saved, that means the current FP is valid, */
846
      /* otherwise, it isn't being used, so we use the SP instead */
847
      if (uses_frame)
848
        fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size;
849
      else
850
        {
851
          fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
852
          fi->extra_info->frameless = 1;
853
          fi->saved_regs[FP_REGNUM] = 0;
854
        }
855
    }
856
}
857
 
858
void
859
d10v_init_extra_frame_info (fromleaf, fi)
860
     int fromleaf;
861
     struct frame_info *fi;
862
{
863
  fi->extra_info = (struct frame_extra_info *)
864
    frame_obstack_alloc (sizeof (struct frame_extra_info));
865
  frame_saved_regs_zalloc (fi);
866
 
867
  fi->extra_info->frameless = 0;
868
  fi->extra_info->size = 0;
869
  fi->extra_info->return_pc = 0;
870
 
871
  /* The call dummy doesn't save any registers on the stack, so we can
872
     return now.  */
873
  if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
874
    {
875
      return;
876
    }
877
  else
878
    {
879
      d10v_frame_init_saved_regs (fi);
880
    }
881
}
882
 
883
static void
884
show_regs (args, from_tty)
885
     char *args;
886
     int from_tty;
887
{
888
  int a;
889
  printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
890
                   (long) read_register (PC_REGNUM),
891
                   (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)),
892
                   (long) read_register (PSW_REGNUM),
893
                   (long) read_register (24),
894
                   (long) read_register (25),
895
                   (long) read_register (23));
896
  printf_filtered ("R0-R7  %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
897
                   (long) read_register (0),
898
                   (long) read_register (1),
899
                   (long) read_register (2),
900
                   (long) read_register (3),
901
                   (long) read_register (4),
902
                   (long) read_register (5),
903
                   (long) read_register (6),
904
                   (long) read_register (7));
905
  printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
906
                   (long) read_register (8),
907
                   (long) read_register (9),
908
                   (long) read_register (10),
909
                   (long) read_register (11),
910
                   (long) read_register (12),
911
                   (long) read_register (13),
912
                   (long) read_register (14),
913
                   (long) read_register (15));
914
  for (a = 0; a < NR_IMAP_REGS; a++)
915
    {
916
      if (a > 0)
917
        printf_filtered ("    ");
918
      printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
919
    }
920
  if (NR_DMAP_REGS == 1)
921
    printf_filtered ("    DMAP %04lx\n", d10v_dmap_register (2));
922
  else
923
    {
924
      for (a = 0; a < NR_DMAP_REGS; a++)
925
        {
926
          printf_filtered ("    DMAP%d %04lx", a, d10v_dmap_register (a));
927
        }
928
      printf_filtered ("\n");
929
    }
930
  printf_filtered ("A0-A%d", NR_A_REGS - 1);
931
  for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
932
    {
933
      char num[MAX_REGISTER_RAW_SIZE];
934
      int i;
935
      printf_filtered ("  ");
936
      read_register_gen (a, (char *) &num);
937
      for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
938
        {
939
          printf_filtered ("%02x", (num[i] & 0xff));
940
        }
941
    }
942
  printf_filtered ("\n");
943
}
944
 
945
CORE_ADDR
946
d10v_read_pc (pid)
947
     int pid;
948
{
949
  int save_pid;
950
  CORE_ADDR pc;
951
  CORE_ADDR retval;
952
 
953
  save_pid = inferior_pid;
954
  inferior_pid = pid;
955
  pc = (int) read_register (PC_REGNUM);
956
  inferior_pid = save_pid;
957
  retval = D10V_MAKE_IADDR (pc);
958
  return retval;
959
}
960
 
961
void
962
d10v_write_pc (val, pid)
963
     CORE_ADDR val;
964
     int pid;
965
{
966
  int save_pid;
967
 
968
  save_pid = inferior_pid;
969
  inferior_pid = pid;
970
  write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val));
971
  inferior_pid = save_pid;
972
}
973
 
974
CORE_ADDR
975
d10v_read_sp ()
976
{
977
  return (D10V_MAKE_DADDR (read_register (SP_REGNUM)));
978
}
979
 
980
void
981
d10v_write_sp (val)
982
     CORE_ADDR val;
983
{
984
  write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val));
985
}
986
 
987
void
988
d10v_write_fp (val)
989
     CORE_ADDR val;
990
{
991
  write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val));
992
}
993
 
994
CORE_ADDR
995
d10v_read_fp ()
996
{
997
  return (D10V_MAKE_DADDR (read_register (FP_REGNUM)));
998
}
999
 
1000
/* Function: push_return_address (pc)
1001
   Set up the return address for the inferior function call.
1002
   Needed for targets where we don't actually execute a JSR/BSR instruction */
1003
 
1004
CORE_ADDR
1005
d10v_push_return_address (pc, sp)
1006
     CORE_ADDR pc;
1007
     CORE_ADDR sp;
1008
{
1009
  write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ()));
1010
  return sp;
1011
}
1012
 
1013
 
1014
/* When arguments must be pushed onto the stack, they go on in reverse
1015
   order.  The below implements a FILO (stack) to do this. */
1016
 
1017
struct stack_item
1018
{
1019
  int len;
1020
  struct stack_item *prev;
1021
  void *data;
1022
};
1023
 
1024
static struct stack_item *push_stack_item PARAMS ((struct stack_item * prev, void *contents, int len));
1025
static struct stack_item *
1026
push_stack_item (prev, contents, len)
1027
     struct stack_item *prev;
1028
     void *contents;
1029
     int len;
1030
{
1031
  struct stack_item *si;
1032
  si = xmalloc (sizeof (struct stack_item));
1033
  si->data = xmalloc (len);
1034
  si->len = len;
1035
  si->prev = prev;
1036
  memcpy (si->data, contents, len);
1037
  return si;
1038
}
1039
 
1040
static struct stack_item *pop_stack_item PARAMS ((struct stack_item * si));
1041
static struct stack_item *
1042
pop_stack_item (si)
1043
     struct stack_item *si;
1044
{
1045
  struct stack_item *dead = si;
1046
  si = si->prev;
1047
  free (dead->data);
1048
  free (dead);
1049
  return si;
1050
}
1051
 
1052
 
1053
CORE_ADDR
1054
d10v_push_arguments (nargs, args, sp, struct_return, struct_addr)
1055
     int nargs;
1056
     value_ptr *args;
1057
     CORE_ADDR sp;
1058
     int struct_return;
1059
     CORE_ADDR struct_addr;
1060
{
1061
  int i;
1062
  int regnum = ARG1_REGNUM;
1063
  struct stack_item *si = NULL;
1064
 
1065
  /* Fill in registers and arg lists */
1066
  for (i = 0; i < nargs; i++)
1067
    {
1068
      value_ptr arg = args[i];
1069
      struct type *type = check_typedef (VALUE_TYPE (arg));
1070
      char *contents = VALUE_CONTENTS (arg);
1071
      int len = TYPE_LENGTH (type);
1072
      /* printf ("push: type=%d len=%d\n", type->code, len); */
1073
      if (TYPE_CODE (type) == TYPE_CODE_PTR)
1074
        {
1075
          /* pointers require special handling - first convert and
1076
             then store */
1077
          long val = extract_signed_integer (contents, len);
1078
          len = 2;
1079
          if (TYPE_TARGET_TYPE (type)
1080
              && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
1081
            {
1082
              /* function pointer */
1083
              val = D10V_CONVERT_IADDR_TO_RAW (val);
1084
            }
1085
          else if (D10V_IADDR_P (val))
1086
            {
1087
              /* also function pointer! */
1088
              val = D10V_CONVERT_DADDR_TO_RAW (val);
1089
            }
1090
          else
1091
            {
1092
              /* data pointer */
1093
              val &= 0xFFFF;
1094
            }
1095
          if (regnum <= ARGN_REGNUM)
1096
            write_register (regnum++, val & 0xffff);
1097
          else
1098
            {
1099
              char ptr[2];
1100
              /* arg will go onto stack */
1101
              store_address (ptr, 2, val & 0xffff);
1102
              si = push_stack_item (si, ptr, 2);
1103
            }
1104
        }
1105
      else
1106
        {
1107
          int aligned_regnum = (regnum + 1) & ~1;
1108
          if (len <= 2 && regnum <= ARGN_REGNUM)
1109
            /* fits in a single register, do not align */
1110
            {
1111
              long val = extract_unsigned_integer (contents, len);
1112
              write_register (regnum++, val);
1113
            }
1114
          else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
1115
            /* value fits in remaining registers, store keeping left
1116
               aligned */
1117
            {
1118
              int b;
1119
              regnum = aligned_regnum;
1120
              for (b = 0; b < (len & ~1); b += 2)
1121
                {
1122
                  long val = extract_unsigned_integer (&contents[b], 2);
1123
                  write_register (regnum++, val);
1124
                }
1125
              if (b < len)
1126
                {
1127
                  long val = extract_unsigned_integer (&contents[b], 1);
1128
                  write_register (regnum++, (val << 8));
1129
                }
1130
            }
1131
          else
1132
            {
1133
              /* arg will go onto stack */
1134
              regnum = ARGN_REGNUM + 1;
1135
              si = push_stack_item (si, contents, len);
1136
            }
1137
        }
1138
    }
1139
 
1140
  while (si)
1141
    {
1142
      sp = (sp - si->len) & ~1;
1143
      write_memory (sp, si->data, si->len);
1144
      si = pop_stack_item (si);
1145
    }
1146
 
1147
  return sp;
1148
}
1149
 
1150
 
1151
/* Given a return value in `regbuf' with a type `valtype',
1152
   extract and copy its value into `valbuf'.  */
1153
 
1154
void
1155
d10v_extract_return_value (type, regbuf, valbuf)
1156
     struct type *type;
1157
     char regbuf[REGISTER_BYTES];
1158
     char *valbuf;
1159
{
1160
  int len;
1161
  /*    printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)));  */
1162
  if (TYPE_CODE (type) == TYPE_CODE_PTR
1163
      && TYPE_TARGET_TYPE (type)
1164
      && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
1165
    {
1166
      /* pointer to function */
1167
      int num;
1168
      short snum;
1169
      snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1170
      store_address (valbuf, 4, D10V_MAKE_IADDR (snum));
1171
    }
1172
  else if (TYPE_CODE (type) == TYPE_CODE_PTR)
1173
    {
1174
      /* pointer to data */
1175
      int num;
1176
      short snum;
1177
      snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1178
      store_address (valbuf, 4, D10V_MAKE_DADDR (snum));
1179
    }
1180
  else
1181
    {
1182
      len = TYPE_LENGTH (type);
1183
      if (len == 1)
1184
        {
1185
          unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1186
          store_unsigned_integer (valbuf, 1, c);
1187
        }
1188
      else if ((len & 1) == 0)
1189
        memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
1190
      else
1191
        {
1192
          /* For return values of odd size, the first byte is in the
1193
             least significant part of the first register.  The
1194
             remaining bytes in remaining registers. Interestingly,
1195
             when such values are passed in, the last byte is in the
1196
             most significant byte of that same register - wierd. */
1197
          memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
1198
        }
1199
    }
1200
}
1201
 
1202
/* Translate a GDB virtual ADDR/LEN into a format the remote target
1203
   understands.  Returns number of bytes that can be transfered
1204
   starting at TARG_ADDR.  Return ZERO if no bytes can be transfered
1205
   (segmentation fault).  Since the simulator knows all about how the
1206
   VM system works, we just call that to do the translation. */
1207
 
1208
static void
1209
remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1210
                                    CORE_ADDR *targ_addr, int *targ_len)
1211
{
1212
  long out_addr;
1213
  long out_len;
1214
  out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
1215
                                     &out_addr,
1216
                                     d10v_dmap_register,
1217
                                     d10v_imap_register);
1218
  *targ_addr = out_addr;
1219
  *targ_len = out_len;
1220
}
1221
 
1222
 
1223
/* The following code implements access to, and display of, the D10V's
1224
   instruction trace buffer.  The buffer consists of 64K or more
1225
   4-byte words of data, of which each words includes an 8-bit count,
1226
   an 8-bit segment number, and a 16-bit instruction address.
1227
 
1228
   In theory, the trace buffer is continuously capturing instruction
1229
   data that the CPU presents on its "debug bus", but in practice, the
1230
   ROMified GDB stub only enables tracing when it continues or steps
1231
   the program, and stops tracing when the program stops; so it
1232
   actually works for GDB to read the buffer counter out of memory and
1233
   then read each trace word.  The counter records where the tracing
1234
   stops, but there is no record of where it started, so we remember
1235
   the PC when we resumed and then search backwards in the trace
1236
   buffer for a word that includes that address.  This is not perfect,
1237
   because you will miss trace data if the resumption PC is the target
1238
   of a branch.  (The value of the buffer counter is semi-random, any
1239
   trace data from a previous program stop is gone.)  */
1240
 
1241
/* The address of the last word recorded in the trace buffer.  */
1242
 
1243
#define DBBC_ADDR (0xd80000)
1244
 
1245
/* The base of the trace buffer, at least for the "Board_0".  */
1246
 
1247
#define TRACE_BUFFER_BASE (0xf40000)
1248
 
1249
static void trace_command PARAMS ((char *, int));
1250
 
1251
static void untrace_command PARAMS ((char *, int));
1252
 
1253
static void trace_info PARAMS ((char *, int));
1254
 
1255
static void tdisassemble_command PARAMS ((char *, int));
1256
 
1257
static void display_trace PARAMS ((int, int));
1258
 
1259
/* True when instruction traces are being collected.  */
1260
 
1261
static int tracing;
1262
 
1263
/* Remembered PC.  */
1264
 
1265
static CORE_ADDR last_pc;
1266
 
1267
/* True when trace output should be displayed whenever program stops.  */
1268
 
1269
static int trace_display;
1270
 
1271
/* True when trace listing should include source lines.  */
1272
 
1273
static int default_trace_show_source = 1;
1274
 
1275
struct trace_buffer
1276
  {
1277
    int size;
1278
    short *counts;
1279
    CORE_ADDR *addrs;
1280
  }
1281
trace_data;
1282
 
1283
static void
1284
trace_command (args, from_tty)
1285
     char *args;
1286
     int from_tty;
1287
{
1288
  /* Clear the host-side trace buffer, allocating space if needed.  */
1289
  trace_data.size = 0;
1290
  if (trace_data.counts == NULL)
1291
    trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1292
  if (trace_data.addrs == NULL)
1293
    trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1294
 
1295
  tracing = 1;
1296
 
1297
  printf_filtered ("Tracing is now on.\n");
1298
}
1299
 
1300
static void
1301
untrace_command (args, from_tty)
1302
     char *args;
1303
     int from_tty;
1304
{
1305
  tracing = 0;
1306
 
1307
  printf_filtered ("Tracing is now off.\n");
1308
}
1309
 
1310
static void
1311
trace_info (args, from_tty)
1312
     char *args;
1313
     int from_tty;
1314
{
1315
  int i;
1316
 
1317
  if (trace_data.size)
1318
    {
1319
      printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1320
 
1321
      for (i = 0; i < trace_data.size; ++i)
1322
        {
1323
          printf_filtered ("%d: %d instruction%s at 0x%s\n",
1324
                           i,
1325
                           trace_data.counts[i],
1326
                           (trace_data.counts[i] == 1 ? "" : "s"),
1327
                           paddr_nz (trace_data.addrs[i]));
1328
        }
1329
    }
1330
  else
1331
    printf_filtered ("No entries in trace buffer.\n");
1332
 
1333
  printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1334
}
1335
 
1336
/* Print the instruction at address MEMADDR in debugged memory,
1337
   on STREAM.  Returns length of the instruction, in bytes.  */
1338
 
1339
static int
1340
print_insn (memaddr, stream)
1341
     CORE_ADDR memaddr;
1342
     struct ui_file *stream;
1343
{
1344
  /* If there's no disassembler, something is very wrong.  */
1345
  if (tm_print_insn == NULL)
1346
    internal_error ("print_insn: no disassembler");
1347
 
1348
  if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1349
    tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1350
  else
1351
    tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1352
  return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1353
}
1354
 
1355
static void
1356
d10v_eva_prepare_to_trace ()
1357
{
1358
  if (!tracing)
1359
    return;
1360
 
1361
  last_pc = read_register (PC_REGNUM);
1362
}
1363
 
1364
/* Collect trace data from the target board and format it into a form
1365
   more useful for display.  */
1366
 
1367
static void
1368
d10v_eva_get_trace_data ()
1369
{
1370
  int count, i, j, oldsize;
1371
  int trace_addr, trace_seg, trace_cnt, next_cnt;
1372
  unsigned int last_trace, trace_word, next_word;
1373
  unsigned int *tmpspace;
1374
 
1375
  if (!tracing)
1376
    return;
1377
 
1378
  tmpspace = xmalloc (65536 * sizeof (unsigned int));
1379
 
1380
  last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1381
 
1382
  /* Collect buffer contents from the target, stopping when we reach
1383
     the word recorded when execution resumed.  */
1384
 
1385
  count = 0;
1386
  while (last_trace > 0)
1387
    {
1388
      QUIT;
1389
      trace_word =
1390
        read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1391
      trace_addr = trace_word & 0xffff;
1392
      last_trace -= 4;
1393
      /* Ignore an apparently nonsensical entry.  */
1394
      if (trace_addr == 0xffd5)
1395
        continue;
1396
      tmpspace[count++] = trace_word;
1397
      if (trace_addr == last_pc)
1398
        break;
1399
      if (count > 65535)
1400
        break;
1401
    }
1402
 
1403
  /* Move the data to the host-side trace buffer, adjusting counts to
1404
     include the last instruction executed and transforming the address
1405
     into something that GDB likes.  */
1406
 
1407
  for (i = 0; i < count; ++i)
1408
    {
1409
      trace_word = tmpspace[i];
1410
      next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1411
      trace_addr = trace_word & 0xffff;
1412
      next_cnt = (next_word >> 24) & 0xff;
1413
      j = trace_data.size + count - i - 1;
1414
      trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1415
      trace_data.counts[j] = next_cnt + 1;
1416
    }
1417
 
1418
  oldsize = trace_data.size;
1419
  trace_data.size += count;
1420
 
1421
  free (tmpspace);
1422
 
1423
  if (trace_display)
1424
    display_trace (oldsize, trace_data.size);
1425
}
1426
 
1427
static void
1428
tdisassemble_command (arg, from_tty)
1429
     char *arg;
1430
     int from_tty;
1431
{
1432
  int i, count;
1433
  CORE_ADDR low, high;
1434
  char *space_index;
1435
 
1436
  if (!arg)
1437
    {
1438
      low = 0;
1439
      high = trace_data.size;
1440
    }
1441
  else if (!(space_index = (char *) strchr (arg, ' ')))
1442
    {
1443
      low = parse_and_eval_address (arg);
1444
      high = low + 5;
1445
    }
1446
  else
1447
    {
1448
      /* Two arguments.  */
1449
      *space_index = '\0';
1450
      low = parse_and_eval_address (arg);
1451
      high = parse_and_eval_address (space_index + 1);
1452
      if (high < low)
1453
        high = low;
1454
    }
1455
 
1456
  printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
1457
 
1458
  display_trace (low, high);
1459
 
1460
  printf_filtered ("End of trace dump.\n");
1461
  gdb_flush (gdb_stdout);
1462
}
1463
 
1464
static void
1465
display_trace (low, high)
1466
     int low, high;
1467
{
1468
  int i, count, trace_show_source, first, suppress;
1469
  CORE_ADDR next_address;
1470
 
1471
  trace_show_source = default_trace_show_source;
1472
  if (!have_full_symbols () && !have_partial_symbols ())
1473
    {
1474
      trace_show_source = 0;
1475
      printf_filtered ("No symbol table is loaded.  Use the \"file\" command.\n");
1476
      printf_filtered ("Trace will not display any source.\n");
1477
    }
1478
 
1479
  first = 1;
1480
  suppress = 0;
1481
  for (i = low; i < high; ++i)
1482
    {
1483
      next_address = trace_data.addrs[i];
1484
      count = trace_data.counts[i];
1485
      while (count-- > 0)
1486
        {
1487
          QUIT;
1488
          if (trace_show_source)
1489
            {
1490
              struct symtab_and_line sal, sal_prev;
1491
 
1492
              sal_prev = find_pc_line (next_address - 4, 0);
1493
              sal = find_pc_line (next_address, 0);
1494
 
1495
              if (sal.symtab)
1496
                {
1497
                  if (first || sal.line != sal_prev.line)
1498
                    print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1499
                  suppress = 0;
1500
                }
1501
              else
1502
                {
1503
                  if (!suppress)
1504
                    /* FIXME-32x64--assumes sal.pc fits in long.  */
1505
                    printf_filtered ("No source file for address %s.\n",
1506
                                 local_hex_string ((unsigned long) sal.pc));
1507
                  suppress = 1;
1508
                }
1509
            }
1510
          first = 0;
1511
          print_address (next_address, gdb_stdout);
1512
          printf_filtered (":");
1513
          printf_filtered ("\t");
1514
          wrap_here ("    ");
1515
          next_address = next_address + print_insn (next_address, gdb_stdout);
1516
          printf_filtered ("\n");
1517
          gdb_flush (gdb_stdout);
1518
        }
1519
    }
1520
}
1521
 
1522
 
1523
static gdbarch_init_ftype d10v_gdbarch_init;
1524
 
1525
static struct gdbarch *
1526
d10v_gdbarch_init (info, arches)
1527
     struct gdbarch_info info;
1528
     struct gdbarch_list *arches;
1529
{
1530
  static LONGEST d10v_call_dummy_words[] =
1531
  {0};
1532
  struct gdbarch *gdbarch;
1533
  int d10v_num_regs;
1534
  struct gdbarch_tdep *tdep;
1535
  gdbarch_register_name_ftype *d10v_register_name;
1536
 
1537
  /* Find a candidate among the list of pre-declared architectures. */
1538
  arches = gdbarch_list_lookup_by_info (arches, &info);
1539
  if (arches != NULL)
1540
    return arches->gdbarch;
1541
 
1542
  /* None found, create a new architecture from the information
1543
     provided. */
1544
  tdep = XMALLOC (struct gdbarch_tdep);
1545
  gdbarch = gdbarch_alloc (&info, tdep);
1546
 
1547
  switch (info.bfd_arch_info->mach)
1548
    {
1549
    case bfd_mach_d10v_ts2:
1550
      d10v_num_regs = 37;
1551
      d10v_register_name = d10v_ts2_register_name;
1552
      tdep->a0_regnum = TS2_A0_REGNUM;
1553
      tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
1554
      tdep->register_sim_regno = d10v_ts2_register_sim_regno;
1555
      tdep->dmap_register = d10v_ts2_dmap_register;
1556
      tdep->imap_register = d10v_ts2_imap_register;
1557
      break;
1558
    default:
1559
    case bfd_mach_d10v_ts3:
1560
      d10v_num_regs = 42;
1561
      d10v_register_name = d10v_ts3_register_name;
1562
      tdep->a0_regnum = TS3_A0_REGNUM;
1563
      tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
1564
      tdep->register_sim_regno = d10v_ts3_register_sim_regno;
1565
      tdep->dmap_register = d10v_ts3_dmap_register;
1566
      tdep->imap_register = d10v_ts3_imap_register;
1567
      break;
1568
    }
1569
 
1570
  set_gdbarch_read_pc (gdbarch, d10v_read_pc);
1571
  set_gdbarch_write_pc (gdbarch, d10v_write_pc);
1572
  set_gdbarch_read_fp (gdbarch, d10v_read_fp);
1573
  set_gdbarch_write_fp (gdbarch, d10v_write_fp);
1574
  set_gdbarch_read_sp (gdbarch, d10v_read_sp);
1575
  set_gdbarch_write_sp (gdbarch, d10v_write_sp);
1576
 
1577
  set_gdbarch_num_regs (gdbarch, d10v_num_regs);
1578
  set_gdbarch_sp_regnum (gdbarch, 15);
1579
  set_gdbarch_fp_regnum (gdbarch, 11);
1580
  set_gdbarch_pc_regnum (gdbarch, 18);
1581
  set_gdbarch_register_name (gdbarch, d10v_register_name);
1582
  set_gdbarch_register_size (gdbarch, 2);
1583
  set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
1584
  set_gdbarch_register_byte (gdbarch, d10v_register_byte);
1585
  set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
1586
  set_gdbarch_max_register_raw_size (gdbarch, 8);
1587
  set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size);
1588
  set_gdbarch_max_register_virtual_size (gdbarch, 8);
1589
  set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
1590
 
1591
  set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1592
  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1593
  set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1594
  set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1595
  set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1596
  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1597
  set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1598
  set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1599
 
1600
  set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1601
  set_gdbarch_call_dummy_length (gdbarch, 0);
1602
  set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1603
  set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1604
  set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
1605
  set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1606
  set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1607
  set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1608
  set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
1609
  set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
1610
  set_gdbarch_call_dummy_p (gdbarch, 1);
1611
  set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1612
  set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1613
  set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1614
 
1615
  set_gdbarch_register_convertible (gdbarch, d10v_register_convertible);
1616
  set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual);
1617
  set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw);
1618
 
1619
  set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
1620
  set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
1621
  set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1622
  set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
1623
 
1624
  set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr);
1625
  set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr);
1626
  set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p);
1627
  set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p);
1628
  set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw);
1629
  set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw);
1630
 
1631
  set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
1632
  set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
1633
  set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
1634
  set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
1635
 
1636
  set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
1637
  set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
1638
 
1639
  set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
1640
 
1641
  set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
1642
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1643
  set_gdbarch_decr_pc_after_break (gdbarch, 4);
1644
  set_gdbarch_function_start_offset (gdbarch, 0);
1645
  set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
1646
 
1647
  set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
1648
 
1649
  set_gdbarch_frame_args_skip (gdbarch, 0);
1650
  set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1651
  set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
1652
  set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
1653
  set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
1654
  set_gdbarch_frame_args_address (gdbarch, d10v_frame_args_address);
1655
  set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address);
1656
  set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
1657
  set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1658
 
1659
  return gdbarch;
1660
}
1661
 
1662
 
1663
extern void (*target_resume_hook) PARAMS ((void));
1664
extern void (*target_wait_loop_hook) PARAMS ((void));
1665
 
1666
void
1667
_initialize_d10v_tdep ()
1668
{
1669
  register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
1670
 
1671
  tm_print_insn = print_insn_d10v;
1672
 
1673
  target_resume_hook = d10v_eva_prepare_to_trace;
1674
  target_wait_loop_hook = d10v_eva_get_trace_data;
1675
 
1676
  add_com ("regs", class_vars, show_regs, "Print all registers");
1677
 
1678
  add_com ("itrace", class_support, trace_command,
1679
           "Enable tracing of instruction execution.");
1680
 
1681
  add_com ("iuntrace", class_support, untrace_command,
1682
           "Disable tracing of instruction execution.");
1683
 
1684
  add_com ("itdisassemble", class_vars, tdisassemble_command,
1685
           "Disassemble the trace buffer.\n\
1686
Two optional arguments specify a range of trace buffer entries\n\
1687
as reported by info trace (NOT addresses!).");
1688
 
1689
  add_info ("itrace", trace_info,
1690
            "Display info about the trace data buffer.");
1691
 
1692
  add_show_from_set (add_set_cmd ("itracedisplay", no_class,
1693
                                  var_integer, (char *) &trace_display,
1694
                             "Set automatic display of trace.\n", &setlist),
1695
                     &showlist);
1696
  add_show_from_set (add_set_cmd ("itracesource", no_class,
1697
                           var_integer, (char *) &default_trace_show_source,
1698
                      "Set display of source code with trace.\n", &setlist),
1699
                     &showlist);
1700
 
1701
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.