OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.0/] [gdb/] [ocd.h] - Blame information for rev 1772

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 104 markom
/* Definitions for the Macraigor Systems BDM Wiggler
2
   Copyright 1996, 1997 Free Software Foundation, Inc.
3
 
4
   This file is part of GDB.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 59 Temple Place - Suite 330,
19
   Boston, MA 02111-1307, USA.  */
20
 
21
#ifndef OCD_H
22
#define OCD_H
23
 
24
/* Wiggler serial protocol definitions */
25
 
26
#define DLE 020                 /* Quote char */
27
#define SYN 026                 /* Start of packet */
28
#define RAW_SYN ((026 << 8) | 026)      /* get_quoted_char found a naked SYN */
29
 
30
/* Status flags */
31
 
32
#define OCD_FLAG_RESET 0x01     /* Target is being reset */
33
#define OCD_FLAG_STOPPED 0x02   /* Target is halted */
34
#define OCD_FLAG_BDM 0x04       /* Target is in BDM */
35
#define OCD_FLAG_PWF 0x08       /* Power failed */
36
#define OCD_FLAG_CABLE_DISC 0x10        /* BDM cable disconnected */
37
 
38
/* Commands */
39
 
40
#define OCD_AYT 0x0             /* Are you there? */
41
#define OCD_GET_VERSION 0x1     /* Get Version */
42
#define OCD_SET_BAUD_RATE 0x2   /* Set Baud Rate */
43
#define OCD_INIT 0x10           /* Initialize Wiggler */
44
#define OCD_SET_SPEED 0x11      /* Set Speed */
45
#define OCD_GET_STATUS_MASK 0x12        /* Get Status Mask */
46
#define OCD_GET_CTRS 0x13       /* Get Error Counters */
47
#define OCD_SET_FUNC_CODE 0x14  /* Set Function Code */
48
#define OCD_SET_CTL_FLAGS 0x15  /* Set Control Flags */
49
#define OCD_SET_BUF_ADDR 0x16   /* Set Register Buffer Address */
50
#define OCD_RUN 0x20            /* Run Target from PC */
51
#define OCD_RUN_ADDR 0x21       /* Run Target from Specified Address */
52
#define OCD_STOP 0x22           /* Stop Target */
53
#define OCD_RESET_RUN 0x23      /* Reset Target and Run */
54
#define OCD_RESET 0x24          /* Reset Target and Halt */
55
#define OCD_STEP 0x25           /* Single step */
56
#define OCD_READ_REGS 0x30      /* Read Registers */
57
#define OCD_WRITE_REGS 0x31     /* Write Registers */
58
#define OCD_READ_MEM 0x32       /* Read Memory */
59
#define OCD_WRITE_MEM 0x33      /* Write Memory */
60
#define OCD_FILL_MEM 0x34       /* Fill Memory */
61
#define OCD_MOVE_MEM 0x35       /* Move Memory */
62
 
63
#define OCD_READ_INT_MEM 0x80   /* Read Internal Memory */
64
#define OCD_WRITE_INT_MEM 0x81  /* Write Internal Memory */
65
#define OCD_JUMP 0x82           /* Jump to Subroutine */
66
 
67
#define OCD_ERASE_FLASH 0x90    /* Erase flash memory */
68
#define OCD_PROGRAM_FLASH 0x91  /* Write flash memory */
69
#define OCD_EXIT_MON 0x93       /* Exit the flash programming monitor  */
70
#define OCD_ENTER_MON 0x94      /* Enter the flash programming monitor  */
71
 
72
#define OCD_SET_STATUS 0x0a     /* Set status */
73
#define OCD_SET_CONNECTION 0xf0 /* Set connection (init Wigglers.dll) */
74
#define OCD_LOG_FILE 0xf1       /* Cmd to get Wigglers.dll to log cmds */
75
#define OCD_FLAG_STOP 0x0       /* Stop the target, enter BDM */
76
#define OCD_FLAG_START 0x01     /* Start the target at PC */
77
#define OCD_FLAG_RETURN_STATUS 0x04     /* Return async status */
78
 
79
/* Target type (for OCD_INIT command) */
80
 
81
enum ocd_target_type
82
  {
83
    OCD_TARGET_CPU32 = 0x0,     /* Moto cpu32 family */
84
    OCD_TARGET_CPU16 = 0x1,
85
    OCD_TARGET_MOTO_PPC = 0x2,  /* Motorola PPC 5xx/8xx */
86
    OCD_TARGET_IBM_PPC = 0x3
87
  };                            /* IBM PPC 4xx */
88
 
89
void ocd_open PARAMS ((char *name, int from_tty, enum ocd_target_type,
90
                       struct target_ops * ops));
91
 
92
void ocd_close PARAMS ((int quitting));
93
 
94
void ocd_detach PARAMS ((char *args, int from_tty));
95
 
96
void ocd_resume PARAMS ((int pid, int step, enum target_signal siggnal));
97
 
98
void ocd_prepare_to_store PARAMS ((void));
99
 
100
void ocd_stop PARAMS ((void));
101
 
102
void ocd_files_info PARAMS ((struct target_ops * ignore));
103
 
104
 
105
int ocd_xfer_memory PARAMS ((CORE_ADDR memaddr, char *myaddr,
106
                             int len, int should_write,
107
                             struct target_ops * target));
108
 
109
void ocd_mourn PARAMS ((void));
110
 
111
void ocd_create_inferior PARAMS ((char *exec_file,
112
                                  char *args,
113
                                  char **env));
114
 
115
int ocd_thread_alive PARAMS ((int th));
116
 
117
void ocd_error PARAMS ((char *s, int error_code));
118
 
119
void ocd_kill PARAMS ((void));
120
 
121
void ocd_load PARAMS ((char *args, int from_tty));
122
 
123
unsigned char *ocd_read_bdm_registers PARAMS ((int first_bdm_regno,
124
                                               int last_bdm_regno,
125
                                               int *reglen));
126
 
127
CORE_ADDR ocd_read_bdm_register PARAMS ((int bdm_regno));
128
 
129
void ocd_write_bdm_registers PARAMS ((int first_bdm_regno,
130
                                      unsigned char *regptr,
131
                                      int reglen));
132
 
133
void ocd_write_bdm_register PARAMS ((int bdm_regno, CORE_ADDR reg));
134
 
135
int ocd_wait PARAMS ((void));
136
 
137
int ocd_insert_breakpoint PARAMS ((CORE_ADDR addr, char *contents_cache));
138
int ocd_remove_breakpoint PARAMS ((CORE_ADDR addr, char *contents_cache));
139
 
140
int ocd_write_bytes PARAMS ((CORE_ADDR memaddr, char *myaddr, int len));
141
 
142
#endif /* OCD_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.