Subversion Repositories or1k

/* Target-dependent code for the SPARC for GDB, the GNU debugger.

   Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997

   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 59 Temple Place - Suite 330,

   Boston, MA 02111-1307, USA.  */

/* ??? Support for calling functions from gdb in sparc64 is unfinished.  */

#include "defs.h"

#include "frame.h"

#include "inferior.h"

#include "obstack.h"

#include "target.h"

#include "value.h"

#include "bfd.h"

#include "gdb_string.h"

#ifdef  USE_PROC_FS

#include <sys/procfs.h>

#endif

#include "gdbcore.h"

#if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)

#define SPARC_HAS_FPU 0

#else

#define SPARC_HAS_FPU 1

#endif

#ifdef GDB_TARGET_IS_SPARC64

#define FP_REGISTER_BYTES (64 * 4)

#else

#define FP_REGISTER_BYTES (32 * 4)

#endif

/* If not defined, assume 32 bit sparc.  */

#ifndef FP_MAX_REGNUM

#define FP_MAX_REGNUM (FP0_REGNUM + 32)

#endif

#define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))

/* From infrun.c */

extern int stop_after_trap;

/* We don't store all registers immediately when requested, since they

   get sent over in large chunks anyway.  Instead, we accumulate most

   of the changes and send them over once.  "deferred_stores" keeps

   track of which sets of registers we have locally-changed copies of,

   so we only need send the groups that have changed.  */

int deferred_stores = 0; /* Cumulates stores we want to do eventually. */

/* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode

   where instructions are big-endian and data are little-endian.

   This flag is set when we detect that the target is of this type. */

int bi_endian = 0;

/* Fetch a single instruction.  Even on bi-endian machines

   such as sparc86x, instructions are always big-endian.  */

static unsigned long

fetch_instruction (pc)

     CORE_ADDR pc;

{

  unsigned long retval;

  int i;

  unsigned char buf[4];

  read_memory (pc, buf, sizeof (buf));

  /* Start at the most significant end of the integer, and work towards

     the least significant.  */

  retval = 0;

  for (i = 0; i < sizeof (buf); ++i)

    retval = (retval << 8) | buf[i];

  return retval;

}

/* Branches with prediction are treated like their non-predicting cousins.  */

/* FIXME: What about floating point branches?  */

/* Macros to extract fields from sparc instructions.  */

#define X_OP(i) (((i) >> 30) & 0x3)

#define X_RD(i) (((i) >> 25) & 0x1f)

#define X_A(i) (((i) >> 29) & 1)

#define X_COND(i) (((i) >> 25) & 0xf)

#define X_OP2(i) (((i) >> 22) & 0x7)

#define X_IMM22(i) ((i) & 0x3fffff)

#define X_OP3(i) (((i) >> 19) & 0x3f)

#define X_RS1(i) (((i) >> 14) & 0x1f)

#define X_I(i) (((i) >> 13) & 1)

#define X_IMM13(i) ((i) & 0x1fff)

/* Sign extension macros.  */

#define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)

#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)

#define X_CC(i) (((i) >> 20) & 3)

#define X_P(i) (((i) >> 19) & 1)

#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)

#define X_RCOND(i) (((i) >> 25) & 7)

#define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)

#define X_FCN(i) (((i) >> 25) & 31)

typedef enum

{

  Error, not_branch, bicc, bicca, ba, baa, ticc, ta,

#ifdef GDB_TARGET_IS_SPARC64

  done_retry

#endif

}

branch_type;

/* Simulate single-step ptrace call for sun4.  Code written by Gary

   Beihl (beihl@mcc.com).  */

/* npc4 and next_pc describe the situation at the time that the

   step-breakpoint was set, not necessary the current value of NPC_REGNUM.  */

static CORE_ADDR next_pc, npc4, target;

static int brknpc4, brktrg;

typedef char binsn_quantum[BREAKPOINT_MAX];

static binsn_quantum break_mem[3];

static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *));

/* single_step() is called just before we want to resume the inferior,

   if we want to single-step it but there is no hardware or kernel single-step

   support (as on all SPARCs).  We find all the possible targets of the

   coming instruction and breakpoint them.

   single_step is also called just after the inferior stops.  If we had

   set up a simulated single-step, we undo our damage.  */

void

sparc_software_single_step (ignore, insert_breakpoints_p)

     enum target_signal ignore; /* pid, but we don't need it */

     int insert_breakpoints_p;

{

  branch_type br;

  CORE_ADDR pc;

  long pc_instruction;

  if (insert_breakpoints_p)

    {

      /* Always set breakpoint for NPC.  */

      next_pc = read_register (NPC_REGNUM);

      npc4 = next_pc + 4;       /* branch not taken */

      target_insert_breakpoint (next_pc, break_mem[0]);

      /* printf_unfiltered ("set break at %x\n",next_pc); */

      pc = read_register (PC_REGNUM);

      pc_instruction = fetch_instruction (pc);

      br = isbranch (pc_instruction, pc, &target);

      brknpc4 = brktrg = 0;

      if (br == bicca)

        {

          /* Conditional annulled branch will either end up at

             npc (if taken) or at npc+4 (if not taken).

             Trap npc+4.  */

          brknpc4 = 1;

          target_insert_breakpoint (npc4, break_mem[1]);

        }

      else if (br == baa && target != next_pc)

        {

          /* Unconditional annulled branch will always end up at

             the target.  */

          brktrg = 1;

          target_insert_breakpoint (target, break_mem[2]);

        }

#ifdef GDB_TARGET_IS_SPARC64

      else if (br == done_retry)

        {

          brktrg = 1;

          target_insert_breakpoint (target, break_mem[2]);

        }

#endif

    }

  else

    {

      /* Remove breakpoints */

      target_remove_breakpoint (next_pc, break_mem[0]);

      if (brknpc4)

        target_remove_breakpoint (npc4, break_mem[1]);

      if (brktrg)

        target_remove_breakpoint (target, break_mem[2]);

    }

}

/* Call this for each newly created frame.  For SPARC, we need to calculate

   the bottom of the frame, and do some extra work if the prologue

   has been generated via the -mflat option to GCC.  In particular,

   we need to know where the previous fp and the pc have been stashed,

   since their exact position within the frame may vary.  */

void

sparc_init_extra_frame_info (fromleaf, fi)

     int fromleaf;

     struct frame_info *fi;

{

  char *name;

  CORE_ADDR prologue_start, prologue_end;

  int insn;

  fi->bottom =

    (fi->next ?

     (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) :

     read_sp ());

  /* If fi->next is NULL, then we already set ->frame by passing read_fp()

     to create_new_frame.  */

  if (fi->next)

    {

      char buf[MAX_REGISTER_RAW_SIZE];

      /* Compute ->frame as if not flat.  If it is flat, we'll change

         it later.  */

      if (fi->next->next != NULL

          && (fi->next->next->signal_handler_caller

              || frame_in_dummy (fi->next->next))

          && frameless_look_for_prologue (fi->next))

        {

          /* A frameless function interrupted by a signal did not change

             the frame pointer, fix up frame pointer accordingly.  */

          fi->frame = FRAME_FP (fi->next);

          fi->bottom = fi->next->bottom;

        }

      else

        {

          /* Should we adjust for stack bias here? */

          get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0);

          fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));

#ifdef GDB_TARGET_IS_SPARC64

          if (fi->frame & 1)

            fi->frame += 2047;

#endif

        }

    }

  /* Decide whether this is a function with a ``flat register window''

     frame.  For such functions, the frame pointer is actually in %i7.  */

  fi->flat = 0;

  fi->in_prologue = 0;

  if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end))

    {

      /* See if the function starts with an add (which will be of a

         negative number if a flat frame) to the sp.  FIXME: Does not

         handle large frames which will need more than one instruction

         to adjust the sp.  */

      insn = fetch_instruction (prologue_start, 4);

      if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0

          && X_I (insn) && X_SIMM13 (insn) < 0)

        {

          int offset = X_SIMM13 (insn);

          /* Then look for a save of %i7 into the frame.  */

          insn = fetch_instruction (prologue_start + 4);

          if (X_OP (insn) == 3

              && X_RD (insn) == 31

              && X_OP3 (insn) == 4

              && X_RS1 (insn) == 14)

            {

              char buf[MAX_REGISTER_RAW_SIZE];

              /* We definitely have a flat frame now.  */

              fi->flat = 1;

              fi->sp_offset = offset;

              /* Overwrite the frame's address with the value in %i7.  */

              get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0);

              fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM));

#ifdef GDB_TARGET_IS_SPARC64

              if (fi->frame & 1)

                fi->frame += 2047;

#endif

              /* Record where the fp got saved.  */

              fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);

              /* Also try to collect where the pc got saved to.  */

              fi->pc_addr = 0;

              insn = fetch_instruction (prologue_start + 12);

              if (X_OP (insn) == 3

                  && X_RD (insn) == 15

                  && X_OP3 (insn) == 4

                  && X_RS1 (insn) == 14)

                fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);

            }

        }

      else

        {

          /* Check if the PC is in the function prologue before a SAVE

             instruction has been executed yet.  If so, set the frame

             to the current value of the stack pointer and set

             the in_prologue flag.  */

          CORE_ADDR addr;

          struct symtab_and_line sal;

          sal = find_pc_line (prologue_start, 0);

          if (sal.line == 0)     /* no line info, use PC */

            prologue_end = fi->pc;

          else if (sal.end < prologue_end)

            prologue_end = sal.end;

          if (fi->pc < prologue_end)

            {

              for (addr = prologue_start; addr < fi->pc; addr += 4)

                {

                  insn = read_memory_integer (addr, 4);

                  if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)

                    break;      /* SAVE seen, stop searching */

                }

              if (addr >= fi->pc)

                {

                  fi->in_prologue = 1;

                  fi->frame = read_register (SP_REGNUM);

                }

            }

        }

    }

  if (fi->next && fi->frame == 0)

    {

      /* Kludge to cause init_prev_frame_info to destroy the new frame.  */

      fi->frame = fi->next->frame;

      fi->pc = fi->next->pc;

    }

}

CORE_ADDR

sparc_frame_chain (frame)

     struct frame_info *frame;

{

  /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain

     value.  If it realy is zero, we detect it later in

     sparc_init_prev_frame.  */

  return (CORE_ADDR) 1;

}

CORE_ADDR

sparc_extract_struct_value_address (regbuf)

     char regbuf[REGISTER_BYTES];

{

  return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM),

                          REGISTER_RAW_SIZE (O0_REGNUM));

}

/* Find the pc saved in frame FRAME.  */

CORE_ADDR

sparc_frame_saved_pc (frame)

     struct frame_info *frame;

{

  char buf[MAX_REGISTER_RAW_SIZE];

  CORE_ADDR addr;

  if (frame->signal_handler_caller)

    {

      /* This is the signal trampoline frame.

         Get the saved PC from the sigcontext structure.  */

#ifndef SIGCONTEXT_PC_OFFSET

#define SIGCONTEXT_PC_OFFSET 12

#endif

      CORE_ADDR sigcontext_addr;

      char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT];

      int saved_pc_offset = SIGCONTEXT_PC_OFFSET;

      char *name = NULL;

      /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext

         as the third parameter.  The offset to the saved pc is 12.  */

      find_pc_partial_function (frame->pc, &name,

                                (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);

      if (name && STREQ (name, "ucbsigvechandler"))

        saved_pc_offset = 12;

      /* The sigcontext address is contained in register O2.  */

      get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL,

                          frame, O0_REGNUM + 2, (enum lval_type *) NULL);

      sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2));

      /* Don't cause a memory_error when accessing sigcontext in case the

         stack layout has changed or the stack is corrupt.  */

      target_read_memory (sigcontext_addr + saved_pc_offset,

                          scbuf, sizeof (scbuf));

      return extract_address (scbuf, sizeof (scbuf));

    }

  else if (frame->in_prologue ||

           (frame->next != NULL

            && (frame->next->signal_handler_caller

                || frame_in_dummy (frame->next))

            && frameless_look_for_prologue (frame)))

    {

      /* A frameless function interrupted by a signal did not save

         the PC, it is still in %o7.  */

      get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL,

                          frame, O7_REGNUM, (enum lval_type *) NULL);

      return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));

    }

  if (frame->flat)

    addr = frame->pc_addr;

  else

    addr = frame->bottom + FRAME_SAVED_I0 +

      SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM);

  if (addr == 0)

    /* A flat frame leaf function might not save the PC anywhere,

       just leave it in %o7.  */

    return PC_ADJUST (read_register (O7_REGNUM));

  read_memory (addr, buf, SPARC_INTREG_SIZE);

  return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));

}

/* Since an individual frame in the frame cache is defined by two

   arguments (a frame pointer and a stack pointer), we need two

   arguments to get info for an arbitrary stack frame.  This routine

   takes two arguments and makes the cached frames look as if these

   two arguments defined a frame on the cache.  This allows the rest

   of info frame to extract the important arguments without

   difficulty.  */

struct frame_info *

setup_arbitrary_frame (argc, argv)

     int argc;

     CORE_ADDR *argv;

{

  struct frame_info *frame;

  if (argc != 2)

    error ("Sparc frame specifications require two arguments: fp and sp");

  frame = create_new_frame (argv[0], 0);

  if (!frame)

    internal_error ("create_new_frame returned invalid frame");

  frame->bottom = argv[1];

  frame->pc = FRAME_SAVED_PC (frame);

  return frame;

}

/* Given a pc value, skip it forward past the function prologue by

   disassembling instructions that appear to be a prologue.

   If FRAMELESS_P is set, we are only testing to see if the function

   is frameless.  This allows a quicker answer.

   This routine should be more specific in its actions; making sure

   that it uses the same register in the initial prologue section.  */

static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *,

                                           struct frame_saved_regs *));

static CORE_ADDR

examine_prologue (start_pc, frameless_p, fi, saved_regs)

     CORE_ADDR start_pc;

     int frameless_p;

     struct frame_info *fi;

     struct frame_saved_regs *saved_regs;

{

  int insn;

  int dest = -1;

  CORE_ADDR pc = start_pc;

  int is_flat = 0;

  insn = fetch_instruction (pc);

  /* Recognize the `sethi' insn and record its destination.  */

  if (X_OP (insn) == 0 && X_OP2 (insn) == 4)

    {

      dest = X_RD (insn);

      pc += 4;

      insn = fetch_instruction (pc);

    }

  /* Recognize an add immediate value to register to either %g1 or

     the destination register recorded above.  Actually, this might

     well recognize several different arithmetic operations.

     It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"

     followed by "save %sp, %g1, %sp" is a valid prologue (Not that

     I imagine any compiler really does that, however).  */

  if (X_OP (insn) == 2

      && X_I (insn)

      && (X_RD (insn) == 1 || X_RD (insn) == dest))

    {

      pc += 4;

      insn = fetch_instruction (pc);

    }

  /* Recognize any SAVE insn.  */

  if (X_OP (insn) == 2 && X_OP3 (insn) == 60)

    {

      pc += 4;

      if (frameless_p)          /* If the save is all we care about, */

        return pc;              /* return before doing more work */

      insn = fetch_instruction (pc);

    }

  /* Recognize add to %sp.  */

  else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0)

    {

      pc += 4;

      if (frameless_p)          /* If the add is all we care about, */

        return pc;              /* return before doing more work */

      is_flat = 1;

      insn = fetch_instruction (pc);

      /* Recognize store of frame pointer (i7).  */

      if (X_OP (insn) == 3

          && X_RD (insn) == 31

          && X_OP3 (insn) == 4

          && X_RS1 (insn) == 14)

        {

          pc += 4;

          insn = fetch_instruction (pc);

          /* Recognize sub %sp, <anything>, %i7.  */

          if (X_OP (insn) == 2

              && X_OP3 (insn) == 4

              && X_RS1 (insn) == 14

              && X_RD (insn) == 31)

            {

              pc += 4;

              insn = fetch_instruction (pc);

            }

          else

            return pc;

        }

      else

        return pc;

    }

  else

    /* Without a save or add instruction, it's not a prologue.  */

    return start_pc;

  while (1)

    {

      /* Recognize stores into the frame from the input registers.

         This recognizes all non alternate stores of input register,

         into a location offset from the frame pointer.  */

      if ((X_OP (insn) == 3

           && (X_OP3 (insn) & 0x3c) == 4        /* Store, non-alternate.  */

           && (X_RD (insn) & 0x18) == 0x18      /* Input register.  */

           && X_I (insn)        /* Immediate mode.  */

           && X_RS1 (insn) == 30        /* Off of frame pointer.  */

      /* Into reserved stack space.  */

           && X_SIMM13 (insn) >= 0x44

           && X_SIMM13 (insn) < 0x5b))

        ;

      else if (is_flat

               && X_OP (insn) == 3

               && X_OP3 (insn) == 4

               && X_RS1 (insn) == 14

        )

        {

          if (saved_regs && X_I (insn))

            saved_regs->regs[X_RD (insn)] =

              fi->frame + fi->sp_offset + X_SIMM13 (insn);

        }

      else

        break;

      pc += 4;

      insn = fetch_instruction (pc);

    }

  return pc;

}

CORE_ADDR

sparc_skip_prologue (start_pc, frameless_p)

     CORE_ADDR start_pc;

     int frameless_p;

{

  return examine_prologue (start_pc, frameless_p, NULL, NULL);

}

/* Check instruction at ADDR to see if it is a branch.

   All non-annulled instructions will go to NPC or will trap.

   Set *TARGET if we find a candidate branch; set to zero if not.

   This isn't static as it's used by remote-sa.sparc.c.  */

static branch_type

isbranch (instruction, addr, target)

     long instruction;

     CORE_ADDR addr, *target;

{

  branch_type val = not_branch;

  long int offset = 0;           /* Must be signed for sign-extend.  */

  *target = 0;

  if (X_OP (instruction) == 0

      && (X_OP2 (instruction) == 2

          || X_OP2 (instruction) == 6

          || X_OP2 (instruction) == 1

          || X_OP2 (instruction) == 3

          || X_OP2 (instruction) == 5

#ifndef GDB_TARGET_IS_SPARC64

          || X_OP2 (instruction) == 7

#endif

      ))

    {

      if (X_COND (instruction) == 8)

        val = X_A (instruction) ? baa : ba;

      else

        val = X_A (instruction) ? bicca : bicc;

      switch (X_OP2 (instruction))

        {

        case 2:

        case 6:

#ifndef GDB_TARGET_IS_SPARC64

        case 7:

#endif

          offset = 4 * X_DISP22 (instruction);

          break;

        case 1:

        case 5:

          offset = 4 * X_DISP19 (instruction);

          break;

        case 3:

          offset = 4 * X_DISP16 (instruction);

          break;

        }

      *target = addr + offset;

    }

#ifdef GDB_TARGET_IS_SPARC64

  else if (X_OP (instruction) == 2

           && X_OP3 (instruction) == 62)

    {

      if (X_FCN (instruction) == 0)

        {

          /* done */

          *target = read_register (TNPC_REGNUM);

          val = done_retry;

        }

      else if (X_FCN (instruction) == 1)

        {

          /* retry */

          *target = read_register (TPC_REGNUM);

          val = done_retry;

        }

    }

#endif

  return val;

}

/* Find register number REGNUM relative to FRAME and put its

   (raw) contents in *RAW_BUFFER.  Set *OPTIMIZED if the variable

   was optimized out (and thus can't be fetched).  If the variable

   was fetched from memory, set *ADDRP to where it was fetched from,

   otherwise it was fetched from a register.

   The argument RAW_BUFFER must point to aligned memory.  */

void

sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)

     char *raw_buffer;

     int *optimized;

     CORE_ADDR *addrp;

     struct frame_info *frame;

     int regnum;

     enum lval_type *lval;

{

  struct frame_info *frame1;

  CORE_ADDR addr;

  if (!target_has_registers)

    error ("No registers.");

  if (optimized)

    *optimized = 0;

  addr = 0;

  /* FIXME This code extracted from infcmd.c; should put elsewhere! */

  if (frame == NULL)

    {

      /* error ("No selected frame."); */

      if (!target_has_registers)

        error ("The program has no registers now.");