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[/] [or1k/] [trunk/] [gdb-5.0/] [opcodes/] [alpha-opc.c] - Blame information for rev 1765

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1 106 markom
/* alpha-opc.c -- Alpha AXP opcode list
2
   Copyright (c) 1996, 1998, 1999 Free Software Foundation, Inc.
3
   Contributed by Richard Henderson <rth@cygnus.com>,
4
   patterned after the PPC opcode handling written by Ian Lance Taylor.
5
 
6
   This file is part of GDB, GAS, and the GNU binutils.
7
 
8
   GDB, GAS, and the GNU binutils are free software; you can redistribute
9
   them and/or modify them under the terms of the GNU General Public
10
   License as published by the Free Software Foundation; either version
11
   2, or (at your option) any later version.
12
 
13
   GDB, GAS, and the GNU binutils are distributed in the hope that they
14
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
15
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
16
   the GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this file; see the file COPYING.  If not, write to the
20
   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21
   02111-1307, USA.  */
22
 
23
#include <stdio.h>
24
#include "ansidecl.h"
25
#include "opcode/alpha.h"
26
#include "bfd.h"
27
#include "opintl.h"
28
 
29
/* This file holds the Alpha AXP opcode table.  The opcode table includes
30
   almost all of the extended instruction mnemonics.  This permits the
31
   disassembler to use them, and simplifies the assembler logic, at the
32
   cost of increasing the table size.  The table is strictly constant
33
   data, so the compiler should be able to put it in the .text section.
34
 
35
   This file also holds the operand table.  All knowledge about inserting
36
   operands into instructions and vice-versa is kept in this file.
37
 
38
   The information for the base instruction set was compiled from the
39
   _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
40
   version 2.
41
 
42
   The information for the post-ev5 architecture extensions BWX, CIX and
43
   MAX came from version 3 of this same document, which is also available
44
   on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
45
   /literature/alphahb2.pdf
46
 
47
   The information for the EV4 PALcode instructions was compiled from
48
   _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
49
   Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
50
   revision dated June 1994.
51
 
52
   The information for the EV5 PALcode instructions was compiled from
53
   _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
54
   Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
55
 
56
/* Local insertion and extraction functions */
57
 
58
static unsigned insert_rba PARAMS((unsigned, int, const char **));
59
static unsigned insert_rca PARAMS((unsigned, int, const char **));
60
static unsigned insert_za PARAMS((unsigned, int, const char **));
61
static unsigned insert_zb PARAMS((unsigned, int, const char **));
62
static unsigned insert_zc PARAMS((unsigned, int, const char **));
63
static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
64
static unsigned insert_jhint PARAMS((unsigned, int, const char **));
65
static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
66
 
67
static int extract_rba PARAMS((unsigned, int *));
68
static int extract_rca PARAMS((unsigned, int *));
69
static int extract_za PARAMS((unsigned, int *));
70
static int extract_zb PARAMS((unsigned, int *));
71
static int extract_zc PARAMS((unsigned, int *));
72
static int extract_bdisp PARAMS((unsigned, int *));
73
static int extract_jhint PARAMS((unsigned, int *));
74
static int extract_ev6hwjhint PARAMS((unsigned, int *));
75
 
76
 
77
/* The operands table  */
78
 
79
const struct alpha_operand alpha_operands[] =
80
{
81
  /* The fields are bits, shift, insert, extract, flags */
82
  /* The zero index is used to indicate end-of-list */
83
#define UNUSED          0
84
  { 0, 0, 0, 0, 0, 0 },
85
 
86
  /* The plain integer register fields */
87
#define RA              (UNUSED + 1)
88
  { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
89
#define RB              (RA + 1)
90
  { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
91
#define RC              (RB + 1)
92
  { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
93
 
94
  /* The plain fp register fields */
95
#define FA              (RC + 1)
96
  { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
97
#define FB              (FA + 1)
98
  { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
99
#define FC              (FB + 1)
100
  { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
101
 
102
  /* The integer registers when they are ZERO */
103
#define ZA              (FC + 1)
104
  { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
105
#define ZB              (ZA + 1)
106
  { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
107
#define ZC              (ZB + 1)
108
  { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
109
 
110
  /* The RB field when it needs parentheses */
111
#define PRB             (ZC + 1)
112
  { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
113
 
114
  /* The RB field when it needs parentheses _and_ a preceding comma */
115
#define CPRB            (PRB + 1)
116
  { 5, 16, 0,
117
    AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
118
 
119
  /* The RB field when it must be the same as the RA field */
120
#define RBA             (CPRB + 1)
121
  { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
122
 
123
  /* The RC field when it must be the same as the RB field */
124
#define RCA             (RBA + 1)
125
  { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
126
 
127
  /* The RC field when it can *default* to RA */
128
#define DRC1            (RCA + 1)
129
  { 5, 0, 0,
130
    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
131
 
132
  /* The RC field when it can *default* to RB */
133
#define DRC2            (DRC1 + 1)
134
  { 5, 0, 0,
135
    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
136
 
137
  /* The FC field when it can *default* to RA */
138
#define DFC1            (DRC2 + 1)
139
  { 5, 0, 0,
140
    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
141
 
142
  /* The FC field when it can *default* to RB */
143
#define DFC2            (DFC1 + 1)
144
  { 5, 0, 0,
145
    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
146
 
147
  /* The unsigned 8-bit literal of Operate format insns */
148
#define LIT             (DFC2 + 1)
149
  { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
150
 
151
  /* The signed 16-bit displacement of Memory format insns.  From here
152
     we can't tell what relocation should be used, so don't use a default. */
153
#define MDISP           (LIT + 1)
154
  { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
155
 
156
  /* The signed "23-bit" aligned displacement of Branch format insns */
157
#define BDISP           (MDISP + 1)
158
  { 21, 0, BFD_RELOC_23_PCREL_S2,
159
    AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
160
 
161
  /* The 26-bit PALcode function */
162
#define PALFN           (BDISP + 1)
163
  { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
164
 
165
  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
166
#define JMPHINT         (PALFN + 1)
167
  { 14, 0, BFD_RELOC_ALPHA_HINT,
168
    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
169
    insert_jhint, extract_jhint },
170
 
171
  /* The optional hint to RET/JSR_COROUTINE */
172
#define RETHINT         (JMPHINT + 1)
173
  { 14, 0, -RETHINT,
174
    AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
175
 
176
  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
177
#define EV4HWDISP       (RETHINT + 1)
178
#define EV6HWDISP       (EV4HWDISP)
179
  { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
180
 
181
  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
182
#define EV4HWINDEX      (EV4HWDISP + 1)
183
  { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
184
 
185
  /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
186
     that occur in DEC PALcode.  */
187
#define EV4EXTHWINDEX   (EV4HWINDEX + 1)
188
  { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
189
 
190
  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
191
#define EV5HWDISP       (EV4EXTHWINDEX + 1)
192
  { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
193
 
194
  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
195
#define EV5HWINDEX      (EV5HWDISP + 1)
196
  { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
197
 
198
  /* The 16-bit combined index/scoreboard mask for the ev6
199
     hw_m[ft]pr (pal19/pal1d) insns */
200
#define EV6HWINDEX      (EV5HWINDEX + 1)
201
  { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
202
 
203
  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
204
#define EV6HWJMPHINT    (EV6HWINDEX+ 1)
205
  { 8, 0, -EV6HWJMPHINT,
206
    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
207
    insert_ev6hwjhint, extract_ev6hwjhint }
208
};
209
 
210
const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
211
 
212
/* The RB field when it is the same as the RA field in the same insn.
213
   This operand is marked fake.  The insertion function just copies
214
   the RA field into the RB field, and the extraction function just
215
   checks that the fields are the same. */
216
 
217
/*ARGSUSED*/
218
static unsigned
219
insert_rba(insn, value, errmsg)
220
     unsigned insn;
221
     int value ATTRIBUTE_UNUSED;
222
     const char **errmsg ATTRIBUTE_UNUSED;
223
{
224
  return insn | (((insn >> 21) & 0x1f) << 16);
225
}
226
 
227
static int
228
extract_rba(insn, invalid)
229
     unsigned insn;
230
     int *invalid;
231
{
232
  if (invalid != (int *) NULL
233
      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
234
    *invalid = 1;
235
  return 0;
236
}
237
 
238
 
239
/* The same for the RC field */
240
 
241
/*ARGSUSED*/
242
static unsigned
243
insert_rca(insn, value, errmsg)
244
     unsigned insn;
245
     int value ATTRIBUTE_UNUSED;
246
     const char **errmsg ATTRIBUTE_UNUSED;
247
{
248
  return insn | ((insn >> 21) & 0x1f);
249
}
250
 
251
static int
252
extract_rca(insn, invalid)
253
     unsigned insn;
254
     int *invalid;
255
{
256
  if (invalid != (int *) NULL
257
      && ((insn >> 21) & 0x1f) != (insn & 0x1f))
258
    *invalid = 1;
259
  return 0;
260
}
261
 
262
 
263
/* Fake arguments in which the registers must be set to ZERO */
264
 
265
/*ARGSUSED*/
266
static unsigned
267
insert_za(insn, value, errmsg)
268
     unsigned insn;
269
     int value ATTRIBUTE_UNUSED;
270
     const char **errmsg ATTRIBUTE_UNUSED;
271
{
272
  return insn | (31 << 21);
273
}
274
 
275
static int
276
extract_za(insn, invalid)
277
     unsigned insn;
278
     int *invalid;
279
{
280
  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
281
    *invalid = 1;
282
  return 0;
283
}
284
 
285
/*ARGSUSED*/
286
static unsigned
287
insert_zb(insn, value, errmsg)
288
     unsigned insn;
289
     int value ATTRIBUTE_UNUSED;
290
     const char **errmsg ATTRIBUTE_UNUSED;
291
{
292
  return insn | (31 << 16);
293
}
294
 
295
static int
296
extract_zb(insn, invalid)
297
     unsigned insn;
298
     int *invalid;
299
{
300
  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
301
    *invalid = 1;
302
  return 0;
303
}
304
 
305
/*ARGSUSED*/
306
static unsigned
307
insert_zc(insn, value, errmsg)
308
     unsigned insn;
309
     int value ATTRIBUTE_UNUSED;
310
     const char **errmsg ATTRIBUTE_UNUSED;
311
{
312
  return insn | 31;
313
}
314
 
315
static int
316
extract_zc(insn, invalid)
317
     unsigned insn;
318
     int *invalid;
319
{
320
  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
321
    *invalid = 1;
322
  return 0;
323
}
324
 
325
 
326
/* The displacement field of a Branch format insn.  */
327
 
328
static unsigned
329
insert_bdisp(insn, value, errmsg)
330
     unsigned insn;
331
     int value;
332
     const char **errmsg;
333
{
334
  if (errmsg != (const char **)NULL && (value & 3))
335
    *errmsg = _("branch operand unaligned");
336
  return insn | ((value / 4) & 0x1FFFFF);
337
}
338
 
339
/*ARGSUSED*/
340
static int
341
extract_bdisp(insn, invalid)
342
     unsigned insn;
343
     int *invalid ATTRIBUTE_UNUSED;
344
{
345
  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
346
}
347
 
348
 
349
/* The hint field of a JMP/JSR insn.  */
350
 
351
static unsigned
352
insert_jhint(insn, value, errmsg)
353
     unsigned insn;
354
     int value;
355
     const char **errmsg;
356
{
357
  if (errmsg != (const char **)NULL && (value & 3))
358
    *errmsg = _("jump hint unaligned");
359
  return insn | ((value / 4) & 0x3FFF);
360
}
361
 
362
/*ARGSUSED*/
363
static int
364
extract_jhint(insn, invalid)
365
     unsigned insn;
366
     int *invalid ATTRIBUTE_UNUSED;
367
{
368
  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
369
}
370
 
371
/* The hint field of an EV6 HW_JMP/JSR insn.  */
372
 
373
static unsigned
374
insert_ev6hwjhint(insn, value, errmsg)
375
     unsigned insn;
376
     int value;
377
     const char **errmsg;
378
{
379
  if (errmsg != (const char **)NULL && (value & 3))
380
    *errmsg = _("jump hint unaligned");
381
  return insn | ((value / 4) & 0x1FFF);
382
}
383
 
384
/*ARGSUSED*/
385
static int
386
extract_ev6hwjhint(insn, invalid)
387
     unsigned insn;
388
     int *invalid ATTRIBUTE_UNUSED;
389
{
390
  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
391
}
392
 
393
 
394
/* Macros used to form opcodes */
395
 
396
/* The main opcode */
397
#define OP(x)           (((x) & 0x3F) << 26)
398
#define OP_MASK         0xFC000000
399
 
400
/* Branch format instructions */
401
#define BRA_(oo)        OP(oo)
402
#define BRA_MASK        OP_MASK
403
#define BRA(oo)         BRA_(oo), BRA_MASK
404
 
405
/* Floating point format instructions */
406
#define FP_(oo,fff)     (OP(oo) | (((fff) & 0x7FF) << 5))
407
#define FP_MASK         (OP_MASK | 0xFFE0)
408
#define FP(oo,fff)      FP_(oo,fff), FP_MASK
409
 
410
/* Memory format instructions */
411
#define MEM_(oo)        OP(oo)
412
#define MEM_MASK        OP_MASK
413
#define MEM(oo)         MEM_(oo), MEM_MASK
414
 
415
/* Memory/Func Code format instructions */
416
#define MFC_(oo,ffff)   (OP(oo) | ((ffff) & 0xFFFF))
417
#define MFC_MASK        (OP_MASK | 0xFFFF)
418
#define MFC(oo,ffff)    MFC_(oo,ffff), MFC_MASK
419
 
420
/* Memory/Branch format instructions */
421
#define MBR_(oo,h)      (OP(oo) | (((h) & 3) << 14))
422
#define MBR_MASK        (OP_MASK | 0xC000)
423
#define MBR(oo,h)       MBR_(oo,h), MBR_MASK
424
 
425
/* Operate format instructions.  The OPRL variant specifies a
426
   literal second argument. */
427
#define OPR_(oo,ff)     (OP(oo) | (((ff) & 0x7F) << 5))
428
#define OPRL_(oo,ff)    (OPR_((oo),(ff)) | 0x1000)
429
#define OPR_MASK        (OP_MASK | 0x1FE0)
430
#define OPR(oo,ff)      OPR_(oo,ff), OPR_MASK
431
#define OPRL(oo,ff)     OPRL_(oo,ff), OPR_MASK
432
 
433
/* Generic PALcode format instructions */
434
#define PCD_(oo)        OP(oo)
435
#define PCD_MASK        OP_MASK
436
#define PCD(oo)         PCD_(oo), PCD_MASK
437
 
438
/* Specific PALcode instructions */
439
#define SPCD_(oo,ffff)  (OP(oo) | ((ffff) & 0x3FFFFFF))
440
#define SPCD_MASK       0xFFFFFFFF
441
#define SPCD(oo,ffff)   SPCD_(oo,ffff), SPCD_MASK
442
 
443
/* Hardware memory (hw_{ld,st}) instructions */
444
#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
445
#define EV4HWMEM_MASK   (OP_MASK | 0xF000)
446
#define EV4HWMEM(oo,f)  EV4HWMEM_(oo,f), EV4HWMEM_MASK
447
 
448
#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
449
#define EV5HWMEM_MASK   (OP_MASK | 0xF800)
450
#define EV5HWMEM(oo,f)  EV5HWMEM_(oo,f), EV5HWMEM_MASK
451
 
452
#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
453
#define EV6HWMEM_MASK   (OP_MASK | 0xF000)
454
#define EV6HWMEM(oo,f)  EV6HWMEM_(oo,f), EV6HWMEM_MASK
455
 
456
#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
457
#define EV6HWMBR_MASK   (OP_MASK | 0xE000)
458
#define EV6HWMBR(oo,h)  EV6HWMBR_(oo,h), EV6HWMBR_MASK
459
 
460
/* Abbreviations for instruction subsets.  */
461
#define BASE                    AXP_OPCODE_BASE
462
#define EV4                     AXP_OPCODE_EV4
463
#define EV5                     AXP_OPCODE_EV5
464
#define EV6                     AXP_OPCODE_EV6
465
#define BWX                     AXP_OPCODE_BWX
466
#define CIX                     AXP_OPCODE_CIX
467
#define MAX                     AXP_OPCODE_MAX
468
 
469
/* Common combinations of arguments */
470
#define ARG_NONE                { 0 }
471
#define ARG_BRA                 { RA, BDISP }
472
#define ARG_FBRA                { FA, BDISP }
473
#define ARG_FP                  { FA, FB, DFC1 }
474
#define ARG_FPZ1                { ZA, FB, DFC1 }
475
#define ARG_MEM                 { RA, MDISP, PRB }
476
#define ARG_FMEM                { FA, MDISP, PRB }
477
#define ARG_OPR                 { RA, RB, DRC1 }
478
#define ARG_OPRL                { RA, LIT, DRC1 }
479
#define ARG_OPRZ1               { ZA, RB, DRC1 }
480
#define ARG_OPRLZ1              { ZA, LIT, RC }
481
#define ARG_PCD                 { PALFN }
482
#define ARG_EV4HWMEM            { RA, EV4HWDISP, PRB }
483
#define ARG_EV4HWMPR            { RA, RBA, EV4HWINDEX }
484
#define ARG_EV5HWMEM            { RA, EV5HWDISP, PRB }
485
#define ARG_EV6HWMEM            { RA, EV6HWDISP, PRB }
486
 
487
/* The opcode table.
488
 
489
   The format of the opcode table is:
490
 
491
   NAME OPCODE MASK { OPERANDS }
492
 
493
   NAME         is the name of the instruction.
494
 
495
   OPCODE       is the instruction opcode.
496
 
497
   MASK         is the opcode mask; this is used to tell the disassembler
498
                which bits in the actual opcode must match OPCODE.
499
 
500
   OPERANDS     is the list of operands.
501
 
502
   The preceding macros merge the text of the OPCODE and MASK fields.
503
 
504
   The disassembler reads the table in order and prints the first
505
   instruction which matches, so this table is sorted to put more
506
   specific instructions before more general instructions.
507
 
508
   Otherwise, it is sorted by major opcode and minor function code.
509
 
510
   There are three classes of not-really-instructions in this table:
511
 
512
   ALIAS        is another name for another instruction.  Some of
513
                these come from the Architecture Handbook, some
514
                come from the original gas opcode tables.  In all
515
                cases, the functionality of the opcode is unchanged.
516
 
517
   PSEUDO       a stylized code form endorsed by Chapter A.4 of the
518
                Architecture Handbook.
519
 
520
   EXTRA        a stylized code form found in the original gas tables.
521
 
522
   And two annotations:
523
 
524
   EV56 BUT     opcodes that are officially introduced as of the ev56,
525
                but with defined results on previous implementations.
526
 
527
   EV56 UNA     opcodes that were introduced as of the ev56 with
528
                presumably undefined results on previous implementations
529
                that were not assigned to a particular extension.
530
*/
531
 
532
const struct alpha_opcode alpha_opcodes[] = {
533
  { "halt",             SPCD(0x00,0x0000), BASE, ARG_NONE },
534
  { "draina",           SPCD(0x00,0x0002), BASE, ARG_NONE },
535
  { "bpt",              SPCD(0x00,0x0080), BASE, ARG_NONE },
536
  { "callsys",          SPCD(0x00,0x0083), BASE, ARG_NONE },
537
  { "chmk",             SPCD(0x00,0x0083), BASE, ARG_NONE },
538
  { "imb",              SPCD(0x00,0x0086), BASE, ARG_NONE },
539
  { "call_pal",         PCD(0x00), BASE, ARG_PCD },
540
  { "pal",              PCD(0x00), BASE, ARG_PCD },             /* alias */
541
 
542
  { "lda",              MEM(0x08), BASE, ARG_MEM },
543
  { "ldah",             MEM(0x09), BASE, ARG_MEM },
544
  { "ldbu",             MEM(0x0A), BWX, ARG_MEM },
545
  { "unop",             MEM(0x0B), BASE, { ZA } },              /* pseudo */
546
  { "ldq_u",            MEM(0x0B), BASE, ARG_MEM },
547
  { "ldwu",             MEM(0x0C), BWX, ARG_MEM },
548
  { "stw",              MEM(0x0D), BWX, ARG_MEM },
549
  { "stb",              MEM(0x0E), BWX, ARG_MEM },
550
  { "stq_u",            MEM(0x0F), BASE, ARG_MEM },
551
 
552
  { "sextl",            OPR(0x10,0x00), BASE, ARG_OPRZ1 },      /* pseudo */
553
  { "sextl",            OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },    /* pseudo */
554
  { "addl",             OPR(0x10,0x00), BASE, ARG_OPR },
555
  { "addl",             OPRL(0x10,0x00), BASE, ARG_OPRL },
556
  { "s4addl",           OPR(0x10,0x02), BASE, ARG_OPR },
557
  { "s4addl",           OPRL(0x10,0x02), BASE, ARG_OPRL },
558
  { "negl",             OPR(0x10,0x09), BASE, ARG_OPRZ1 },      /* pseudo */
559
  { "negl",             OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },    /* pseudo */
560
  { "subl",             OPR(0x10,0x09), BASE, ARG_OPR },
561
  { "subl",             OPRL(0x10,0x09), BASE, ARG_OPRL },
562
  { "s4subl",           OPR(0x10,0x0B), BASE, ARG_OPR },
563
  { "s4subl",           OPRL(0x10,0x0B), BASE, ARG_OPRL },
564
  { "cmpbge",           OPR(0x10,0x0F), BASE, ARG_OPR },
565
  { "cmpbge",           OPRL(0x10,0x0F), BASE, ARG_OPRL },
566
  { "s8addl",           OPR(0x10,0x12), BASE, ARG_OPR },
567
  { "s8addl",           OPRL(0x10,0x12), BASE, ARG_OPRL },
568
  { "s8subl",           OPR(0x10,0x1B), BASE, ARG_OPR },
569
  { "s8subl",           OPRL(0x10,0x1B), BASE, ARG_OPRL },
570
  { "cmpult",           OPR(0x10,0x1D), BASE, ARG_OPR },
571
  { "cmpult",           OPRL(0x10,0x1D), BASE, ARG_OPRL },
572
  { "addq",             OPR(0x10,0x20), BASE, ARG_OPR },
573
  { "addq",             OPRL(0x10,0x20), BASE, ARG_OPRL },
574
  { "s4addq",           OPR(0x10,0x22), BASE, ARG_OPR },
575
  { "s4addq",           OPRL(0x10,0x22), BASE, ARG_OPRL },
576
  { "negq",             OPR(0x10,0x29), BASE, ARG_OPRZ1 },      /* pseudo */
577
  { "negq",             OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },    /* pseudo */
578
  { "subq",             OPR(0x10,0x29), BASE, ARG_OPR },
579
  { "subq",             OPRL(0x10,0x29), BASE, ARG_OPRL },
580
  { "s4subq",           OPR(0x10,0x2B), BASE, ARG_OPR },
581
  { "s4subq",           OPRL(0x10,0x2B), BASE, ARG_OPRL },
582
  { "cmpeq",            OPR(0x10,0x2D), BASE, ARG_OPR },
583
  { "cmpeq",            OPRL(0x10,0x2D), BASE, ARG_OPRL },
584
  { "s8addq",           OPR(0x10,0x32), BASE, ARG_OPR },
585
  { "s8addq",           OPRL(0x10,0x32), BASE, ARG_OPRL },
586
  { "s8subq",           OPR(0x10,0x3B), BASE, ARG_OPR },
587
  { "s8subq",           OPRL(0x10,0x3B), BASE, ARG_OPRL },
588
  { "cmpule",           OPR(0x10,0x3D), BASE, ARG_OPR },
589
  { "cmpule",           OPRL(0x10,0x3D), BASE, ARG_OPRL },
590
  { "addl/v",           OPR(0x10,0x40), BASE, ARG_OPR },
591
  { "addl/v",           OPRL(0x10,0x40), BASE, ARG_OPRL },
592
  { "negl/v",           OPR(0x10,0x49), BASE, ARG_OPRZ1 },      /* pseudo */
593
  { "negl/v",           OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },    /* pseudo */
594
  { "subl/v",           OPR(0x10,0x49), BASE, ARG_OPR },
595
  { "subl/v",           OPRL(0x10,0x49), BASE, ARG_OPRL },
596
  { "cmplt",            OPR(0x10,0x4D), BASE, ARG_OPR },
597
  { "cmplt",            OPRL(0x10,0x4D), BASE, ARG_OPRL },
598
  { "addq/v",           OPR(0x10,0x60), BASE, ARG_OPR },
599
  { "addq/v",           OPRL(0x10,0x60), BASE, ARG_OPRL },
600
  { "negq/v",           OPR(0x10,0x69), BASE, ARG_OPRZ1 },      /* pseudo */
601
  { "negq/v",           OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },    /* pseudo */
602
  { "subq/v",           OPR(0x10,0x69), BASE, ARG_OPR },
603
  { "subq/v",           OPRL(0x10,0x69), BASE, ARG_OPRL },
604
  { "cmple",            OPR(0x10,0x6D), BASE, ARG_OPR },
605
  { "cmple",            OPRL(0x10,0x6D), BASE, ARG_OPRL },
606
 
607
  { "and",              OPR(0x11,0x00), BASE, ARG_OPR },
608
  { "and",              OPRL(0x11,0x00), BASE, ARG_OPRL },
609
  { "andnot",           OPR(0x11,0x08), BASE, ARG_OPR },        /* alias */
610
  { "andnot",           OPRL(0x11,0x08), BASE, ARG_OPRL },      /* alias */
611
  { "bic",              OPR(0x11,0x08), BASE, ARG_OPR },
612
  { "bic",              OPRL(0x11,0x08), BASE, ARG_OPRL },
613
  { "cmovlbs",          OPR(0x11,0x14), BASE, ARG_OPR },
614
  { "cmovlbs",          OPRL(0x11,0x14), BASE, ARG_OPRL },
615
  { "cmovlbc",          OPR(0x11,0x16), BASE, ARG_OPR },
616
  { "cmovlbc",          OPRL(0x11,0x16), BASE, ARG_OPRL },
617
  { "nop",              OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
618
  { "clr",              OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
619
  { "mov",              OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
620
  { "mov",              OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
621
  { "mov",              OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
622
  { "or",               OPR(0x11,0x20), BASE, ARG_OPR },        /* alias */
623
  { "or",               OPRL(0x11,0x20), BASE, ARG_OPRL },      /* alias */
624
  { "bis",              OPR(0x11,0x20), BASE, ARG_OPR },
625
  { "bis",              OPRL(0x11,0x20), BASE, ARG_OPRL },
626
  { "cmoveq",           OPR(0x11,0x24), BASE, ARG_OPR },
627
  { "cmoveq",           OPRL(0x11,0x24), BASE, ARG_OPRL },
628
  { "cmovne",           OPR(0x11,0x26), BASE, ARG_OPR },
629
  { "cmovne",           OPRL(0x11,0x26), BASE, ARG_OPRL },
630
  { "not",              OPR(0x11,0x28), BASE, ARG_OPRZ1 },      /* pseudo */
631
  { "not",              OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },    /* pseudo */
632
  { "ornot",            OPR(0x11,0x28), BASE, ARG_OPR },
633
  { "ornot",            OPRL(0x11,0x28), BASE, ARG_OPRL },
634
  { "xor",              OPR(0x11,0x40), BASE, ARG_OPR },
635
  { "xor",              OPRL(0x11,0x40), BASE, ARG_OPRL },
636
  { "cmovlt",           OPR(0x11,0x44), BASE, ARG_OPR },
637
  { "cmovlt",           OPRL(0x11,0x44), BASE, ARG_OPRL },
638
  { "cmovge",           OPR(0x11,0x46), BASE, ARG_OPR },
639
  { "cmovge",           OPRL(0x11,0x46), BASE, ARG_OPRL },
640
  { "eqv",              OPR(0x11,0x48), BASE, ARG_OPR },
641
  { "eqv",              OPRL(0x11,0x48), BASE, ARG_OPRL },
642
  { "xornot",           OPR(0x11,0x48), BASE, ARG_OPR },        /* alias */
643
  { "xornot",           OPRL(0x11,0x48), BASE, ARG_OPRL },      /* alias */
644
  { "amask",            OPR(0x11,0x61), BASE, ARG_OPRZ1 },      /* ev56 but */
645
  { "amask",            OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },    /* ev56 but */
646
  { "cmovle",           OPR(0x11,0x64), BASE, ARG_OPR },
647
  { "cmovle",           OPRL(0x11,0x64), BASE, ARG_OPRL },
648
  { "cmovgt",           OPR(0x11,0x66), BASE, ARG_OPR },
649
  { "cmovgt",           OPRL(0x11,0x66), BASE, ARG_OPRL },
650
  { "implver",          OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
651
                        0xFFFFFFE0, BASE, { RC } },             /* ev56 but */
652
 
653
  { "mskbl",            OPR(0x12,0x02), BASE, ARG_OPR },
654
  { "mskbl",            OPRL(0x12,0x02), BASE, ARG_OPRL },
655
  { "extbl",            OPR(0x12,0x06), BASE, ARG_OPR },
656
  { "extbl",            OPRL(0x12,0x06), BASE, ARG_OPRL },
657
  { "insbl",            OPR(0x12,0x0B), BASE, ARG_OPR },
658
  { "insbl",            OPRL(0x12,0x0B), BASE, ARG_OPRL },
659
  { "mskwl",            OPR(0x12,0x12), BASE, ARG_OPR },
660
  { "mskwl",            OPRL(0x12,0x12), BASE, ARG_OPRL },
661
  { "extwl",            OPR(0x12,0x16), BASE, ARG_OPR },
662
  { "extwl",            OPRL(0x12,0x16), BASE, ARG_OPRL },
663
  { "inswl",            OPR(0x12,0x1B), BASE, ARG_OPR },
664
  { "inswl",            OPRL(0x12,0x1B), BASE, ARG_OPRL },
665
  { "mskll",            OPR(0x12,0x22), BASE, ARG_OPR },
666
  { "mskll",            OPRL(0x12,0x22), BASE, ARG_OPRL },
667
  { "extll",            OPR(0x12,0x26), BASE, ARG_OPR },
668
  { "extll",            OPRL(0x12,0x26), BASE, ARG_OPRL },
669
  { "insll",            OPR(0x12,0x2B), BASE, ARG_OPR },
670
  { "insll",            OPRL(0x12,0x2B), BASE, ARG_OPRL },
671
  { "zap",              OPR(0x12,0x30), BASE, ARG_OPR },
672
  { "zap",              OPRL(0x12,0x30), BASE, ARG_OPRL },
673
  { "zapnot",           OPR(0x12,0x31), BASE, ARG_OPR },
674
  { "zapnot",           OPRL(0x12,0x31), BASE, ARG_OPRL },
675
  { "mskql",            OPR(0x12,0x32), BASE, ARG_OPR },
676
  { "mskql",            OPRL(0x12,0x32), BASE, ARG_OPRL },
677
  { "srl",              OPR(0x12,0x34), BASE, ARG_OPR },
678
  { "srl",              OPRL(0x12,0x34), BASE, ARG_OPRL },
679
  { "extql",            OPR(0x12,0x36), BASE, ARG_OPR },
680
  { "extql",            OPRL(0x12,0x36), BASE, ARG_OPRL },
681
  { "sll",              OPR(0x12,0x39), BASE, ARG_OPR },
682
  { "sll",              OPRL(0x12,0x39), BASE, ARG_OPRL },
683
  { "insql",            OPR(0x12,0x3B), BASE, ARG_OPR },
684
  { "insql",            OPRL(0x12,0x3B), BASE, ARG_OPRL },
685
  { "sra",              OPR(0x12,0x3C), BASE, ARG_OPR },
686
  { "sra",              OPRL(0x12,0x3C), BASE, ARG_OPRL },
687
  { "mskwh",            OPR(0x12,0x52), BASE, ARG_OPR },
688
  { "mskwh",            OPRL(0x12,0x52), BASE, ARG_OPRL },
689
  { "inswh",            OPR(0x12,0x57), BASE, ARG_OPR },
690
  { "inswh",            OPRL(0x12,0x57), BASE, ARG_OPRL },
691
  { "extwh",            OPR(0x12,0x5A), BASE, ARG_OPR },
692
  { "extwh",            OPRL(0x12,0x5A), BASE, ARG_OPRL },
693
  { "msklh",            OPR(0x12,0x62), BASE, ARG_OPR },
694
  { "msklh",            OPRL(0x12,0x62), BASE, ARG_OPRL },
695
  { "inslh",            OPR(0x12,0x67), BASE, ARG_OPR },
696
  { "inslh",            OPRL(0x12,0x67), BASE, ARG_OPRL },
697
  { "extlh",            OPR(0x12,0x6A), BASE, ARG_OPR },
698
  { "extlh",            OPRL(0x12,0x6A), BASE, ARG_OPRL },
699
  { "mskqh",            OPR(0x12,0x72), BASE, ARG_OPR },
700
  { "mskqh",            OPRL(0x12,0x72), BASE, ARG_OPRL },
701
  { "insqh",            OPR(0x12,0x77), BASE, ARG_OPR },
702
  { "insqh",            OPRL(0x12,0x77), BASE, ARG_OPRL },
703
  { "extqh",            OPR(0x12,0x7A), BASE, ARG_OPR },
704
  { "extqh",            OPRL(0x12,0x7A), BASE, ARG_OPRL },
705
 
706
  { "mull",             OPR(0x13,0x00), BASE, ARG_OPR },
707
  { "mull",             OPRL(0x13,0x00), BASE, ARG_OPRL },
708
  { "mulq",             OPR(0x13,0x20), BASE, ARG_OPR },
709
  { "mulq",             OPRL(0x13,0x20), BASE, ARG_OPRL },
710
  { "umulh",            OPR(0x13,0x30), BASE, ARG_OPR },
711
  { "umulh",            OPRL(0x13,0x30), BASE, ARG_OPRL },
712
  { "mull/v",           OPR(0x13,0x40), BASE, ARG_OPR },
713
  { "mull/v",           OPRL(0x13,0x40), BASE, ARG_OPRL },
714
  { "mulq/v",           OPR(0x13,0x60), BASE, ARG_OPR },
715
  { "mulq/v",           OPRL(0x13,0x60), BASE, ARG_OPRL },
716
 
717
  { "itofs",            FP(0x14,0x004), CIX, { RA, ZB, FC } },
718
  { "sqrtf/c",          FP(0x14,0x00A), CIX, ARG_FPZ1 },
719
  { "sqrts/c",          FP(0x14,0x00B), CIX, ARG_FPZ1 },
720
  { "itoff",            FP(0x14,0x014), CIX, { RA, ZB, FC } },
721
  { "itoft",            FP(0x14,0x024), CIX, { RA, ZB, FC } },
722
  { "sqrtg/c",          FP(0x14,0x02A), CIX, ARG_FPZ1 },
723
  { "sqrtt/c",          FP(0x14,0x02B), CIX, ARG_FPZ1 },
724
  { "sqrts/m",          FP(0x14,0x04B), CIX, ARG_FPZ1 },
725
  { "sqrtt/m",          FP(0x14,0x06B), CIX, ARG_FPZ1 },
726
  { "sqrtf",            FP(0x14,0x08A), CIX, ARG_FPZ1 },
727
  { "sqrts",            FP(0x14,0x08B), CIX, ARG_FPZ1 },
728
  { "sqrtg",            FP(0x14,0x0AA), CIX, ARG_FPZ1 },
729
  { "sqrtt",            FP(0x14,0x0AB), CIX, ARG_FPZ1 },
730
  { "sqrts/d",          FP(0x14,0x0CB), CIX, ARG_FPZ1 },
731
  { "sqrtt/d",          FP(0x14,0x0EB), CIX, ARG_FPZ1 },
732
  { "sqrtf/uc",         FP(0x14,0x10A), CIX, ARG_FPZ1 },
733
  { "sqrts/uc",         FP(0x14,0x10B), CIX, ARG_FPZ1 },
734
  { "sqrtg/uc",         FP(0x14,0x12A), CIX, ARG_FPZ1 },
735
  { "sqrtt/uc",         FP(0x14,0x12B), CIX, ARG_FPZ1 },
736
  { "sqrts/um",         FP(0x14,0x14B), CIX, ARG_FPZ1 },
737
  { "sqrtt/um",         FP(0x14,0x16B), CIX, ARG_FPZ1 },
738
  { "sqrtf/u",          FP(0x14,0x18A), CIX, ARG_FPZ1 },
739
  { "sqrts/u",          FP(0x14,0x18B), CIX, ARG_FPZ1 },
740
  { "sqrtg/u",          FP(0x14,0x1AA), CIX, ARG_FPZ1 },
741
  { "sqrtt/u",          FP(0x14,0x1AB), CIX, ARG_FPZ1 },
742
  { "sqrts/ud",         FP(0x14,0x1CB), CIX, ARG_FPZ1 },
743
  { "sqrtt/ud",         FP(0x14,0x1EB), CIX, ARG_FPZ1 },
744
  { "sqrtf/sc",         FP(0x14,0x40A), CIX, ARG_FPZ1 },
745
  { "sqrtg/sc",         FP(0x14,0x42A), CIX, ARG_FPZ1 },
746
  { "sqrtf/s",          FP(0x14,0x48A), CIX, ARG_FPZ1 },
747
  { "sqrtg/s",          FP(0x14,0x4AA), CIX, ARG_FPZ1 },
748
  { "sqrtf/suc",        FP(0x14,0x50A), CIX, ARG_FPZ1 },
749
  { "sqrts/suc",        FP(0x14,0x50B), CIX, ARG_FPZ1 },
750
  { "sqrtg/suc",        FP(0x14,0x52A), CIX, ARG_FPZ1 },
751
  { "sqrtt/suc",        FP(0x14,0x52B), CIX, ARG_FPZ1 },
752
  { "sqrts/sum",        FP(0x14,0x54B), CIX, ARG_FPZ1 },
753
  { "sqrtt/sum",        FP(0x14,0x56B), CIX, ARG_FPZ1 },
754
  { "sqrtf/su",         FP(0x14,0x58A), CIX, ARG_FPZ1 },
755
  { "sqrts/su",         FP(0x14,0x58B), CIX, ARG_FPZ1 },
756
  { "sqrtg/su",         FP(0x14,0x5AA), CIX, ARG_FPZ1 },
757
  { "sqrtt/su",         FP(0x14,0x5AB), CIX, ARG_FPZ1 },
758
  { "sqrts/sud",        FP(0x14,0x5CB), CIX, ARG_FPZ1 },
759
  { "sqrtt/sud",        FP(0x14,0x5EB), CIX, ARG_FPZ1 },
760
  { "sqrts/suic",       FP(0x14,0x70B), CIX, ARG_FPZ1 },
761
  { "sqrtt/suic",       FP(0x14,0x72B), CIX, ARG_FPZ1 },
762
  { "sqrts/suim",       FP(0x14,0x74B), CIX, ARG_FPZ1 },
763
  { "sqrtt/suim",       FP(0x14,0x76B), CIX, ARG_FPZ1 },
764
  { "sqrts/sui",        FP(0x14,0x78B), CIX, ARG_FPZ1 },
765
  { "sqrtt/sui",        FP(0x14,0x7AB), CIX, ARG_FPZ1 },
766
  { "sqrts/suid",       FP(0x14,0x7CB), CIX, ARG_FPZ1 },
767
  { "sqrtt/suid",       FP(0x14,0x7EB), CIX, ARG_FPZ1 },
768
 
769
  { "addf/c",           FP(0x15,0x000), BASE, ARG_FP },
770
  { "subf/c",           FP(0x15,0x001), BASE, ARG_FP },
771
  { "mulf/c",           FP(0x15,0x002), BASE, ARG_FP },
772
  { "divf/c",           FP(0x15,0x003), BASE, ARG_FP },
773
  { "cvtdg/c",          FP(0x15,0x01E), BASE, ARG_FPZ1 },
774
  { "addg/c",           FP(0x15,0x020), BASE, ARG_FP },
775
  { "subg/c",           FP(0x15,0x021), BASE, ARG_FP },
776
  { "mulg/c",           FP(0x15,0x022), BASE, ARG_FP },
777
  { "divg/c",           FP(0x15,0x023), BASE, ARG_FP },
778
  { "cvtgf/c",          FP(0x15,0x02C), BASE, ARG_FPZ1 },
779
  { "cvtgd/c",          FP(0x15,0x02D), BASE, ARG_FPZ1 },
780
  { "cvtgq/c",          FP(0x15,0x02F), BASE, ARG_FPZ1 },
781
  { "cvtqf/c",          FP(0x15,0x03C), BASE, ARG_FPZ1 },
782
  { "cvtqg/c",          FP(0x15,0x03E), BASE, ARG_FPZ1 },
783
  { "addf",             FP(0x15,0x080), BASE, ARG_FP },
784
  { "negf",             FP(0x15,0x081), BASE, ARG_FPZ1 },       /* pseudo */
785
  { "subf",             FP(0x15,0x081), BASE, ARG_FP },
786
  { "mulf",             FP(0x15,0x082), BASE, ARG_FP },
787
  { "divf",             FP(0x15,0x083), BASE, ARG_FP },
788
  { "cvtdg",            FP(0x15,0x09E), BASE, ARG_FPZ1 },
789
  { "addg",             FP(0x15,0x0A0), BASE, ARG_FP },
790
  { "negg",             FP(0x15,0x0A1), BASE, ARG_FPZ1 },       /* pseudo */
791
  { "subg",             FP(0x15,0x0A1), BASE, ARG_FP },
792
  { "mulg",             FP(0x15,0x0A2), BASE, ARG_FP },
793
  { "divg",             FP(0x15,0x0A3), BASE, ARG_FP },
794
  { "cmpgeq",           FP(0x15,0x0A5), BASE, ARG_FP },
795
  { "cmpglt",           FP(0x15,0x0A6), BASE, ARG_FP },
796
  { "cmpgle",           FP(0x15,0x0A7), BASE, ARG_FP },
797
  { "cvtgf",            FP(0x15,0x0AC), BASE, ARG_FPZ1 },
798
  { "cvtgd",            FP(0x15,0x0AD), BASE, ARG_FPZ1 },
799
  { "cvtgq",            FP(0x15,0x0AF), BASE, ARG_FPZ1 },
800
  { "cvtqf",            FP(0x15,0x0BC), BASE, ARG_FPZ1 },
801
  { "cvtqg",            FP(0x15,0x0BE), BASE, ARG_FPZ1 },
802
  { "addf/uc",          FP(0x15,0x100), BASE, ARG_FP },
803
  { "subf/uc",          FP(0x15,0x101), BASE, ARG_FP },
804
  { "mulf/uc",          FP(0x15,0x102), BASE, ARG_FP },
805
  { "divf/uc",          FP(0x15,0x103), BASE, ARG_FP },
806
  { "cvtdg/uc",         FP(0x15,0x11E), BASE, ARG_FPZ1 },
807
  { "addg/uc",          FP(0x15,0x120), BASE, ARG_FP },
808
  { "subg/uc",          FP(0x15,0x121), BASE, ARG_FP },
809
  { "mulg/uc",          FP(0x15,0x122), BASE, ARG_FP },
810
  { "divg/uc",          FP(0x15,0x123), BASE, ARG_FP },
811
  { "cvtgf/uc",         FP(0x15,0x12C), BASE, ARG_FPZ1 },
812
  { "cvtgd/uc",         FP(0x15,0x12D), BASE, ARG_FPZ1 },
813
  { "cvtgq/vc",         FP(0x15,0x12F), BASE, ARG_FPZ1 },
814
  { "addf/u",           FP(0x15,0x180), BASE, ARG_FP },
815
  { "subf/u",           FP(0x15,0x181), BASE, ARG_FP },
816
  { "mulf/u",           FP(0x15,0x182), BASE, ARG_FP },
817
  { "divf/u",           FP(0x15,0x183), BASE, ARG_FP },
818
  { "cvtdg/u",          FP(0x15,0x19E), BASE, ARG_FPZ1 },
819
  { "addg/u",           FP(0x15,0x1A0), BASE, ARG_FP },
820
  { "subg/u",           FP(0x15,0x1A1), BASE, ARG_FP },
821
  { "mulg/u",           FP(0x15,0x1A2), BASE, ARG_FP },
822
  { "divg/u",           FP(0x15,0x1A3), BASE, ARG_FP },
823
  { "cvtgf/u",          FP(0x15,0x1AC), BASE, ARG_FPZ1 },
824
  { "cvtgd/u",          FP(0x15,0x1AD), BASE, ARG_FPZ1 },
825
  { "cvtgq/v",          FP(0x15,0x1AF), BASE, ARG_FPZ1 },
826
  { "addf/sc",          FP(0x15,0x400), BASE, ARG_FP },
827
  { "subf/sc",          FP(0x15,0x401), BASE, ARG_FP },
828
  { "mulf/sc",          FP(0x15,0x402), BASE, ARG_FP },
829
  { "divf/sc",          FP(0x15,0x403), BASE, ARG_FP },
830
  { "cvtdg/sc",         FP(0x15,0x41E), BASE, ARG_FPZ1 },
831
  { "addg/sc",          FP(0x15,0x420), BASE, ARG_FP },
832
  { "subg/sc",          FP(0x15,0x421), BASE, ARG_FP },
833
  { "mulg/sc",          FP(0x15,0x422), BASE, ARG_FP },
834
  { "divg/sc",          FP(0x15,0x423), BASE, ARG_FP },
835
  { "cvtgf/sc",         FP(0x15,0x42C), BASE, ARG_FPZ1 },
836
  { "cvtgd/sc",         FP(0x15,0x42D), BASE, ARG_FPZ1 },
837
  { "cvtgq/sc",         FP(0x15,0x42F), BASE, ARG_FPZ1 },
838
  { "addf/s",           FP(0x15,0x480), BASE, ARG_FP },
839
  { "negf/s",           FP(0x15,0x481), BASE, ARG_FPZ1 },       /* pseudo */
840
  { "subf/s",           FP(0x15,0x481), BASE, ARG_FP },
841
  { "mulf/s",           FP(0x15,0x482), BASE, ARG_FP },
842
  { "divf/s",           FP(0x15,0x483), BASE, ARG_FP },
843
  { "cvtdg/s",          FP(0x15,0x49E), BASE, ARG_FPZ1 },
844
  { "addg/s",           FP(0x15,0x4A0), BASE, ARG_FP },
845
  { "negg/s",           FP(0x15,0x4A1), BASE, ARG_FPZ1 },       /* pseudo */
846
  { "subg/s",           FP(0x15,0x4A1), BASE, ARG_FP },
847
  { "mulg/s",           FP(0x15,0x4A2), BASE, ARG_FP },
848
  { "divg/s",           FP(0x15,0x4A3), BASE, ARG_FP },
849
  { "cmpgeq/s",         FP(0x15,0x4A5), BASE, ARG_FP },
850
  { "cmpglt/s",         FP(0x15,0x4A6), BASE, ARG_FP },
851
  { "cmpgle/s",         FP(0x15,0x4A7), BASE, ARG_FP },
852
  { "cvtgf/s",          FP(0x15,0x4AC), BASE, ARG_FPZ1 },
853
  { "cvtgd/s",          FP(0x15,0x4AD), BASE, ARG_FPZ1 },
854
  { "cvtgq/s",          FP(0x15,0x4AF), BASE, ARG_FPZ1 },
855
  { "addf/suc",         FP(0x15,0x500), BASE, ARG_FP },
856
  { "subf/suc",         FP(0x15,0x501), BASE, ARG_FP },
857
  { "mulf/suc",         FP(0x15,0x502), BASE, ARG_FP },
858
  { "divf/suc",         FP(0x15,0x503), BASE, ARG_FP },
859
  { "cvtdg/suc",        FP(0x15,0x51E), BASE, ARG_FPZ1 },
860
  { "addg/suc",         FP(0x15,0x520), BASE, ARG_FP },
861
  { "subg/suc",         FP(0x15,0x521), BASE, ARG_FP },
862
  { "mulg/suc",         FP(0x15,0x522), BASE, ARG_FP },
863
  { "divg/suc",         FP(0x15,0x523), BASE, ARG_FP },
864
  { "cvtgf/suc",        FP(0x15,0x52C), BASE, ARG_FPZ1 },
865
  { "cvtgd/suc",        FP(0x15,0x52D), BASE, ARG_FPZ1 },
866
  { "cvtgq/svc",        FP(0x15,0x52F), BASE, ARG_FPZ1 },
867
  { "addf/su",          FP(0x15,0x580), BASE, ARG_FP },
868
  { "subf/su",          FP(0x15,0x581), BASE, ARG_FP },
869
  { "mulf/su",          FP(0x15,0x582), BASE, ARG_FP },
870
  { "divf/su",          FP(0x15,0x583), BASE, ARG_FP },
871
  { "cvtdg/su",         FP(0x15,0x59E), BASE, ARG_FPZ1 },
872
  { "addg/su",          FP(0x15,0x5A0), BASE, ARG_FP },
873
  { "subg/su",          FP(0x15,0x5A1), BASE, ARG_FP },
874
  { "mulg/su",          FP(0x15,0x5A2), BASE, ARG_FP },
875
  { "divg/su",          FP(0x15,0x5A3), BASE, ARG_FP },
876
  { "cvtgf/su",         FP(0x15,0x5AC), BASE, ARG_FPZ1 },
877
  { "cvtgd/su",         FP(0x15,0x5AD), BASE, ARG_FPZ1 },
878
  { "cvtgq/sv",         FP(0x15,0x5AF), BASE, ARG_FPZ1 },
879
 
880
  { "adds/c",           FP(0x16,0x000), BASE, ARG_FP },
881
  { "subs/c",           FP(0x16,0x001), BASE, ARG_FP },
882
  { "muls/c",           FP(0x16,0x002), BASE, ARG_FP },
883
  { "divs/c",           FP(0x16,0x003), BASE, ARG_FP },
884
  { "addt/c",           FP(0x16,0x020), BASE, ARG_FP },
885
  { "subt/c",           FP(0x16,0x021), BASE, ARG_FP },
886
  { "mult/c",           FP(0x16,0x022), BASE, ARG_FP },
887
  { "divt/c",           FP(0x16,0x023), BASE, ARG_FP },
888
  { "cvtts/c",          FP(0x16,0x02C), BASE, ARG_FPZ1 },
889
  { "cvttq/c",          FP(0x16,0x02F), BASE, ARG_FPZ1 },
890
  { "cvtqs/c",          FP(0x16,0x03C), BASE, ARG_FPZ1 },
891
  { "cvtqt/c",          FP(0x16,0x03E), BASE, ARG_FPZ1 },
892
  { "adds/m",           FP(0x16,0x040), BASE, ARG_FP },
893
  { "subs/m",           FP(0x16,0x041), BASE, ARG_FP },
894
  { "muls/m",           FP(0x16,0x042), BASE, ARG_FP },
895
  { "divs/m",           FP(0x16,0x043), BASE, ARG_FP },
896
  { "addt/m",           FP(0x16,0x060), BASE, ARG_FP },
897
  { "subt/m",           FP(0x16,0x061), BASE, ARG_FP },
898
  { "mult/m",           FP(0x16,0x062), BASE, ARG_FP },
899
  { "divt/m",           FP(0x16,0x063), BASE, ARG_FP },
900
  { "cvtts/m",          FP(0x16,0x06C), BASE, ARG_FPZ1 },
901
  { "cvttq/m",          FP(0x16,0x06F), BASE, ARG_FPZ1 },
902
  { "cvtqs/m",          FP(0x16,0x07C), BASE, ARG_FPZ1 },
903
  { "cvtqt/m",          FP(0x16,0x07E), BASE, ARG_FPZ1 },
904
  { "adds",             FP(0x16,0x080), BASE, ARG_FP },
905
  { "negs",             FP(0x16,0x081), BASE, ARG_FPZ1 },       /* pseudo */
906
  { "subs",             FP(0x16,0x081), BASE, ARG_FP },
907
  { "muls",             FP(0x16,0x082), BASE, ARG_FP },
908
  { "divs",             FP(0x16,0x083), BASE, ARG_FP },
909
  { "addt",             FP(0x16,0x0A0), BASE, ARG_FP },
910
  { "negt",             FP(0x16,0x0A1), BASE, ARG_FPZ1 },       /* pseudo */
911
  { "subt",             FP(0x16,0x0A1), BASE, ARG_FP },
912
  { "mult",             FP(0x16,0x0A2), BASE, ARG_FP },
913
  { "divt",             FP(0x16,0x0A3), BASE, ARG_FP },
914
  { "cmptun",           FP(0x16,0x0A4), BASE, ARG_FP },
915
  { "cmpteq",           FP(0x16,0x0A5), BASE, ARG_FP },
916
  { "cmptlt",           FP(0x16,0x0A6), BASE, ARG_FP },
917
  { "cmptle",           FP(0x16,0x0A7), BASE, ARG_FP },
918
  { "cvtts",            FP(0x16,0x0AC), BASE, ARG_FPZ1 },
919
  { "cvttq",            FP(0x16,0x0AF), BASE, ARG_FPZ1 },
920
  { "cvtqs",            FP(0x16,0x0BC), BASE, ARG_FPZ1 },
921
  { "cvtqt",            FP(0x16,0x0BE), BASE, ARG_FPZ1 },
922
  { "adds/d",           FP(0x16,0x0C0), BASE, ARG_FP },
923
  { "subs/d",           FP(0x16,0x0C1), BASE, ARG_FP },
924
  { "muls/d",           FP(0x16,0x0C2), BASE, ARG_FP },
925
  { "divs/d",           FP(0x16,0x0C3), BASE, ARG_FP },
926
  { "addt/d",           FP(0x16,0x0E0), BASE, ARG_FP },
927
  { "subt/d",           FP(0x16,0x0E1), BASE, ARG_FP },
928
  { "mult/d",           FP(0x16,0x0E2), BASE, ARG_FP },
929
  { "divt/d",           FP(0x16,0x0E3), BASE, ARG_FP },
930
  { "cvtts/d",          FP(0x16,0x0EC), BASE, ARG_FPZ1 },
931
  { "cvttq/d",          FP(0x16,0x0EF), BASE, ARG_FPZ1 },
932
  { "cvtqs/d",          FP(0x16,0x0FC), BASE, ARG_FPZ1 },
933
  { "cvtqt/d",          FP(0x16,0x0FE), BASE, ARG_FPZ1 },
934
  { "adds/uc",          FP(0x16,0x100), BASE, ARG_FP },
935
  { "subs/uc",          FP(0x16,0x101), BASE, ARG_FP },
936
  { "muls/uc",          FP(0x16,0x102), BASE, ARG_FP },
937
  { "divs/uc",          FP(0x16,0x103), BASE, ARG_FP },
938
  { "addt/uc",          FP(0x16,0x120), BASE, ARG_FP },
939
  { "subt/uc",          FP(0x16,0x121), BASE, ARG_FP },
940
  { "mult/uc",          FP(0x16,0x122), BASE, ARG_FP },
941
  { "divt/uc",          FP(0x16,0x123), BASE, ARG_FP },
942
  { "cvtts/uc",         FP(0x16,0x12C), BASE, ARG_FPZ1 },
943
  { "cvttq/vc",         FP(0x16,0x12F), BASE, ARG_FPZ1 },
944
  { "adds/um",          FP(0x16,0x140), BASE, ARG_FP },
945
  { "subs/um",          FP(0x16,0x141), BASE, ARG_FP },
946
  { "muls/um",          FP(0x16,0x142), BASE, ARG_FP },
947
  { "divs/um",          FP(0x16,0x143), BASE, ARG_FP },
948
  { "addt/um",          FP(0x16,0x160), BASE, ARG_FP },
949
  { "subt/um",          FP(0x16,0x161), BASE, ARG_FP },
950
  { "mult/um",          FP(0x16,0x162), BASE, ARG_FP },
951
  { "divt/um",          FP(0x16,0x163), BASE, ARG_FP },
952
  { "cvtts/um",         FP(0x16,0x16C), BASE, ARG_FPZ1 },
953
  { "cvttq/vm",         FP(0x16,0x16F), BASE, ARG_FPZ1 },
954
  { "adds/u",           FP(0x16,0x180), BASE, ARG_FP },
955
  { "subs/u",           FP(0x16,0x181), BASE, ARG_FP },
956
  { "muls/u",           FP(0x16,0x182), BASE, ARG_FP },
957
  { "divs/u",           FP(0x16,0x183), BASE, ARG_FP },
958
  { "addt/u",           FP(0x16,0x1A0), BASE, ARG_FP },
959
  { "subt/u",           FP(0x16,0x1A1), BASE, ARG_FP },
960
  { "mult/u",           FP(0x16,0x1A2), BASE, ARG_FP },
961
  { "divt/u",           FP(0x16,0x1A3), BASE, ARG_FP },
962
  { "cvtts/u",          FP(0x16,0x1AC), BASE, ARG_FPZ1 },
963
  { "cvttq/v",          FP(0x16,0x1AF), BASE, ARG_FPZ1 },
964
  { "adds/ud",          FP(0x16,0x1C0), BASE, ARG_FP },
965
  { "subs/ud",          FP(0x16,0x1C1), BASE, ARG_FP },
966
  { "muls/ud",          FP(0x16,0x1C2), BASE, ARG_FP },
967
  { "divs/ud",          FP(0x16,0x1C3), BASE, ARG_FP },
968
  { "addt/ud",          FP(0x16,0x1E0), BASE, ARG_FP },
969
  { "subt/ud",          FP(0x16,0x1E1), BASE, ARG_FP },
970
  { "mult/ud",          FP(0x16,0x1E2), BASE, ARG_FP },
971
  { "divt/ud",          FP(0x16,0x1E3), BASE, ARG_FP },
972
  { "cvtts/ud",         FP(0x16,0x1EC), BASE, ARG_FPZ1 },
973
  { "cvttq/vd",         FP(0x16,0x1EF), BASE, ARG_FPZ1 },
974
  { "cvtst",            FP(0x16,0x2AC), BASE, ARG_FPZ1 },
975
  { "adds/suc",         FP(0x16,0x500), BASE, ARG_FP },
976
  { "subs/suc",         FP(0x16,0x501), BASE, ARG_FP },
977
  { "muls/suc",         FP(0x16,0x502), BASE, ARG_FP },
978
  { "divs/suc",         FP(0x16,0x503), BASE, ARG_FP },
979
  { "addt/suc",         FP(0x16,0x520), BASE, ARG_FP },
980
  { "subt/suc",         FP(0x16,0x521), BASE, ARG_FP },
981
  { "mult/suc",         FP(0x16,0x522), BASE, ARG_FP },
982
  { "divt/suc",         FP(0x16,0x523), BASE, ARG_FP },
983
  { "cvtts/suc",        FP(0x16,0x52C), BASE, ARG_FPZ1 },
984
  { "cvttq/svc",        FP(0x16,0x52F), BASE, ARG_FPZ1 },
985
  { "adds/sum",         FP(0x16,0x540), BASE, ARG_FP },
986
  { "subs/sum",         FP(0x16,0x541), BASE, ARG_FP },
987
  { "muls/sum",         FP(0x16,0x542), BASE, ARG_FP },
988
  { "divs/sum",         FP(0x16,0x543), BASE, ARG_FP },
989
  { "addt/sum",         FP(0x16,0x560), BASE, ARG_FP },
990
  { "subt/sum",         FP(0x16,0x561), BASE, ARG_FP },
991
  { "mult/sum",         FP(0x16,0x562), BASE, ARG_FP },
992
  { "divt/sum",         FP(0x16,0x563), BASE, ARG_FP },
993
  { "cvtts/sum",        FP(0x16,0x56C), BASE, ARG_FPZ1 },
994
  { "cvttq/svm",        FP(0x16,0x56F), BASE, ARG_FPZ1 },
995
  { "adds/su",          FP(0x16,0x580), BASE, ARG_FP },
996
  { "negs/su",          FP(0x16,0x581), BASE, ARG_FPZ1 },       /* pseudo */
997
  { "subs/su",          FP(0x16,0x581), BASE, ARG_FP },
998
  { "muls/su",          FP(0x16,0x582), BASE, ARG_FP },
999
  { "divs/su",          FP(0x16,0x583), BASE, ARG_FP },
1000
  { "addt/su",          FP(0x16,0x5A0), BASE, ARG_FP },
1001
  { "negt/su",          FP(0x16,0x5A1), BASE, ARG_FPZ1 },       /* pseudo */
1002
  { "subt/su",          FP(0x16,0x5A1), BASE, ARG_FP },
1003
  { "mult/su",          FP(0x16,0x5A2), BASE, ARG_FP },
1004
  { "divt/su",          FP(0x16,0x5A3), BASE, ARG_FP },
1005
  { "cmptun/su",        FP(0x16,0x5A4), BASE, ARG_FP },
1006
  { "cmpteq/su",        FP(0x16,0x5A5), BASE, ARG_FP },
1007
  { "cmptlt/su",        FP(0x16,0x5A6), BASE, ARG_FP },
1008
  { "cmptle/su",        FP(0x16,0x5A7), BASE, ARG_FP },
1009
  { "cvtts/su",         FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1010
  { "cvttq/sv",         FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1011
  { "adds/sud",         FP(0x16,0x5C0), BASE, ARG_FP },
1012
  { "subs/sud",         FP(0x16,0x5C1), BASE, ARG_FP },
1013
  { "muls/sud",         FP(0x16,0x5C2), BASE, ARG_FP },
1014
  { "divs/sud",         FP(0x16,0x5C3), BASE, ARG_FP },
1015
  { "addt/sud",         FP(0x16,0x5E0), BASE, ARG_FP },
1016
  { "subt/sud",         FP(0x16,0x5E1), BASE, ARG_FP },
1017
  { "mult/sud",         FP(0x16,0x5E2), BASE, ARG_FP },
1018
  { "divt/sud",         FP(0x16,0x5E3), BASE, ARG_FP },
1019
  { "cvtts/sud",        FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1020
  { "cvttq/svd",        FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1021
  { "cvtst/s",          FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1022
  { "adds/suic",        FP(0x16,0x700), BASE, ARG_FP },
1023
  { "subs/suic",        FP(0x16,0x701), BASE, ARG_FP },
1024
  { "muls/suic",        FP(0x16,0x702), BASE, ARG_FP },
1025
  { "divs/suic",        FP(0x16,0x703), BASE, ARG_FP },
1026
  { "addt/suic",        FP(0x16,0x720), BASE, ARG_FP },
1027
  { "subt/suic",        FP(0x16,0x721), BASE, ARG_FP },
1028
  { "mult/suic",        FP(0x16,0x722), BASE, ARG_FP },
1029
  { "divt/suic",        FP(0x16,0x723), BASE, ARG_FP },
1030
  { "cvtts/suic",       FP(0x16,0x72C), BASE, ARG_FPZ1 },
1031
  { "cvttq/svic",       FP(0x16,0x72F), BASE, ARG_FPZ1 },
1032
  { "cvtqs/suic",       FP(0x16,0x73C), BASE, ARG_FPZ1 },
1033
  { "cvtqt/suic",       FP(0x16,0x73E), BASE, ARG_FPZ1 },
1034
  { "adds/suim",        FP(0x16,0x740), BASE, ARG_FP },
1035
  { "subs/suim",        FP(0x16,0x741), BASE, ARG_FP },
1036
  { "muls/suim",        FP(0x16,0x742), BASE, ARG_FP },
1037
  { "divs/suim",        FP(0x16,0x743), BASE, ARG_FP },
1038
  { "addt/suim",        FP(0x16,0x760), BASE, ARG_FP },
1039
  { "subt/suim",        FP(0x16,0x761), BASE, ARG_FP },
1040
  { "mult/suim",        FP(0x16,0x762), BASE, ARG_FP },
1041
  { "divt/suim",        FP(0x16,0x763), BASE, ARG_FP },
1042
  { "cvtts/suim",       FP(0x16,0x76C), BASE, ARG_FPZ1 },
1043
  { "cvttq/svim",       FP(0x16,0x76F), BASE, ARG_FPZ1 },
1044
  { "cvtqs/suim",       FP(0x16,0x77C), BASE, ARG_FPZ1 },
1045
  { "cvtqt/suim",       FP(0x16,0x77E), BASE, ARG_FPZ1 },
1046
  { "adds/sui",         FP(0x16,0x780), BASE, ARG_FP },
1047
  { "negs/sui",         FP(0x16,0x781), BASE, ARG_FPZ1 },       /* pseudo */
1048
  { "subs/sui",         FP(0x16,0x781), BASE, ARG_FP },
1049
  { "muls/sui",         FP(0x16,0x782), BASE, ARG_FP },
1050
  { "divs/sui",         FP(0x16,0x783), BASE, ARG_FP },
1051
  { "addt/sui",         FP(0x16,0x7A0), BASE, ARG_FP },
1052
  { "negt/sui",         FP(0x16,0x7A1), BASE, ARG_FPZ1 },       /* pseudo */
1053
  { "subt/sui",         FP(0x16,0x7A1), BASE, ARG_FP },
1054
  { "mult/sui",         FP(0x16,0x7A2), BASE, ARG_FP },
1055
  { "divt/sui",         FP(0x16,0x7A3), BASE, ARG_FP },
1056
  { "cvtts/sui",        FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1057
  { "cvttq/svi",        FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1058
  { "cvtqs/sui",        FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1059
  { "cvtqt/sui",        FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1060
  { "adds/suid",        FP(0x16,0x7C0), BASE, ARG_FP },
1061
  { "subs/suid",        FP(0x16,0x7C1), BASE, ARG_FP },
1062
  { "muls/suid",        FP(0x16,0x7C2), BASE, ARG_FP },
1063
  { "divs/suid",        FP(0x16,0x7C3), BASE, ARG_FP },
1064
  { "addt/suid",        FP(0x16,0x7E0), BASE, ARG_FP },
1065
  { "subt/suid",        FP(0x16,0x7E1), BASE, ARG_FP },
1066
  { "mult/suid",        FP(0x16,0x7E2), BASE, ARG_FP },
1067
  { "divt/suid",        FP(0x16,0x7E3), BASE, ARG_FP },
1068
  { "cvtts/suid",       FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1069
  { "cvttq/svid",       FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1070
  { "cvtqs/suid",       FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1071
  { "cvtqt/suid",       FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1072
 
1073
  { "cvtlq",            FP(0x17,0x010), BASE, ARG_FPZ1 },
1074
  { "fnop",             FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1075
  { "fclr",             FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1076
  { "fabs",             FP(0x17,0x020), BASE, ARG_FPZ1 },       /* pseudo */
1077
  { "fmov",             FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1078
  { "cpys",             FP(0x17,0x020), BASE, ARG_FP },
1079
  { "fneg",             FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1080
  { "cpysn",            FP(0x17,0x021), BASE, ARG_FP },
1081
  { "cpyse",            FP(0x17,0x022), BASE, ARG_FP },
1082
  { "mt_fpcr",          FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1083
  { "mf_fpcr",          FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1084
  { "fcmoveq",          FP(0x17,0x02A), BASE, ARG_FP },
1085
  { "fcmovne",          FP(0x17,0x02B), BASE, ARG_FP },
1086
  { "fcmovlt",          FP(0x17,0x02C), BASE, ARG_FP },
1087
  { "fcmovge",          FP(0x17,0x02D), BASE, ARG_FP },
1088
  { "fcmovle",          FP(0x17,0x02E), BASE, ARG_FP },
1089
  { "fcmovgt",          FP(0x17,0x02F), BASE, ARG_FP },
1090
  { "cvtql",            FP(0x17,0x030), BASE, ARG_FPZ1 },
1091
  { "cvtql/v",          FP(0x17,0x130), BASE, ARG_FPZ1 },
1092
  { "cvtql/sv",         FP(0x17,0x530), BASE, ARG_FPZ1 },
1093
 
1094
  { "trapb",            MFC(0x18,0x0000), BASE, ARG_NONE },
1095
  { "draint",           MFC(0x18,0x0000), BASE, ARG_NONE },     /* alias */
1096
  { "excb",             MFC(0x18,0x0400), BASE, ARG_NONE },
1097
  { "mb",               MFC(0x18,0x4000), BASE, ARG_NONE },
1098
  { "wmb",              MFC(0x18,0x4400), BASE, ARG_NONE },
1099
  { "fetch",            MFC(0x18,0x8000), BASE, { ZA, PRB } },
1100
  { "fetch_m",          MFC(0x18,0xA000), BASE, { ZA, PRB } },
1101
  { "rpcc",             MFC(0x18,0xC000), BASE, { RA } },
1102
  { "rc",               MFC(0x18,0xE000), BASE, { RA } },
1103
  { "ecb",              MFC(0x18,0xE800), BASE, { ZA, PRB } },  /* ev56 una */
1104
  { "rs",               MFC(0x18,0xF000), BASE, { RA } },
1105
  { "wh64",             MFC(0x18,0xF800), BASE, { ZA, PRB } },  /* ev56 una */
1106
 
1107
  { "hw_mfpr",          OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1108
  { "hw_mfpr",          OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1109
  { "hw_mfpr",          OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1110
  { "hw_mfpr/i",        OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1111
  { "hw_mfpr/a",        OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1112
  { "hw_mfpr/ai",       OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1113
  { "hw_mfpr/p",        OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1114
  { "hw_mfpr/pi",       OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1115
  { "hw_mfpr/pa",       OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1116
  { "hw_mfpr/pai",      OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1117
  { "pal19",            PCD(0x19), BASE, ARG_PCD },
1118
 
1119
  { "jmp",              MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1120
  { "jsr",              MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1121
  { "ret",              MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1122
  { "jcr",              MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1123
  { "jsr_coroutine",    MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1124
 
1125
  { "hw_ldl",           EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1126
  { "hw_ldl",           EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1127
  { "hw_ldl",           EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1128
  { "hw_ldl/a",         EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1129
  { "hw_ldl/a",         EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1130
  { "hw_ldl/a",         EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1131
  { "hw_ldl/al",        EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1132
  { "hw_ldl/ar",        EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1133
  { "hw_ldl/av",        EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1134
  { "hw_ldl/avl",       EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1135
  { "hw_ldl/aw",        EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1136
  { "hw_ldl/awl",       EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1137
  { "hw_ldl/awv",       EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1138
  { "hw_ldl/awvl",      EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1139
  { "hw_ldl/l",         EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1140
  { "hw_ldl/p",         EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1141
  { "hw_ldl/p",         EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1142
  { "hw_ldl/p",         EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1143
  { "hw_ldl/pa",        EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1144
  { "hw_ldl/pa",        EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1145
  { "hw_ldl/pal",       EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1146
  { "hw_ldl/par",       EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1147
  { "hw_ldl/pav",       EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1148
  { "hw_ldl/pavl",      EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1149
  { "hw_ldl/paw",       EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1150
  { "hw_ldl/pawl",      EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1151
  { "hw_ldl/pawv",      EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1152
  { "hw_ldl/pawvl",     EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1153
  { "hw_ldl/pl",        EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1154
  { "hw_ldl/pr",        EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1155
  { "hw_ldl/pv",        EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1156
  { "hw_ldl/pvl",       EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1157
  { "hw_ldl/pw",        EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1158
  { "hw_ldl/pwl",       EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1159
  { "hw_ldl/pwv",       EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1160
  { "hw_ldl/pwvl",      EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1161
  { "hw_ldl/r",         EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1162
  { "hw_ldl/v",         EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1163
  { "hw_ldl/v",         EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1164
  { "hw_ldl/vl",        EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1165
  { "hw_ldl/w",         EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1166
  { "hw_ldl/w",         EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1167
  { "hw_ldl/wa",        EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1168
  { "hw_ldl/wl",        EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1169
  { "hw_ldl/wv",        EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1170
  { "hw_ldl/wvl",       EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1171
  { "hw_ldl_l",         EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1172
  { "hw_ldl_l/a",       EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1173
  { "hw_ldl_l/av",      EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1174
  { "hw_ldl_l/aw",      EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1175
  { "hw_ldl_l/awv",     EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1176
  { "hw_ldl_l/p",       EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1177
  { "hw_ldl_l/p",       EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1178
  { "hw_ldl_l/pa",      EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1179
  { "hw_ldl_l/pav",     EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1180
  { "hw_ldl_l/paw",     EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1181
  { "hw_ldl_l/pawv",    EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1182
  { "hw_ldl_l/pv",      EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1183
  { "hw_ldl_l/pw",      EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1184
  { "hw_ldl_l/pwv",     EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1185
  { "hw_ldl_l/v",       EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1186
  { "hw_ldl_l/w",       EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1187
  { "hw_ldl_l/wv",      EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1188
  { "hw_ldq",           EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1189
  { "hw_ldq",           EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1190
  { "hw_ldq",           EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1191
  { "hw_ldq/a",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1192
  { "hw_ldq/a",         EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1193
  { "hw_ldq/a",         EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1194
  { "hw_ldq/al",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1195
  { "hw_ldq/ar",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1196
  { "hw_ldq/av",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1197
  { "hw_ldq/avl",       EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1198
  { "hw_ldq/aw",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1199
  { "hw_ldq/awl",       EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1200
  { "hw_ldq/awv",       EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1201
  { "hw_ldq/awvl",      EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1202
  { "hw_ldq/l",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1203
  { "hw_ldq/p",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1204
  { "hw_ldq/p",         EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1205
  { "hw_ldq/p",         EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1206
  { "hw_ldq/pa",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1207
  { "hw_ldq/pa",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1208
  { "hw_ldq/pal",       EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1209
  { "hw_ldq/par",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1210
  { "hw_ldq/pav",       EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1211
  { "hw_ldq/pavl",      EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1212
  { "hw_ldq/paw",       EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1213
  { "hw_ldq/pawl",      EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1214
  { "hw_ldq/pawv",      EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1215
  { "hw_ldq/pawvl",     EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1216
  { "hw_ldq/pl",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1217
  { "hw_ldq/pr",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1218
  { "hw_ldq/pv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1219
  { "hw_ldq/pvl",       EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1220
  { "hw_ldq/pw",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1221
  { "hw_ldq/pwl",       EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1222
  { "hw_ldq/pwv",       EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1223
  { "hw_ldq/pwvl",      EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1224
  { "hw_ldq/r",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1225
  { "hw_ldq/v",         EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1226
  { "hw_ldq/v",         EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1227
  { "hw_ldq/vl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1228
  { "hw_ldq/w",         EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1229
  { "hw_ldq/w",         EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1230
  { "hw_ldq/wa",        EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1231
  { "hw_ldq/wl",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1232
  { "hw_ldq/wv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1233
  { "hw_ldq/wvl",       EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1234
  { "hw_ldq_l",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1235
  { "hw_ldq_l/a",       EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1236
  { "hw_ldq_l/av",      EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1237
  { "hw_ldq_l/aw",      EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1238
  { "hw_ldq_l/awv",     EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1239
  { "hw_ldq_l/p",       EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1240
  { "hw_ldq_l/p",       EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1241
  { "hw_ldq_l/pa",      EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1242
  { "hw_ldq_l/pav",     EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1243
  { "hw_ldq_l/paw",     EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1244
  { "hw_ldq_l/pawv",    EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1245
  { "hw_ldq_l/pv",      EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1246
  { "hw_ldq_l/pw",      EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1247
  { "hw_ldq_l/pwv",     EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1248
  { "hw_ldq_l/v",       EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1249
  { "hw_ldq_l/w",       EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1250
  { "hw_ldq_l/wv",      EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1251
  { "hw_ld",            EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1252
  { "hw_ld",            EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1253
  { "hw_ld/a",          EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1254
  { "hw_ld/a",          EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1255
  { "hw_ld/al",         EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1256
  { "hw_ld/aq",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1257
  { "hw_ld/aq",         EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1258
  { "hw_ld/aql",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1259
  { "hw_ld/aqv",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1260
  { "hw_ld/aqvl",       EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1261
  { "hw_ld/ar",         EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1262
  { "hw_ld/arq",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1263
  { "hw_ld/av",         EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1264
  { "hw_ld/avl",        EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1265
  { "hw_ld/aw",         EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1266
  { "hw_ld/awl",        EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1267
  { "hw_ld/awq",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1268
  { "hw_ld/awql",       EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1269
  { "hw_ld/awqv",       EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1270
  { "hw_ld/awqvl",      EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1271
  { "hw_ld/awv",        EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1272
  { "hw_ld/awvl",       EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1273
  { "hw_ld/l",          EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1274
  { "hw_ld/p",          EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1275
  { "hw_ld/p",          EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1276
  { "hw_ld/pa",         EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1277
  { "hw_ld/pa",         EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1278
  { "hw_ld/pal",        EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1279
  { "hw_ld/paq",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1280
  { "hw_ld/paq",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1281
  { "hw_ld/paql",       EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1282
  { "hw_ld/paqv",       EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1283
  { "hw_ld/paqvl",      EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1284
  { "hw_ld/par",        EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1285
  { "hw_ld/parq",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1286
  { "hw_ld/pav",        EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1287
  { "hw_ld/pavl",       EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1288
  { "hw_ld/paw",        EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1289
  { "hw_ld/pawl",       EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1290
  { "hw_ld/pawq",       EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1291
  { "hw_ld/pawql",      EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1292
  { "hw_ld/pawqv",      EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1293
  { "hw_ld/pawqvl",     EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1294
  { "hw_ld/pawv",       EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1295
  { "hw_ld/pawvl",      EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1296
  { "hw_ld/pl",         EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1297
  { "hw_ld/pq",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1298
  { "hw_ld/pq",         EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1299
  { "hw_ld/pql",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1300
  { "hw_ld/pqv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1301
  { "hw_ld/pqvl",       EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1302
  { "hw_ld/pr",         EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1303
  { "hw_ld/prq",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1304
  { "hw_ld/pv",         EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1305
  { "hw_ld/pvl",        EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1306
  { "hw_ld/pw",         EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1307
  { "hw_ld/pwl",        EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1308
  { "hw_ld/pwq",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1309
  { "hw_ld/pwql",       EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1310
  { "hw_ld/pwqv",       EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1311
  { "hw_ld/pwqvl",      EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1312
  { "hw_ld/pwv",        EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1313
  { "hw_ld/pwvl",       EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1314
  { "hw_ld/q",          EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1315
  { "hw_ld/q",          EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1316
  { "hw_ld/ql",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1317
  { "hw_ld/qv",         EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1318
  { "hw_ld/qvl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1319
  { "hw_ld/r",          EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1320
  { "hw_ld/rq",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1321
  { "hw_ld/v",          EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1322
  { "hw_ld/vl",         EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1323
  { "hw_ld/w",          EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1324
  { "hw_ld/wl",         EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1325
  { "hw_ld/wq",         EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1326
  { "hw_ld/wql",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1327
  { "hw_ld/wqv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1328
  { "hw_ld/wqvl",       EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1329
  { "hw_ld/wv",         EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1330
  { "hw_ld/wvl",        EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1331
  { "pal1b",            PCD(0x1B), BASE, ARG_PCD },
1332
 
1333
  { "sextb",            OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1334
  { "sextw",            OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1335
  { "ctpop",            OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1336
  { "perr",             OPR(0x1C, 0x31), MAX, ARG_OPR },
1337
  { "ctlz",             OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1338
  { "cttz",             OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1339
  { "unpkbw",           OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1340
  { "unpkbl",           OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1341
  { "pkwb",             OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1342
  { "pklb",             OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1343
  { "minsb8",           OPR(0x1C, 0x38), MAX, ARG_OPR },
1344
  { "minsb8",           OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1345
  { "minsw4",           OPR(0x1C, 0x39), MAX, ARG_OPR },
1346
  { "minsw4",           OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1347
  { "minub8",           OPR(0x1C, 0x3A), MAX, ARG_OPR },
1348
  { "minub8",           OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1349
  { "minuw4",           OPR(0x1C, 0x3B), MAX, ARG_OPR },
1350
  { "minuw4",           OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1351
  { "maxub8",           OPR(0x1C, 0x3C), MAX, ARG_OPR },
1352
  { "maxub8",           OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1353
  { "maxuw4",           OPR(0x1C, 0x3D), MAX, ARG_OPR },
1354
  { "maxuw4",           OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1355
  { "maxsb8",           OPR(0x1C, 0x3E), MAX, ARG_OPR },
1356
  { "maxsb8",           OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1357
  { "maxsw4",           OPR(0x1C, 0x3F), MAX, ARG_OPR },
1358
  { "maxsw4",           OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1359
  { "ftoit",            FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1360
  { "ftois",            FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1361
 
1362
  { "hw_mtpr",          OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1363
  { "hw_mtpr",          OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1364
  { "hw_mtpr",          OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1365
  { "hw_mtpr/i",        OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1366
  { "hw_mtpr/a",        OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1367
  { "hw_mtpr/ai",       OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1368
  { "hw_mtpr/p",        OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1369
  { "hw_mtpr/pi",       OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1370
  { "hw_mtpr/pa",       OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1371
  { "hw_mtpr/pai",      OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1372
  { "pal1d",            PCD(0x1D), BASE, ARG_PCD },
1373
 
1374
  { "hw_rei",           SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1375
  { "hw_rei_stall",     SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1376
  { "hw_jmp",           EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1377
  { "hw_jsr",           EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1378
  { "hw_ret",           EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1379
  { "hw_jcr",           EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1380
  { "hw_coroutine",     EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1381
  { "hw_jmp/stall",     EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1382
  { "hw_jsr/stall",     EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1383
  { "hw_ret/stall",     EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1384
  { "hw_jcr/stall",     EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1385
  { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1386
  { "pal1e",            PCD(0x1E), BASE, ARG_PCD },
1387
 
1388
  { "hw_stl",           EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1389
  { "hw_stl",           EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1390
  { "hw_stl",           EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1391
  { "hw_stl/a",         EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1392
  { "hw_stl/a",         EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1393
  { "hw_stl/a",         EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1394
  { "hw_stl/ac",        EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1395
  { "hw_stl/ar",        EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1396
  { "hw_stl/av",        EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1397
  { "hw_stl/avc",       EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1398
  { "hw_stl/c",         EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1399
  { "hw_stl/p",         EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1400
  { "hw_stl/p",         EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1401
  { "hw_stl/p",         EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1402
  { "hw_stl/pa",        EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1403
  { "hw_stl/pa",        EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1404
  { "hw_stl/pac",       EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1405
  { "hw_stl/pav",       EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1406
  { "hw_stl/pavc",      EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1407
  { "hw_stl/pc",        EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1408
  { "hw_stl/pr",        EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1409
  { "hw_stl/pv",        EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1410
  { "hw_stl/pvc",       EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1411
  { "hw_stl/r",         EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1412
  { "hw_stl/v",         EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1413
  { "hw_stl/vc",        EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1414
  { "hw_stl_c",         EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1415
  { "hw_stl_c/a",       EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1416
  { "hw_stl_c/av",      EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1417
  { "hw_stl_c/p",       EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1418
  { "hw_stl_c/p",       EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1419
  { "hw_stl_c/pa",      EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1420
  { "hw_stl_c/pav",     EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1421
  { "hw_stl_c/pv",      EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1422
  { "hw_stl_c/v",       EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1423
  { "hw_stq",           EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1424
  { "hw_stq",           EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1425
  { "hw_stq",           EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1426
  { "hw_stq/a",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1427
  { "hw_stq/a",         EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1428
  { "hw_stq/a",         EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1429
  { "hw_stq/ac",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1430
  { "hw_stq/ar",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1431
  { "hw_stq/av",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1432
  { "hw_stq/avc",       EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1433
  { "hw_stq/c",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1434
  { "hw_stq/p",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1435
  { "hw_stq/p",         EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1436
  { "hw_stq/p",         EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1437
  { "hw_stq/pa",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1438
  { "hw_stq/pa",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1439
  { "hw_stq/pac",       EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1440
  { "hw_stq/par",       EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1441
  { "hw_stq/par",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1442
  { "hw_stq/pav",       EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1443
  { "hw_stq/pavc",      EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1444
  { "hw_stq/pc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1445
  { "hw_stq/pr",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1446
  { "hw_stq/pv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1447
  { "hw_stq/pvc",       EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1448
  { "hw_stq/r",         EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1449
  { "hw_stq/v",         EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1450
  { "hw_stq/vc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1451
  { "hw_stq_c",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1452
  { "hw_stq_c/a",       EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1453
  { "hw_stq_c/av",      EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1454
  { "hw_stq_c/p",       EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1455
  { "hw_stq_c/p",       EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1456
  { "hw_stq_c/pa",      EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1457
  { "hw_stq_c/pav",     EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1458
  { "hw_stq_c/pv",      EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1459
  { "hw_stq_c/v",       EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1460
  { "hw_st",            EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1461
  { "hw_st",            EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1462
  { "hw_st/a",          EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1463
  { "hw_st/a",          EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1464
  { "hw_st/ac",         EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1465
  { "hw_st/aq",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1466
  { "hw_st/aq",         EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1467
  { "hw_st/aqc",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1468
  { "hw_st/aqv",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1469
  { "hw_st/aqvc",       EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1470
  { "hw_st/ar",         EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1471
  { "hw_st/arq",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1472
  { "hw_st/av",         EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1473
  { "hw_st/avc",        EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1474
  { "hw_st/c",          EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1475
  { "hw_st/p",          EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1476
  { "hw_st/p",          EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1477
  { "hw_st/pa",         EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1478
  { "hw_st/pa",         EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1479
  { "hw_st/pac",        EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1480
  { "hw_st/paq",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1481
  { "hw_st/paq",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1482
  { "hw_st/paqc",       EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1483
  { "hw_st/paqv",       EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1484
  { "hw_st/paqvc",      EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1485
  { "hw_st/par",        EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1486
  { "hw_st/parq",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1487
  { "hw_st/pav",        EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1488
  { "hw_st/pavc",       EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1489
  { "hw_st/pc",         EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1490
  { "hw_st/pq",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1491
  { "hw_st/pq",         EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1492
  { "hw_st/pqc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1493
  { "hw_st/pqv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1494
  { "hw_st/pqvc",       EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1495
  { "hw_st/pr",         EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1496
  { "hw_st/prq",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1497
  { "hw_st/pv",         EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1498
  { "hw_st/pvc",        EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1499
  { "hw_st/q",          EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1500
  { "hw_st/q",          EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1501
  { "hw_st/qc",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1502
  { "hw_st/qv",         EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1503
  { "hw_st/qvc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1504
  { "hw_st/r",          EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1505
  { "hw_st/v",          EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1506
  { "hw_st/vc",         EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1507
  { "pal1f",            PCD(0x1F), BASE, ARG_PCD },
1508
 
1509
  { "ldf",              MEM(0x20), BASE, ARG_FMEM },
1510
  { "ldg",              MEM(0x21), BASE, ARG_FMEM },
1511
  { "lds",              MEM(0x22), BASE, ARG_FMEM },
1512
  { "ldt",              MEM(0x23), BASE, ARG_FMEM },
1513
  { "stf",              MEM(0x24), BASE, ARG_FMEM },
1514
  { "stg",              MEM(0x25), BASE, ARG_FMEM },
1515
  { "sts",              MEM(0x26), BASE, ARG_FMEM },
1516
  { "stt",              MEM(0x27), BASE, ARG_FMEM },
1517
 
1518
  { "ldl",              MEM(0x28), BASE, ARG_MEM },
1519
  { "ldq",              MEM(0x29), BASE, ARG_MEM },
1520
  { "ldl_l",            MEM(0x2A), BASE, ARG_MEM },
1521
  { "ldq_l",            MEM(0x2B), BASE, ARG_MEM },
1522
  { "stl",              MEM(0x2C), BASE, ARG_MEM },
1523
  { "stq",              MEM(0x2D), BASE, ARG_MEM },
1524
  { "stl_c",            MEM(0x2E), BASE, ARG_MEM },
1525
  { "stq_c",            MEM(0x2F), BASE, ARG_MEM },
1526
 
1527
  { "br",               BRA(0x30), BASE, { ZA, BDISP } },       /* pseudo */
1528
  { "br",               BRA(0x30), BASE, ARG_BRA },
1529
  { "fbeq",             BRA(0x31), BASE, ARG_FBRA },
1530
  { "fblt",             BRA(0x32), BASE, ARG_FBRA },
1531
  { "fble",             BRA(0x33), BASE, ARG_FBRA },
1532
  { "bsr",              BRA(0x34), BASE, ARG_BRA },
1533
  { "fbne",             BRA(0x35), BASE, ARG_FBRA },
1534
  { "fbge",             BRA(0x36), BASE, ARG_FBRA },
1535
  { "fbgt",             BRA(0x37), BASE, ARG_FBRA },
1536
  { "blbc",             BRA(0x38), BASE, ARG_BRA },
1537
  { "beq",              BRA(0x39), BASE, ARG_BRA },
1538
  { "blt",              BRA(0x3A), BASE, ARG_BRA },
1539
  { "ble",              BRA(0x3B), BASE, ARG_BRA },
1540
  { "blbs",             BRA(0x3C), BASE, ARG_BRA },
1541
  { "bne",              BRA(0x3D), BASE, ARG_BRA },
1542
  { "bge",              BRA(0x3E), BASE, ARG_BRA },
1543
  { "bgt",              BRA(0x3F), BASE, ARG_BRA },
1544
};
1545
 
1546
const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);

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