OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.0/] [opcodes/] [i370-opc.c] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom
/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
2
   Copyright 1994, 1999, 2000 Free Software Foundation, Inc.
3
   PowerPC version written by Ian Lance Taylor, Cygnus Support
4
   Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
5
 
6
This file is part of GDB, GAS, and the GNU binutils.
7
 
8
GDB, GAS, and the GNU binutils are free software; you can redistribute
9
them and/or modify them under the terms of the GNU General Public
10
License as published by the Free Software Foundation; either version
11
2, or (at your option) any later version.
12
 
13
GDB, GAS, and the GNU binutils are distributed in the hope that they
14
will be useful, but WITHOUT ANY WARRANTY; without even the implied
15
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
16
the GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this file; see the file COPYING.  If not, write to the Free
20
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21
02111-1307, USA.  */
22
 
23
#include <stdio.h>
24
#include "ansidecl.h"
25
#include "opcode/i370.h"
26
 
27
/* This file holds the i370 opcode table.  The opcode table
28
   includes almost all of the extended instruction mnemonics.  This
29
   permits the disassembler to use them, and simplifies the assembler
30
   logic, at the cost of increasing the table size.  The table is
31
   strictly constant data, so the compiler should be able to put it in
32
   the .text section.
33
 
34
   This file also holds the operand table.  All knowledge about
35
   inserting operands into instructions and vice-versa is kept in this
36
   file.  */
37
 
38
/* Local insertion and extraction functions.  */
39
static i370_insn_t insert_ss_b2  PARAMS (( i370_insn_t, long, const char **));
40
static i370_insn_t insert_ss_d2  PARAMS (( i370_insn_t, long, const char **));
41
static i370_insn_t insert_rxf_r3  PARAMS (( i370_insn_t, long, const char **));
42
static long extract_ss_b2 PARAMS (( i370_insn_t, int *));
43
static long extract_ss_d2 PARAMS (( i370_insn_t, int *));
44
static long extract_rxf_r3 PARAMS (( i370_insn_t, int *));
45
 
46
 
47
/* The operands table.
48
   The fields are bits, shift, insert, extract, flags, name.
49
   The types:
50
   I370_OPERAND_GPR register, must name a register, must be present
51
   I370_OPERAND_RELATIVE displacement or legnth field, must be present
52
   I370_OPERAND_BASE base register; if present, must name a register
53
                      if absent, should take value of zero
54
   I370_OPERAND_INDEX index register; if present, must name a register
55
                      if absent, should take value of zero
56
   I370_OPERAND_OPTIONAL other optional operand (usuall reg?)
57
*/
58
 
59
const struct i370_operand i370_operands[] =
60
{
61
  /* The zero index is used to indicate the end of the list of
62
     operands.  */
63
#define UNUSED 0
64
  { 0, 0, 0, 0, 0, "unused" },
65
 
66
  /* The R1 register field in an RR form instruction.  */
67
#define RR_R1 (UNUSED + 1)
68
#define RR_R1_MASK (0xf << 4)
69
  { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },
70
 
71
  /* The R2 register field in an RR form instruction.  */
72
#define RR_R2 (RR_R1 + 1)
73
#define RR_R2_MASK (0xf)
74
  { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },
75
 
76
  /* The I field in an RR form SVC-style instruction.  */
77
#define RR_I (RR_R2 + 1)
78
#define RR_I_MASK (0xff)
79
  { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },
80
 
81
  /* The R1 register field in an RRE form instruction.  */
82
#define RRE_R1 (RR_I + 1)
83
#define RRE_R1_MASK (0xf << 4)
84
  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },
85
 
86
  /* The R2 register field in an RRE form instruction.  */
87
#define RRE_R2 (RRE_R1 + 1)
88
#define RRE_R2_MASK (0xf)
89
  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },
90
 
91
  /* The R1 register field in an RRF form instruction.  */
92
#define RRF_R1 (RRE_R2 + 1)
93
#define RRF_R1_MASK (0xf << 4)
94
  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },
95
 
96
  /* The R2 register field in an RRF form instruction.  */
97
#define RRF_R2 (RRF_R1 + 1)
98
#define RRF_R2_MASK (0xf)
99
  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },
100
 
101
  /* The R3 register field in an RRF form instruction.  */
102
#define RRF_R3 (RRF_R2 + 1)
103
#define RRF_R3_MASK (0xf << 12)
104
  { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },
105
 
106
  /* The R1 register field in an RX or RS form instruction.  */
107
#define RX_R1 (RRF_R3 + 1)
108
#define RX_R1_MASK (0xf << 20)
109
  { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },
110
 
111
  /* The X2 index field in an RX form instruction.  */
112
#define RX_X2 (RX_R1 + 1)
113
#define RX_X2_MASK (0xf << 16)
114
  { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},
115
 
116
  /* The B2 base field in an RX form instruction.  */
117
#define RX_B2 (RX_X2 + 1)
118
#define RX_B2_MASK (0xf << 12)
119
  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},
120
 
121
  /* The D2 displacement field in an RX form instruction.  */
122
#define RX_D2 (RX_B2 + 1)
123
#define RX_D2_MASK (0xfff)
124
  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},
125
 
126
 /* The R3 register field in an RXF form instruction.  */
127
#define RXF_R3 (RX_D2 + 1)
128
#define RXF_R3_MASK (0xf << 12)
129
  { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },
130
 
131
  /* The D2 displacement field in an RS form instruction.  */
132
#define RS_D2 (RXF_R3 + 1)
133
#define RS_D2_MASK (0xfff)
134
  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
135
 
136
  /* The R3 register field in an RS form instruction.  */
137
#define RS_R3 (RS_D2 + 1)
138
#define RS_R3_MASK (0xf << 16)
139
  { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
140
 
141
  /* The B2 base field in an RS form instruction.  */
142
#define RS_B2 (RS_R3 + 1)
143
#define RS_B2_MASK (0xf << 12)
144
  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
145
 
146
  /* The optional B2 base field in an RS form instruction.  */
147
  /* Note that this field will almost always be absent */
148
#define RS_B2_OPT (RS_B2 + 1)
149
#define RS_B2_OPT_MASK (0xf << 12)
150
  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
151
 
152
  /* The R1 register field in an RSI form instruction.  */
153
#define RSI_R1 (RS_B2_OPT + 1)
154
#define RSI_R1_MASK (0xf << 20)
155
  { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },
156
 
157
  /* The R3 register field in an RSI form instruction.  */
158
#define RSI_R3 (RSI_R1 + 1)
159
#define RSI_R3_MASK (0xf << 16)
160
  { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },
161
 
162
  /* The I2 immediate field in an RSI form instruction.  */
163
#define RSI_I2 (RSI_R3 + 1)
164
#define RSI_I2_MASK (0xffff)
165
  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },
166
 
167
  /* The R1 register field in an RI form instruction.  */
168
#define RI_R1 (RSI_I2 + 1)
169
#define RI_R1_MASK (0xf << 20)
170
  { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },
171
 
172
  /* The I2 immediate field in an RI form instruction.  */
173
#define RI_I2 (RI_R1 + 1)
174
#define RI_I2_MASK (0xffff)
175
  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },
176
 
177
 /* The I2 index field in an SI form instruction.  */
178
#define SI_I2 (RI_I2 + 1)
179
#define SI_I2_MASK (0xff << 16)
180
  { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},
181
 
182
 /* The B1 base register field in an SI form instruction.  */
183
#define SI_B1 (SI_I2 + 1)
184
#define SI_B1_MASK (0xf << 12)
185
  { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },
186
 
187
  /* The D1 displacement field in an SI form instruction.  */
188
#define SI_D1 (SI_B1 + 1)
189
#define SI_D1_MASK (0xfff)
190
  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },
191
 
192
 /* The B2 base register field in an S form instruction.  */
193
#define S_B2 (SI_D1 + 1)
194
#define S_B2_MASK (0xf << 12)
195
  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },
196
 
197
  /* The D2 displacement field in an S form instruction.  */
198
#define S_D2 (S_B2 + 1)
199
#define S_D2_MASK (0xfff)
200
  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
201
 
202
  /* The L length field in an SS form instruction. */
203
#define SS_L (S_D2 + 1)
204
#define SS_L_MASK (0xffff<<16)
205
  { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
206
 
207
 /* The B1 base register field in an SS form instruction.  */
208
#define SS_B1 (SS_L + 1)
209
#define SS_B1_MASK (0xf << 12)
210
  { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },
211
 
212
  /* The D1 displacement field in an SS form instruction.  */
213
#define SS_D1 (SS_B1 + 1)
214
#define SS_D1_MASK (0xfff)
215
  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },
216
 
217
 /* The B2 base register field in an SS form instruction.  */
218
#define SS_B2 (SS_D1 + 1)
219
#define SS_B2_MASK (0xf << 12)
220
  { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },
221
 
222
  /* The D2 displacement field in an SS form instruction.  */
223
#define SS_D2 (SS_B2 + 1)
224
#define SS_D2_MASK (0xfff)
225
  { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
226
 
227
 
228
};
229
 
230
/* The functions used to insert and extract complicated operands.  */
231
 
232
/*ARGSUSED*/
233
static i370_insn_t
234
insert_ss_b2 (insn, value, errmsg)
235
     i370_insn_t insn;
236
     long value;
237
     const char **errmsg;
238
{
239
  insn.i[1] |= (value & 0xf) << 28;
240
  return insn;
241
}
242
 
243
static i370_insn_t
244
insert_ss_d2 (insn, value, errmsg)
245
     i370_insn_t insn;
246
     long value;
247
     const char **errmsg;
248
{
249
  insn.i[1] |= (value & 0xfff) << 16;
250
  return insn;
251
}
252
 
253
static i370_insn_t
254
insert_rxf_r3 (insn, value, errmsg)
255
     i370_insn_t insn;
256
     long value;
257
     const char **errmsg;
258
{
259
  insn.i[1] |= (value & 0xf) << 28;
260
  return insn;
261
}
262
 
263
static long
264
extract_ss_b2 (insn, invalid)
265
     i370_insn_t insn;
266
     int *invalid;
267
{
268
  return (insn.i[1] >>28) & 0xf;
269
}
270
 
271
static long
272
extract_ss_d2 (insn, invalid)
273
     i370_insn_t insn;
274
     int *invalid;
275
{
276
  return (insn.i[1] >>16) & 0xfff;
277
}
278
 
279
static long
280
extract_rxf_r3 (insn, invalid)
281
     i370_insn_t insn;
282
     int *invalid;
283
{
284
  return (insn.i[1] >>28) & 0xf;
285
}
286
 
287
 
288
/* Macros used to form opcodes.  */
289
 
290
/* The short-instruction opcode.  */
291
#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)
292
#define OPS_MASK OPS (0xff)
293
 
294
/* the extended instruction opcode */
295
#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)
296
#define XOPS_MASK XOPS (0xff)
297
 
298
/* the S instruction opcode */
299
#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)
300
#define SOPS_MASK SOPS (0xffff)
301
 
302
/* the E instruction opcode */
303
#define EOPS(x) (((unsigned short)(x)) & 0xffff)
304
#define EOPS_MASK EOPS (0xffff)
305
 
306
/* the RI instruction opcode */
307
#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \
308
                 ((((unsigned short)(x)) & 0x00f) << 16))
309
#define ROPS_MASK ROPS (0xfff)
310
 
311
/* --------------------------------------------------------- */
312
/* An E form instruction.  */
313
#define E(op)  (EOPS (op))
314
#define E_MASK E (0xffff)
315
 
316
/* An RR form instruction.  */
317
#define RR(op, r1, r2) \
318
  (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
319
              ((((unsigned short)(r2)) & 0xf) ))
320
 
321
#define RR_MASK RR (0xff, 0x0, 0x0)
322
 
323
/* An SVC-style instruction.  */
324
#define SVC(op, i) \
325
  (OPS (op) | (((unsigned short)(i)) & 0xff))
326
 
327
#define SVC_MASK SVC (0xff, 0x0)
328
 
329
/* An RRE form instruction.  */
330
#define RRE(op, r1, r2) \
331
  (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
332
               ((((unsigned short)(r2)) & 0xf) ))
333
 
334
#define RRE_MASK RRE (0xffff, 0x0, 0x0)
335
 
336
/* An RRF form instruction.  */
337
#define RRF(op, r3, r1, r2) \
338
  (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) |   \
339
               ((((unsigned short)(r1)) & 0xf) << 4)  |   \
340
               ((((unsigned short)(r2)) & 0xf) ))
341
 
342
#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
343
 
344
/* An RX form instruction. */
345
#define RX(op, r1, x2, b2, d2) \
346
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
347
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
348
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
349
              ((((unsigned short)(d2)) & 0xfff)))
350
 
351
#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
352
 
353
/* An RXE form instruction high word. */
354
#define RXEH(op, r1, x2, b2, d2) \
355
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
356
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
357
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
358
              ((((unsigned short)(d2)) & 0xfff)))
359
 
360
#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
361
 
362
/* An RXE form instruction low word. */
363
#define RXEL(op) \
364
              ((((unsigned short)(op)) & 0xff) << 16 )
365
 
366
#define RXEL_MASK RXEL (0xff)
367
 
368
/* An RXF form instruction high word. */
369
#define RXFH(op, r1, x2, b2, d2) \
370
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
371
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
372
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
373
              ((((unsigned short)(d2)) & 0xfff)))
374
 
375
#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
376
 
377
/* An RXF form instruction low word. */
378
#define RXFL(op, r3) \
379
              (((((unsigned short)(r3)) & 0xf)  << 28 ) | \
380
               ((((unsigned short)(op)) & 0xff) << 16 ))
381
 
382
#define RXFL_MASK RXFL (0xff, 0)
383
 
384
/* An RS form instruction. */
385
#define RS(op, r1, b3, b2, d2) \
386
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
387
              ((((unsigned short)(b3)) & 0xf) << 16) |  \
388
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
389
              ((((unsigned short)(d2)) & 0xfff)))
390
 
391
#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
392
 
393
/* An RSI form instruction. */
394
#define RSI(op, r1, r3, i2) \
395
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
396
              ((((unsigned short)(r3)) & 0xf) << 16) |  \
397
              ((((unsigned short)(i2)) & 0xffff)))
398
 
399
#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
400
 
401
/* An RI form instruction. */
402
#define RI(op, r1, i2) \
403
  (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
404
              ((((unsigned short)(i2)) & 0xffff)))
405
 
406
#define RI_MASK RI (0xfff, 0x0, 0x0)
407
 
408
/* An SI form instruction. */
409
#define SI(op, i2, b1, d1) \
410
  (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) |  \
411
              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
412
              ((((unsigned short)(d1)) & 0xfff)))
413
 
414
#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
415
 
416
/* An S form instruction. */
417
#define S(op, b2, d2) \
418
  (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \
419
              ((((unsigned short)(d2)) & 0xfff)))
420
 
421
#define S_MASK S (0xffff, 0x0, 0x0)
422
 
423
/* An SS form instruction high word. */
424
#define SSH(op, l, b1, d1) \
425
  (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) |  \
426
              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
427
              ((((unsigned short)(d1)) & 0xfff)))
428
 
429
/* An SS form instruction low word. */
430
#define SSL(b2, d2) \
431
            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
432
              ((((unsigned short)(d1)) & 0xfff) << 16 ))
433
 
434
#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
435
 
436
/* An SSE form instruction high word. */
437
#define SSEH(op, b1, d1) \
438
  (SOPS(op) | ((((unsigned short)(b1)) & 0xf)  << 12) |  \
439
              ((((unsigned short)(d1)) & 0xfff)))
440
 
441
/* An SSE form instruction low word. */
442
#define SSEL(b2, d2) \
443
            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
444
              ((((unsigned short)(d1)) & 0xfff) << 16 ))
445
 
446
#define SSE_MASK SSEH (0xffff, 0x0, 0x0)
447
 
448
 
449
/* Smaller names for the flags so each entry in the opcodes table will
450
   fit on a single line.  These flags are set up so that e.g. IXA means
451
   the insn is supported on the 370/XA or newer architecture.
452
   Note that 370 or older obsolete insn's are not supported ...
453
 */
454
#define IBF     I370_OPCODE_ESA390_BF
455
#define IBS     I370_OPCODE_ESA390_BS
456
#define ICK     I370_OPCODE_ESA390_CK
457
#define ICM     I370_OPCODE_ESA390_CM
458
#define IFX     I370_OPCODE_ESA390_FX
459
#define IHX     I370_OPCODE_ESA390_HX
460
#define IIR     I370_OPCODE_ESA390_IR
461
#define IMI     I370_OPCODE_ESA390_MI
462
#define IPC     I370_OPCODE_ESA390_PC
463
#define IPL     I370_OPCODE_ESA390_PL
464
#define IQR     I370_OPCODE_ESA390_QR
465
#define IRP     I370_OPCODE_ESA390_RP
466
#define ISA     I370_OPCODE_ESA390_SA
467
#define ISG     I370_OPCODE_ESA390_SG
468
#define ISR     I370_OPCODE_ESA390_SR
469
#define ITR     I370_OPCODE_ESA390_SR
470
#define I390    IBF  | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
471
#define IESA    I390 | I370_OPCODE_ESA370
472
#define IXA     IESA | I370_OPCODE_370_XA
473
#define I370    IXA  | I370_OPCODE_370
474
#define I360    I370 | I370_OPCODE_360
475
 
476
 
477
/* The opcode table.
478
 
479
   The format of the opcode table is:
480
 
481
   NAME     LEN  OPCODE_HI  OPCODE_LO   MASK_HI MASK_LO FLAGS           { OPERANDS }
482
 
483
   NAME is the name of the instruction.
484
   OPCODE is the instruction opcode.
485
   MASK is the opcode mask; this is used to tell the disassembler
486
     which bits in the actual opcode must match OPCODE.
487
   FLAGS are flags indicated what processors support the instruction.
488
   OPERANDS is the list of operands.
489
 
490
   The disassembler reads the table in order and prints the first
491
   instruction which matches, so this table is sorted to put more
492
   specific instructions before more general instructions.  It is also
493
   sorted by major opcode.  */
494
 
495
const struct i370_opcode i370_opcodes[] = {
496
 
497
/* E form instructions */
498
{ "pr",     2, {E(0x0101),    0}, {E_MASK,  0}, IESA,  {0} },
499
 
500
{ "trap2",  2, {E(0x01FF),    0}, {E_MASK,  0}, ITR,   {0} },
501
{ "upt",    2, {E(0x0102),    0}, {E_MASK,  0}, IXA,   {0} },
502
 
503
/* RR form instructions */
504
{ "ar",     2, {RR(0x1a,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
505
{ "adr",    2, {RR(0x2a,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
506
{ "aer",    2, {RR(0x3a,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
507
{ "alr",    2, {RR(0x1e,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
508
{ "aur",    2, {RR(0x2e,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
509
{ "awr",    2, {RR(0x3e,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
510
{ "axr",    2, {RR(0x36,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
511
{ "balr",   2, {RR(0x05,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
512
{ "basr",   2, {RR(0x0d,0,0), 0}, {RR_MASK, 0}, IXA,   {RR_R1, RR_R2} },
513
{ "bassm",  2, {RR(0x0c,0,0), 0}, {RR_MASK, 0}, IXA,   {RR_R1, RR_R2} },
514
{ "bsm",    2, {RR(0x0b,0,0), 0}, {RR_MASK, 0}, IXA,   {RR_R1, RR_R2} },
515
{ "bcr",    2, {RR(0x07,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
516
{ "bctr",   2, {RR(0x06,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
517
{ "cdr",    2, {RR(0x29,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
518
{ "cer",    2, {RR(0x39,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
519
{ "clr",    2, {RR(0x15,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
520
{ "clcl",   2, {RR(0x0f,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
521
{ "cr",     2, {RR(0x19,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
522
{ "ddr",    2, {RR(0x2d,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
523
{ "der",    2, {RR(0x3d,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
524
{ "dr",     2, {RR(0x1d,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
525
{ "hdr",    2, {RR(0x24,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
526
{ "her",    2, {RR(0x34,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
527
{ "lcdr",   2, {RR(0x23,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
528
{ "lcer",   2, {RR(0x33,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
529
{ "lcr",    2, {RR(0x13,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
530
{ "ldr",    2, {RR(0x28,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
531
{ "ler",    2, {RR(0x38,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
532
{ "lndr",   2, {RR(0x21,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
533
{ "lner",   2, {RR(0x31,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
534
{ "lnr",    2, {RR(0x11,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
535
{ "lpdr",   2, {RR(0x20,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
536
{ "lper",   2, {RR(0x30,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
537
{ "lpr",    2, {RR(0x10,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
538
{ "lr",     2, {RR(0x18,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
539
{ "lrdr",   2, {RR(0x25,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
540
{ "lrer",   2, {RR(0x35,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
541
{ "ltdr",   2, {RR(0x22,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
542
{ "lter",   2, {RR(0x32,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
543
{ "ltr",    2, {RR(0x12,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
544
{ "mdr",    2, {RR(0x2c,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
545
{ "mer",    2, {RR(0x3c,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
546
{ "mr",     2, {RR(0x1c,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
547
{ "mvcl",   2, {RR(0x0e,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
548
{ "mxdr",   2, {RR(0x27,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
549
{ "mxr",    2, {RR(0x26,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
550
{ "nr",     2, {RR(0x14,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
551
{ "or",     2, {RR(0x16,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
552
{ "sdr",    2, {RR(0x2b,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
553
{ "ser",    2, {RR(0x3b,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
554
{ "slr",    2, {RR(0x1f,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
555
{ "spm",    2, {RR(0x04,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1} },
556
{ "sr",     2, {RR(0x1b,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
557
{ "sur",    2, {RR(0x3f,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
558
{ "swr",    2, {RR(0x2f,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
559
{ "sxr",    2, {RR(0x37,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
560
{ "xr",     2, {RR(0x17,0,0), 0}, {RR_MASK, 0}, I370,  {RR_R1, RR_R2} },
561
 
562
/* unusual RR formats */
563
{ "svc",    2, {SVC(0x0a,0), 0}, {SVC_MASK, 0}, I370,  {RR_I} },
564
 
565
/* RRE form instructions */
566
{ "adbr",   4, {RRE(0xb31a,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
567
{ "aebr",   4, {RRE(0xb30a,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
568
{ "axbr",   4, {RRE(0xb34a,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
569
{ "bakr",   4, {RRE(0xb240,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
570
{ "bsa",    4, {RRE(0xb25a,0,0),   0}, {RRE_MASK, 0}, IBS,  {RRE_R1, RRE_R2} },
571
{ "bsg",    4, {RRE(0xb258,0,0),   0}, {RRE_MASK, 0}, ISG,  {RRE_R1, RRE_R2} },
572
{ "cdbr",   4, {RRE(0xb319,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
573
{ "cdfbr",  4, {RRE(0xb395,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
574
{ "cdfr",   4, {RRE(0xb3b5,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
575
{ "cebr",   4, {RRE(0xb309,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
576
{ "cefbr",  4, {RRE(0xb394,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
577
{ "cefr",   4, {RRE(0xb3b4,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
578
{ "cksm",   4, {RRE(0xb241,0,0),   0}, {RRE_MASK, 0}, ICK,  {RRE_R1, RRE_R2} },
579
{ "clst",   4, {RRE(0xb25d,0,0),   0}, {RRE_MASK, 0}, ISR,  {RRE_R1, RRE_R2} },
580
{ "cpya",   4, {RRE(0xb24d,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
581
{ "cuse",   4, {RRE(0xb257,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
582
{ "cxbr",   4, {RRE(0xb349,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
583
{ "cxfbr",  4, {RRE(0xb396,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
584
{ "cxfr",   4, {RRE(0xb3b6,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
585
{ "cxr",    4, {RRE(0xb369,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
586
{ "ddbr",   4, {RRE(0xb31d,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
587
{ "debr",   4, {RRE(0xb30d,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
588
{ "dxbr",   4, {RRE(0xb34d,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
589
{ "dxr",    4, {RRE(0xb22d,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
590
{ "ear",    4, {RRE(0xb24f,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
591
{ "efpc",   4, {RRE(0xb38c,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
592
{ "epar",   4, {RRE(0xb226,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1} },
593
{ "ereg",   4, {RRE(0xb249,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
594
{ "esar",   4, {RRE(0xb227,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1} },
595
{ "esta",   4, {RRE(0xb24a,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
596
{ "fidr",   4, {RRE(0xb37f,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
597
{ "fier",   4, {RRE(0xb377,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
598
{ "fixr",   4, {RRE(0xb367,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
599
{ "iac",    4, {RRE(0xb224,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1} },
600
{ "ipm",    4, {RRE(0xb222,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1} },
601
{ "ipte",   4, {RRE(0xb221,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
602
{ "iske",   4, {RRE(0xb229,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
603
{ "ivsk",   4, {RRE(0xb223,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
604
{ "kdbr",   4, {RRE(0xb318,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
605
{ "kebr",   4, {RRE(0xb308,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
606
{ "kxbr",   4, {RRE(0xb348,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
607
{ "lcdbr",  4, {RRE(0xb313,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
608
{ "lcebr",  4, {RRE(0xb303,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
609
{ "lcxbr",  4, {RRE(0xb343,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
610
{ "lcxr",   4, {RRE(0xb363,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
611
{ "lder",   4, {RRE(0xb324,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
612
{ "ldxbr",  4, {RRE(0xb345,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
613
{ "ledbr",  4, {RRE(0xb344,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
614
{ "lexbr",  4, {RRE(0xb346,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
615
{ "lexr",   4, {RRE(0xb366,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
616
{ "lndbr",  4, {RRE(0xb311,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
617
{ "lnebr",  4, {RRE(0xb301,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
618
{ "lnxbr",  4, {RRE(0xb341,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
619
{ "lnxr",   4, {RRE(0xb361,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
620
{ "lpdbr",  4, {RRE(0xb310,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
621
{ "lpebr",  4, {RRE(0xb300,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
622
{ "lpxbr",  4, {RRE(0xb340,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
623
{ "lpxr",   4, {RRE(0xb360,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
624
{ "ltdbr",  4, {RRE(0xb312,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
625
{ "ltebr",  4, {RRE(0xb302,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
626
{ "ltxbr",  4, {RRE(0xb342,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
627
{ "ltxr",   4, {RRE(0xb362,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
628
{ "lura",   4, {RRE(0xb24b,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
629
{ "lxdr",   4, {RRE(0xb325,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
630
{ "lxer",   4, {RRE(0xb326,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
631
{ "lxr",    4, {RRE(0xb365,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
632
{ "lzdr",   4, {RRE(0xb375,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
633
{ "lzer",   4, {RRE(0xb374,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
634
{ "lzxr",   4, {RRE(0xb376,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
635
{ "mdbr",   4, {RRE(0xb31c,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
636
{ "mdebr",  4, {RRE(0xb30c,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
637
{ "meebr",  4, {RRE(0xb317,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
638
{ "meer",   4, {RRE(0xb337,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
639
{ "msr",    4, {RRE(0xb252,0,0),   0}, {RRE_MASK, 0}, IIR,  {RRE_R1, RRE_R2} },
640
{ "msta",   4, {RRE(0xb247,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1} },
641
{ "mvpg",   4, {RRE(0xb254,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
642
{ "mvst",   4, {RRE(0xb255,0,0),   0}, {RRE_MASK, 0}, ISR,  {RRE_R1, RRE_R2} },
643
{ "mxbr",   4, {RRE(0xb34c,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
644
{ "mxdbr",  4, {RRE(0xb307,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
645
{ "palb",   4, {RRE(0xb248,0,0),   0}, {RRE_MASK, 0}, IESA, {0} },
646
{ "prbe",   4, {RRE(0xb22a,0,0),   0}, {RRE_MASK, 0}, I370, {RRE_R1, RRE_R2} },
647
{ "pt",     4, {RRE(0xb228,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
648
{ "rrbe",   4, {RRE(0xb22a,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
649
{ "sar",    4, {RRE(0xb24e,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
650
{ "sdbr",   4, {RRE(0xb31b,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
651
{ "sebr",   4, {RRE(0xb30b,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
652
{ "servc",  4, {RRE(0xb220,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
653
{ "sfpc",   4, {RRE(0xb384,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
654
{ "sqdbr",  4, {RRE(0xb315,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
655
{ "sqdr",   4, {RRE(0xb244,0,0),   0}, {RRE_MASK, 0}, IQR,  {RRE_R1, RRE_R2} },
656
{ "sqebr",  4, {RRE(0xb314,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
657
{ "sqer",   4, {RRE(0xb245,0,0),   0}, {RRE_MASK, 0}, IQR,  {RRE_R1, RRE_R2} },
658
{ "sqxbr",  4, {RRE(0xb316,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
659
{ "sqxr",   4, {RRE(0xb336,0,0),   0}, {RRE_MASK, 0}, IHX,  {RRE_R1, RRE_R2} },
660
{ "srst",   4, {RRE(0xb25e,0,0),   0}, {RRE_MASK, 0}, ISR,  {RRE_R1, RRE_R2} },
661
{ "ssar",   4, {RRE(0xb225,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1} },
662
{ "sske",   4, {RRE(0xb22b,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
663
{ "stura",  4, {RRE(0xb246,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
664
{ "sxbr",   4, {RRE(0xb34b,0,0),   0}, {RRE_MASK, 0}, IBF,  {RRE_R1, RRE_R2} },
665
{ "tar",    4, {RRE(0xb24c,0,0),   0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
666
{ "tb",     4, {RRE(0xb22c,0,0),   0}, {RRE_MASK, 0}, IXA,  {RRE_R1, RRE_R2} },
667
{ "thdr",   4, {RRE(0xb359,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
668
{ "thder",  4, {RRE(0xb359,0,0),   0}, {RRE_MASK, 0}, IFX,  {RRE_R1, RRE_R2} },
669
 
670
/* RRF form instructions */
671
{ "cfdbr",  4, {RRF(0xb399,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
672
{ "cfdr",   4, {RRF(0xb3b9,0,0,0), 0}, {RRF_MASK, 0}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
673
{ "cfebr",  4, {RRF(0xb398,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
674
{ "cfer",   4, {RRF(0xb3b8,0,0,0), 0}, {RRF_MASK, 0}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
675
{ "cfxbr",  4, {RRF(0xb39a,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
676
{ "cfxr",   4, {RRF(0xb3ba,0,0,0), 0}, {RRF_MASK, 0}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
677
{ "didbr",  4, {RRF(0xb35b,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
678
{ "diebr",  4, {RRF(0xb353,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
679
{ "fidbr",  4, {RRF(0xb35f,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
680
{ "fiebr",  4, {RRF(0xb357,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
681
{ "fixbr",  4, {RRF(0xb347,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
682
{ "madbr",  4, {RRF(0xb31e,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
683
{ "maebr",  4, {RRF(0xb30e,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
684
{ "msdbr",  4, {RRF(0xb31f,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
685
{ "msebr",  4, {RRF(0xb30f,0,0,0), 0}, {RRF_MASK, 0}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
686
{ "tbdr",   4, {RRF(0xb351,0,0,0), 0}, {RRF_MASK, 0}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
687
{ "tbedr",  4, {RRF(0xb350,0,0,0), 0}, {RRF_MASK, 0}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
688
 
689
/* RX form instructions */
690
{ "a",      4, {RX(0x5a,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
691
{ "ad",     4, {RX(0x6a,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
692
{ "ae",     4, {RX(0x7a,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
693
{ "ah",     4, {RX(0x4a,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
694
{ "al",     4, {RX(0x5e,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
695
{ "au",     4, {RX(0x7e,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
696
{ "aw",     4, {RX(0x6e,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
697
{ "bal",    4, {RX(0x45,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
698
{ "bas",    4, {RX(0x4d,0,0,0,0),  0}, {RX_MASK,  0}, IXA,  {RX_R1, RX_D2, RX_X2, RX_B2} },
699
{ "bc",     4, {RX(0x47,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
700
{ "bct",    4, {RX(0x46,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
701
{ "c",      4, {RX(0x59,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
702
{ "cd",     4, {RX(0x69,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
703
{ "ce",     4, {RX(0x79,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
704
{ "ch",     4, {RX(0x49,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
705
{ "cl",     4, {RX(0x55,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
706
{ "cvb",    4, {RX(0x4f,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
707
{ "cvd",    4, {RX(0x4e,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
708
{ "d",      4, {RX(0x5d,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
709
{ "dd",     4, {RX(0x6d,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
710
{ "de",     4, {RX(0x7d,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
711
{ "ex",     4, {RX(0x44,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
712
{ "ic",     4, {RX(0x43,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
713
{ "l",      4, {RX(0x58,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
714
{ "la",     4, {RX(0x41,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
715
{ "lae",    4, {RX(0x51,0,0,0,0),  0}, {RX_MASK,  0}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
716
{ "ld",     4, {RX(0x68,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
717
{ "le",     4, {RX(0x78,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
718
{ "lh",     4, {RX(0x48,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
719
{ "lra",    4, {RX(0xb1,0,0,0,0),  0}, {RX_MASK,  0}, IXA,  {RX_R1, RX_D2, RX_X2, RX_B2} },
720
{ "m",      4, {RX(0x5c,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
721
{ "md",     4, {RX(0x6c,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
722
{ "me",     4, {RX(0x7c,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
723
{ "mh",     4, {RX(0x4c,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
724
{ "ms",     4, {RX(0x71,0,0,0,0),  0}, {RX_MASK,  0}, IIR,  {RX_R1, RX_D2, RX_X2, RX_B2} },
725
{ "mxd",    4, {RX(0x67,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
726
{ "n",      4, {RX(0x54,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
727
{ "o",      4, {RX(0x56,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
728
{ "s",      4, {RX(0x5b,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
729
{ "sd",     4, {RX(0x6b,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
730
{ "se",     4, {RX(0x7b,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
731
{ "sh",     4, {RX(0x4b,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
732
{ "sl",     4, {RX(0x5f,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
733
{ "st",     4, {RX(0x50,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
734
{ "stc",    4, {RX(0x42,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
735
{ "std",    4, {RX(0x60,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
736
{ "ste",    4, {RX(0x70,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
737
{ "sth",    4, {RX(0x40,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
738
{ "su",     4, {RX(0x7f,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
739
{ "sw",     4, {RX(0x6f,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
740
{ "x",      4, {RX(0x57,0,0,0,0),  0}, {RX_MASK,  0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
741
 
742
/* RXE form instructions */
743
{ "adb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x1a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
744
{ "aeb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x0a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
745
{ "cdb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x19)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
746
{ "ceb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x09)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
747
{ "ddb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x1d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
748
{ "deb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x0d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
749
{ "kdb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x18)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
750
{ "keb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x08)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
751
{ "lde",    6, {RXEH(0xed,0,0,0,0), RXEL(0x24)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
752
{ "ldeb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x04)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
753
{ "lxd",    6, {RXEH(0xed,0,0,0,0), RXEL(0x25)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
754
{ "lxdb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x05)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
755
{ "lxe",    6, {RXEH(0xed,0,0,0,0), RXEL(0x26)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
756
{ "lxeb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x06)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
757
{ "mdb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x1c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
758
{ "mdeb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x0c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
759
{ "mee",    6, {RXEH(0xed,0,0,0,0), RXEL(0x37)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
760
{ "meeb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x17)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
761
{ "mxdb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x07)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
762
{ "sqd",    6, {RXEH(0xed,0,0,0,0), RXEL(0x35)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
763
{ "sqdb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x15)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
764
{ "sqe",    6, {RXEH(0xed,0,0,0,0), RXEL(0x34)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
765
{ "sqeb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x14)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
766
{ "sdb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x1b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
767
{ "seb",    6, {RXEH(0xed,0,0,0,0), RXEL(0x0b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
768
{ "tcdb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x11)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
769
{ "tceb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x10)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
770
{ "tcxb",   6, {RXEH(0xed,0,0,0,0), RXEL(0x12)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
771
 
772
/* RXF form instructions */
773
{ "madb",   6, {RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
774
{ "maeb",   6, {RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
775
{ "msdb",   6, {RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
776
{ "mseb",   6, {RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
777
 
778
/* RS form instructions */
779
{ "bxh",    4, {RS(0x86,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
780
{ "bxle",   4, {RS(0x87,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
781
{ "cds",    4, {RS(0xbb,0,0,0,0), 0}, {RS_MASK, 0}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
782
{ "clcle",  4, {RS(0xa9,0,0,0,0), 0}, {RS_MASK, 0}, ICM,  {RX_R1, RS_R3, RS_D2, RS_B2} },
783
{ "clm",    4, {RS(0xbd,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
784
{ "cs",     4, {RS(0xba,0,0,0,0), 0}, {RS_MASK, 0}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
785
{ "icm",    4, {RS(0xbf,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
786
{ "lam",    4, {RS(0x9a,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
787
{ "lctl",   4, {RS(0xb7,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
788
{ "lm",     4, {RS(0x98,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
789
{ "mvcle",  4, {RS(0xa8,0,0,0,0), 0}, {RS_MASK, 0}, ICM,  {RX_R1, RS_R3, RS_D2, RS_B2} },
790
{ "sigp",   4, {RS(0xae,0,0,0,0), 0}, {RS_MASK, 0}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
791
{ "stam",   4, {RS(0x9b,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
792
{ "stcm",   4, {RS(0xbe,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
793
{ "stctl",  4, {RS(0xb6,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
794
{ "stm",    4, {RS(0x90,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
795
{ "trace",  4, {RS(0x99,0,0,0,0), 0}, {RS_MASK, 0}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
796
 
797
/* RS form instructions with blank R3 and optional B2 (shift left/right) */
798
{ "sla",    4, {RS(0x8b,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
799
{ "slda",   4, {RS(0x8f,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
800
{ "sldl",   4, {RS(0x8d,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
801
{ "sll",    4, {RS(0x89,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
802
{ "sra",    4, {RS(0x8a,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
803
{ "srda",   4, {RS(0x8e,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
804
{ "srdl",   4, {RS(0x8c,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
805
{ "srl",    4, {RS(0x88,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
806
 
807
/* RSI form instructions */
808
{ "brxh",   4, {RSI(0x84,0,0,0),  0}, {RSI_MASK, 0}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
809
{ "brxle",  4, {RSI(0x85,0,0,0),  0}, {RSI_MASK, 0}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
810
 
811
/* RI form instructions */
812
{ "ahi",    4, {RI(0xa7a,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
813
{ "bras",   4, {RI(0xa75,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
814
{ "brc",    4, {RI(0xa74,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
815
{ "brct",   4, {RI(0xa76,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
816
{ "chi",    4, {RI(0xa7e,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
817
{ "lhi",    4, {RI(0xa78,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
818
{ "mhi",    4, {RI(0xa7c,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
819
{ "tmh",    4, {RI(0xa70,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
820
{ "tml",    4, {RI(0xa71,0,0),    0}, {RI_MASK,  0}, IIR,  {RI_R1, RI_I2} },
821
 
822
/* SI form instructions */
823
{ "cli",    4, {SI(0x95,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
824
{ "mc",     4, {SI(0xaf,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
825
{ "mvi",    4, {SI(0x92,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
826
{ "ni",     4, {SI(0x94,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
827
{ "oi",     4, {SI(0x96,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
828
{ "stnsm",  4, {SI(0xac,0,0,0),   0}, {SI_MASK,  0}, IXA,  {SI_D1, SI_B1, SI_I2} },
829
{ "stosm",  4, {SI(0xad,0,0,0),   0}, {SI_MASK,  0}, IXA,  {SI_D1, SI_B1, SI_I2} },
830
{ "tm",     4, {SI(0x91,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
831
{ "xi",     4, {SI(0x97,0,0,0),   0}, {SI_MASK,  0}, I370, {SI_D1, SI_B1, SI_I2} },
832
 
833
/* S form instructions */
834
{ "cfc",    4, {S(0xb21a,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
835
{ "csch",   4, {S(0xb230,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
836
{ "hsch",   4, {S(0xb231,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
837
{ "ipk",    4, {S(0xb20b,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
838
{ "lfpc",   4, {S(0xb29d,0,0),    0}, {S_MASK,      0}, IBF,  {S_D2, S_B2} },
839
{ "lpsw",   4, {S(0x8200,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
840
{ "msch",   4, {S(0xb232,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
841
{ "pc",     4, {S(0xb218,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
842
{ "pcf",    4, {S(0xb218,0,0),    0}, {S_MASK,      0}, IPC,  {S_D2, S_B2} },
843
{ "ptlb",   4, {S(0xb20d,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
844
{ "rchp",   4, {S(0xb23b,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
845
{ "rp",     4, {S(0xb277,0,0),    0}, {S_MASK,      0}, IRP,  {0} },
846
{ "rsch",   4, {S(0xb238,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
847
{ "sac",    4, {S(0xb219,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
848
{ "sacf",   4, {S(0xb279,0,0),    0}, {S_MASK,      0}, ISA,  {S_D2, S_B2} },
849
{ "sal",    4, {S(0xb237,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
850
{ "schm",   4, {S(0xb23c,0,0),    0}, {S_MASK,      0}, IXA,  {0} },
851
{ "sck",    4, {S(0xb204,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
852
{ "sckc",   4, {S(0xb206,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
853
{ "spka",   4, {S(0xb20a,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
854
{ "spt",    4, {S(0xb208,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
855
{ "spx",    4, {S(0xb210,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
856
{ "srnm",   4, {S(0xb299,0,0),    0}, {S_MASK,      0}, IBF,  {S_D2, S_B2} },
857
{ "ssch",   4, {S(0xb233,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
858
{ "ssm",    4, {S(0x8000,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
859
{ "stap",   4, {S(0xb212,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
860
{ "stck",   4, {S(0xb205,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
861
{ "stckc",  4, {S(0xb207,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
862
{ "stcps",  4, {S(0xb23a,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
863
{ "stcrw",  4, {S(0xb239,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
864
{ "stfpc",  4, {S(0xb29c,0,0),    0}, {S_MASK,      0}, IBF,  {S_D2, S_B2} },
865
{ "stidp",  4, {S(0xb202,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
866
{ "stpt",   4, {S(0xb209,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
867
{ "stpx",   4, {S(0xb211,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
868
{ "stsch",  4, {S(0xb234,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
869
{ "tpi",    4, {S(0xb236,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
870
{ "trap4",  4, {S(0xb2ff,0,0),    0}, {S_MASK,      0}, ITR,  {S_D2, S_B2} },
871
{ "ts",     4, {S(0x9300,0,0),    0}, {S_MASK,      0}, I370, {S_D2, S_B2} },
872
{ "tsch",   4, {S(0xb235,0,0),    0}, {S_MASK,      0}, IXA,  {S_D2, S_B2} },
873
 
874
/* SS form instructions */
875
{ "ap",     6, {SSH(0xfa,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
876
{ "clc",    6, {SSH(0xd5,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
877
{ "cp",     6, {SSH(0xf9,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
878
{ "dp",     6, {SSH(0xfd,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
879
{ "ed",     6, {SSH(0xde,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
880
{ "edmk",   6, {SSH(0xdf,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
881
{ "mvc",    6, {SSH(0xd2,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
882
{ "mvcin",  6, {SSH(0xe8,0,0,0),  0}, {SS_MASK,  0}, IMI,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
883
{ "mvck",   6, {SSH(0xd9,0,0,0),  0}, {SS_MASK,  0}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
884
{ "mvcp",   6, {SSH(0xda,0,0,0),  0}, {SS_MASK,  0}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
885
{ "mvcs",   6, {SSH(0xdb,0,0,0),  0}, {SS_MASK,  0}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
886
{ "mvn",    6, {SSH(0xd1,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
887
{ "mvo",    6, {SSH(0xf1,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
888
{ "mvz",    6, {SSH(0xd3,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
889
{ "nc",     6, {SSH(0xd4,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
890
{ "oc",     6, {SSH(0xd6,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
891
{ "pack",   6, {SSH(0xf2,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
892
{ "plo",    6, {SSH(0xee,0,0,0),  0}, {SS_MASK,  0}, IPL,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
893
{ "sp",     6, {SSH(0xfb,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
894
{ "srp",    6, {SSH(0xf0,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
895
{ "tr",     6, {SSH(0xdc,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
896
{ "trt",    6, {SSH(0xdd,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
897
{ "unpk",   6, {SSH(0xf3,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
898
{ "xc",     6, {SSH(0xd7,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
899
{ "zap",    6, {SSH(0xf8,0,0,0),  0}, {SS_MASK,  0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
900
 
901
/* SSE form instructions */
902
{ "lasp",   6, {SSEH(0xe500,0,0), 0}, {SSE_MASK, 0}, IXA,  {SS_D1, SS_B1, SS_D2, SS_B2} },
903
{ "mvcdk",  6, {SSEH(0xe50f,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
904
{ "mvcsk",  6, {SSEH(0xe50e,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
905
{ "tprot",  6, {SSEH(0xe501,0,0), 0}, {SSE_MASK, 0}, IXA,  {SS_D1, SS_B1, SS_D2, SS_B2} },
906
 
907
/* */
908
};
909
 
910
const int i370_num_opcodes =
911
  sizeof (i370_opcodes) / sizeof (i370_opcodes[0]);
912
 
913
/* The macro table.  This is only used by the assembler.  */
914
 
915
const struct i370_macro i370_macros[] = {
916
{ "b",     1,   I370,   "bc  15,%0" },
917
{ "br",    1,   I370,   "bcr 15,%0" },
918
 
919
{ "nop",   1,   I370,   "bc  0,%0" },
920
{ "nopr",  1,   I370,   "bcr 0,%0" },
921
 
922
{ "bh",    1,   I370,   "bc  2,%0" },
923
{ "bhr",   1,   I370,   "bcr 2,%0" },
924
{ "bl",    1,   I370,   "bc  4,%0" },
925
{ "blr",   1,   I370,   "bcr 4,%0" },
926
{ "be",    1,   I370,   "bc  8,%0" },
927
{ "ber",   1,   I370,   "bcr 8,%0" },
928
 
929
{ "bnh",    1,   I370,  "bc  13,%0" },
930
{ "bnhr",   1,   I370,  "bcr 13,%0" },
931
{ "bnl",    1,   I370,  "bc  11,%0" },
932
{ "bnlr",   1,   I370,  "bcr 11,%0" },
933
{ "bne",    1,   I370,  "bc  7,%0" },
934
{ "bner",   1,   I370,  "bcr 7,%0" },
935
 
936
{ "bp",    1,   I370,   "bc  2,%0" },
937
{ "bpr",   1,   I370,   "bcr 2,%0" },
938
{ "bm",    1,   I370,   "bc  4,%0" },
939
{ "bmr",   1,   I370,   "bcr 4,%0" },
940
{ "bz",    1,   I370,   "bc  8,%0" },
941
{ "bzr",   1,   I370,   "bcr 8,%0" },
942
{ "bo",    1,   I370,   "bc  1,%0" },
943
{ "bor",   1,   I370,   "bcr 1,%0" },
944
 
945
{ "bnp",    1,   I370,  "bc  13,%0" },
946
{ "bnpr",   1,   I370,  "bcr 13,%0" },
947
{ "bnm",    1,   I370,  "bc  11,%0" },
948
{ "bnmr",   1,   I370,  "bcr 11,%0" },
949
{ "bnz",    1,   I370,  "bc  7,%0" },
950
{ "bnzr",   1,   I370,  "bcr 7,%0" },
951
{ "bno",    1,   I370,  "bc  14,%0" },
952
{ "bnor",   1,   I370,  "bcr 14,%0" },
953
 
954
{ "sync",   0,   I370,   "bcr 15,0" },
955
 
956
};
957
 
958
const int i370_num_macros =
959
  sizeof (i370_macros) / sizeof (i370_macros[0]);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.