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[/] [or1k/] [trunk/] [gdb-5.0/] [opcodes/] [sparc-dis.c] - Blame information for rev 1765

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1 106 markom
/* Print SPARC instructions.
2
   Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
3
 
4
This program is free software; you can redistribute it and/or modify
5
it under the terms of the GNU General Public License as published by
6
the Free Software Foundation; either version 2 of the License, or
7
(at your option) any later version.
8
 
9
This program is distributed in the hope that it will be useful,
10
but WITHOUT ANY WARRANTY; without even the implied warranty of
11
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
GNU General Public License for more details.
13
 
14
You should have received a copy of the GNU General Public License
15
along with this program; if not, write to the Free Software
16
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
17
 
18
#include <stdio.h>
19
 
20
#include "ansidecl.h"
21
#include "sysdep.h"
22
#include "opcode/sparc.h"
23
#include "dis-asm.h"
24
#include "libiberty.h"
25
#include "opintl.h"
26
 
27
/* Bitmask of v9 architectures.  */
28
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
29
                 | (1 << SPARC_OPCODE_ARCH_V9A))
30
/* 1 if INSN is for v9 only.  */
31
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
32
/* 1 if INSN is for v9.  */
33
#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
34
 
35
/* The sorted opcode table.  */
36
static const struct sparc_opcode **sorted_opcodes;
37
 
38
/* For faster lookup, after insns are sorted they are hashed.  */
39
/* ??? I think there is room for even more improvement.  */
40
 
41
#define HASH_SIZE 256
42
/* It is important that we only look at insn code bits as that is how the
43
   opcode table is hashed.  OPCODE_BITS is a table of valid bits for each
44
   of the main types (0,1,2,3).  */
45
static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
46
#define HASH_INSN(INSN) \
47
  ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
48
struct opcode_hash {
49
  struct opcode_hash *next;
50
  const struct sparc_opcode *opcode;
51
};
52
static struct opcode_hash *opcode_hash_table[HASH_SIZE];
53
 
54
static void build_hash_table
55
  PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
56
static int is_delayed_branch PARAMS ((unsigned long));
57
static int compare_opcodes PARAMS ((const PTR, const PTR));
58
static int compute_arch_mask PARAMS ((unsigned long));
59
 
60
/* Sign-extend a value which is N bits long.  */
61
#define SEX(value, bits) \
62
        ((((int)(value)) << ((8 * sizeof (int)) - bits))        \
63
                         >> ((8 * sizeof (int)) - bits) )
64
 
65
static  char *reg_names[] =
66
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
67
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
68
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
69
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
70
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
71
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
72
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
73
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
74
  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
75
  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
76
  "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
77
  "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
78
/* psr, wim, tbr, fpsr, cpsr are v8 only.  */
79
  "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
80
};
81
 
82
#define freg_names      (&reg_names[4 * 8])
83
 
84
/* These are ordered according to there register number in
85
   rdpr and wrpr insns.  */
86
static char *v9_priv_reg_names[] =
87
{
88
  "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
89
  "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
90
  "wstate", "fq"
91
  /* "ver" - special cased */
92
};
93
 
94
/* These are ordered according to there register number in
95
   rd and wr insns (-16).  */
96
static char *v9a_asr_reg_names[] =
97
{
98
  "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
99
  "softint", "tick_cmpr"
100
};
101
 
102
/* Macros used to extract instruction fields.  Not all fields have
103
   macros defined here, only those which are actually used.  */
104
 
105
#define X_RD(i) (((i) >> 25) & 0x1f)
106
#define X_RS1(i) (((i) >> 14) & 0x1f)
107
#define X_LDST_I(i) (((i) >> 13) & 1)
108
#define X_ASI(i) (((i) >> 5) & 0xff)
109
#define X_RS2(i) (((i) >> 0) & 0x1f)
110
#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
111
#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
112
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
113
#define X_IMM22(i) X_DISP22 (i)
114
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
115
 
116
/* These are for v9.  */
117
#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
118
#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
119
#define X_MEMBAR(i) ((i) & 0x7f)
120
 
121
/* Here is the union which was used to extract instruction fields
122
   before the shift and mask macros were written.
123
 
124
   union sparc_insn
125
     {
126
       unsigned long int code;
127
       struct
128
         {
129
           unsigned int anop:2;
130
           #define      op      ldst.anop
131
           unsigned int anrd:5;
132
           #define      rd      ldst.anrd
133
           unsigned int op3:6;
134
           unsigned int anrs1:5;
135
           #define      rs1     ldst.anrs1
136
           unsigned int i:1;
137
           unsigned int anasi:8;
138
           #define      asi     ldst.anasi
139
           unsigned int anrs2:5;
140
           #define      rs2     ldst.anrs2
141
           #define      shcnt   rs2
142
         } ldst;
143
       struct
144
         {
145
           unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
146
           unsigned int IMM13:13;
147
           #define      imm13   IMM13.IMM13
148
         } IMM13;
149
       struct
150
         {
151
           unsigned int anop:2;
152
           unsigned int a:1;
153
           unsigned int cond:4;
154
           unsigned int op2:3;
155
           unsigned int DISP22:22;
156
           #define      disp22  branch.DISP22
157
           #define      imm22   disp22
158
         } branch;
159
       struct
160
         {
161
           unsigned int anop:2;
162
           unsigned int a:1;
163
           unsigned int z:1;
164
           unsigned int rcond:3;
165
           unsigned int op2:3;
166
           unsigned int DISP16HI:2;
167
           unsigned int p:1;
168
           unsigned int _rs1:5;
169
           unsigned int DISP16LO:14;
170
         } branch16;
171
       struct
172
         {
173
           unsigned int anop:2;
174
           unsigned int adisp30:30;
175
           #define      disp30  call.adisp30
176
         } call;
177
     };
178
 
179
   */
180
 
181
/* Nonzero if INSN is the opcode for a delayed branch.  */
182
static int
183
is_delayed_branch (insn)
184
     unsigned long insn;
185
{
186
  struct opcode_hash *op;
187
 
188
  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
189
    {
190
      CONST struct sparc_opcode *opcode = op->opcode;
191
      if ((opcode->match & insn) == opcode->match
192
          && (opcode->lose & insn) == 0)
193
        return (opcode->flags & F_DELAYED);
194
    }
195
  return 0;
196
}
197
 
198
/* extern void qsort (); */
199
 
200
/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
201
   to compare_opcodes.  */
202
static unsigned int current_arch_mask;
203
 
204
/* Print one instruction from MEMADDR on INFO->STREAM.
205
 
206
   We suffix the instruction with a comment that gives the absolute
207
   address involved, as well as its symbolic form, if the instruction
208
   is preceded by a findable `sethi' and it either adds an immediate
209
   displacement to that register, or it is an `add' or `or' instruction
210
   on that register.  */
211
 
212
int
213
print_insn_sparc (memaddr, info)
214
     bfd_vma memaddr;
215
     disassemble_info *info;
216
{
217
  FILE *stream = info->stream;
218
  bfd_byte buffer[4];
219
  unsigned long insn;
220
  register struct opcode_hash *op;
221
  /* Nonzero of opcode table has been initialized.  */
222
  static int opcodes_initialized = 0;
223
  /* bfd mach number of last call.  */
224
  static unsigned long current_mach = 0;
225
  bfd_vma (*getword) PARAMS ((const unsigned char *));
226
 
227
  if (!opcodes_initialized
228
      || info->mach != current_mach)
229
    {
230
      int i;
231
 
232
      current_arch_mask = compute_arch_mask (info->mach);
233
 
234
      if (!opcodes_initialized)
235
        sorted_opcodes = (const struct sparc_opcode **)
236
          xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
237
      /* Reset the sorted table so we can resort it.  */
238
      for (i = 0; i < sparc_num_opcodes; ++i)
239
        sorted_opcodes[i] = &sparc_opcodes[i];
240
      qsort ((char *) sorted_opcodes, sparc_num_opcodes,
241
             sizeof (sorted_opcodes[0]), compare_opcodes);
242
 
243
      build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
244
      current_mach = info->mach;
245
      opcodes_initialized = 1;
246
    }
247
 
248
  {
249
    int status =
250
      (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
251
    if (status != 0)
252
      {
253
        (*info->memory_error_func) (status, memaddr, info);
254
        return -1;
255
      }
256
  }
257
 
258
  /* On SPARClite variants such as DANlite (sparc86x), instructions
259
     are always big-endian even when the machine is in little-endian mode. */
260
  if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
261
    getword = bfd_getb32;
262
  else
263
    getword = bfd_getl32;
264
 
265
  insn = getword (buffer);
266
 
267
  info->insn_info_valid = 1;                    /* We do return this info */
268
  info->insn_type = dis_nonbranch;              /* Assume non branch insn */
269
  info->branch_delay_insns = 0;                  /* Assume no delay */
270
  info->target = 0;                              /* Assume no target known */
271
 
272
  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
273
    {
274
      CONST struct sparc_opcode *opcode = op->opcode;
275
 
276
      /* If the insn isn't supported by the current architecture, skip it.  */
277
      if (! (opcode->architecture & current_arch_mask))
278
        continue;
279
 
280
      if ((opcode->match & insn) == opcode->match
281
          && (opcode->lose & insn) == 0)
282
        {
283
          /* Nonzero means that we have found an instruction which has
284
             the effect of adding or or'ing the imm13 field to rs1.  */
285
          int imm_added_to_rs1 = 0;
286
          int imm_ored_to_rs1 = 0;
287
 
288
          /* Nonzero means that we have found a plus sign in the args
289
             field of the opcode table.  */
290
          int found_plus = 0;
291
 
292
          /* Nonzero means we have an annulled branch.  */
293
          int is_annulled = 0;
294
 
295
          /* Do we have an `add' or `or' instruction combining an
296
             immediate with rs1?  */
297
          if (opcode->match == 0x80102000) /* or */
298
            imm_ored_to_rs1 = 1;
299
          if (opcode->match == 0x80002000) /* add */
300
            imm_added_to_rs1 = 1;
301
 
302
          if (X_RS1 (insn) != X_RD (insn)
303
              && strchr (opcode->args, 'r') != 0)
304
              /* Can't do simple format if source and dest are different.  */
305
              continue;
306
          if (X_RS2 (insn) != X_RD (insn)
307
              && strchr (opcode->args, 'O') != 0)
308
              /* Can't do simple format if source and dest are different.  */
309
              continue;
310
 
311
          (*info->fprintf_func) (stream, opcode->name);
312
 
313
          {
314
            register CONST char *s;
315
 
316
            if (opcode->args[0] != ',')
317
              (*info->fprintf_func) (stream, " ");
318
            for (s = opcode->args; *s != '\0'; ++s)
319
              {
320
                while (*s == ',')
321
                  {
322
                    (*info->fprintf_func) (stream, ",");
323
                    ++s;
324
                    switch (*s) {
325
                    case 'a':
326
                      (*info->fprintf_func) (stream, "a");
327
                      is_annulled = 1;
328
                      ++s;
329
                      continue;
330
                    case 'N':
331
                      (*info->fprintf_func) (stream, "pn");
332
                      ++s;
333
                      continue;
334
 
335
                    case 'T':
336
                      (*info->fprintf_func) (stream, "pt");
337
                      ++s;
338
                      continue;
339
 
340
                    default:
341
                      break;
342
                    }           /* switch on arg */
343
                  }             /* while there are comma started args */
344
 
345
                (*info->fprintf_func) (stream, " ");
346
 
347
                switch (*s)
348
                  {
349
                  case '+':
350
                    found_plus = 1;
351
 
352
                    /* note fall-through */
353
                  default:
354
                    (*info->fprintf_func) (stream, "%c", *s);
355
                    break;
356
 
357
                  case '#':
358
                    (*info->fprintf_func) (stream, "0");
359
                    break;
360
 
361
#define reg(n)  (*info->fprintf_func) (stream, "%%%s", reg_names[n])
362
                  case '1':
363
                  case 'r':
364
                    reg (X_RS1 (insn));
365
                    break;
366
 
367
                  case '2':
368
                  case 'O':
369
                    reg (X_RS2 (insn));
370
                    break;
371
 
372
                  case 'd':
373
                    reg (X_RD (insn));
374
                    break;
375
#undef  reg
376
 
377
#define freg(n)         (*info->fprintf_func) (stream, "%%%s", freg_names[n])
378
#define fregx(n)        (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
379
                  case 'e':
380
                    freg (X_RS1 (insn));
381
                    break;
382
                  case 'v':     /* double/even */
383
                  case 'V':     /* quad/multiple of 4 */
384
                    fregx (X_RS1 (insn));
385
                    break;
386
 
387
                  case 'f':
388
                    freg (X_RS2 (insn));
389
                    break;
390
                  case 'B':     /* double/even */
391
                  case 'R':     /* quad/multiple of 4 */
392
                    fregx (X_RS2 (insn));
393
                    break;
394
 
395
                  case 'g':
396
                    freg (X_RD (insn));
397
                    break;
398
                  case 'H':     /* double/even */
399
                  case 'J':     /* quad/multiple of 4 */
400
                    fregx (X_RD (insn));
401
                    break;
402
#undef  freg
403
#undef  fregx
404
 
405
#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
406
                  case 'b':
407
                    creg (X_RS1 (insn));
408
                    break;
409
 
410
                  case 'c':
411
                    creg (X_RS2 (insn));
412
                    break;
413
 
414
                  case 'D':
415
                    creg (X_RD (insn));
416
                    break;
417
#undef  creg
418
 
419
                  case 'h':
420
                    (*info->fprintf_func) (stream, "%%hi(%#x)",
421
                                           (0xFFFFFFFF
422
                                            & ((int) X_IMM22 (insn) << 10)));
423
                    break;
424
 
425
                  case 'i':     /* 13 bit immediate */
426
                  case 'I':     /* 11 bit immediate */
427
                  case 'j':     /* 10 bit immediate */
428
                    {
429
                      int imm;
430
 
431
                      if (*s == 'i')
432
                        imm = X_SIMM (insn, 13);
433
                      else if (*s == 'I')
434
                        imm = X_SIMM (insn, 11);
435
                      else
436
                        imm = X_SIMM (insn, 10);
437
 
438
                      /* Check to see whether we have a 1+i, and take
439
                         note of that fact.
440
 
441
                         Note: because of the way we sort the table,
442
                         we will be matching 1+i rather than i+1,
443
                         so it is OK to assume that i is after +,
444
                         not before it.  */
445
                      if (found_plus)
446
                        imm_added_to_rs1 = 1;
447
 
448
                      if (imm <= 9)
449
                        (*info->fprintf_func) (stream, "%d", imm);
450
                      else
451
                        (*info->fprintf_func) (stream, "%#x", imm);
452
                    }
453
                    break;
454
 
455
                  case 'X':     /* 5 bit unsigned immediate */
456
                  case 'Y':     /* 6 bit unsigned immediate */
457
                    {
458
                      int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
459
 
460
                      if (imm <= 9)
461
                        (info->fprintf_func) (stream, "%d", imm);
462
                      else
463
                        (info->fprintf_func) (stream, "%#x", (unsigned) imm);
464
                    }
465
                    break;
466
 
467
                  case 'K':
468
                    {
469
                      int mask = X_MEMBAR (insn);
470
                      int bit = 0x40, printed_one = 0;
471
                      const char *name;
472
 
473
                      if (mask == 0)
474
                        (info->fprintf_func) (stream, "0");
475
                      else
476
                        while (bit)
477
                          {
478
                            if (mask & bit)
479
                              {
480
                                if (printed_one)
481
                                  (info->fprintf_func) (stream, "|");
482
                                name = sparc_decode_membar (bit);
483
                                (info->fprintf_func) (stream, "%s", name);
484
                                printed_one = 1;
485
                              }
486
                            bit >>= 1;
487
                          }
488
                      break;
489
                    }
490
 
491
                  case 'k':
492
                    info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
493
                    (*info->print_address_func) (info->target, info);
494
                    break;
495
 
496
                  case 'G':
497
                    info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
498
                    (*info->print_address_func) (info->target, info);
499
                    break;
500
 
501
                  case '6':
502
                  case '7':
503
                  case '8':
504
                  case '9':
505
                    (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
506
                    break;
507
 
508
                  case 'z':
509
                    (*info->fprintf_func) (stream, "%%icc");
510
                    break;
511
 
512
                  case 'Z':
513
                    (*info->fprintf_func) (stream, "%%xcc");
514
                    break;
515
 
516
                  case 'E':
517
                    (*info->fprintf_func) (stream, "%%ccr");
518
                    break;
519
 
520
                  case 's':
521
                    (*info->fprintf_func) (stream, "%%fprs");
522
                    break;
523
 
524
                  case 'o':
525
                    (*info->fprintf_func) (stream, "%%asi");
526
                    break;
527
 
528
                  case 'W':
529
                    (*info->fprintf_func) (stream, "%%tick");
530
                    break;
531
 
532
                  case 'P':
533
                    (*info->fprintf_func) (stream, "%%pc");
534
                    break;
535
 
536
                  case '?':
537
                    if (X_RS1 (insn) == 31)
538
                      (*info->fprintf_func) (stream, "%%ver");
539
                    else if ((unsigned) X_RS1 (insn) < 16)
540
                      (*info->fprintf_func) (stream, "%%%s",
541
                                             v9_priv_reg_names[X_RS1 (insn)]);
542
                    else
543
                      (*info->fprintf_func) (stream, "%%reserved");
544
                    break;
545
 
546
                  case '!':
547
                    if ((unsigned) X_RD (insn) < 15)
548
                      (*info->fprintf_func) (stream, "%%%s",
549
                                             v9_priv_reg_names[X_RD (insn)]);
550
                    else
551
                      (*info->fprintf_func) (stream, "%%reserved");
552
                    break;
553
 
554
                  case '/':
555
                    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23)
556
                      (*info->fprintf_func) (stream, "%%reserved");
557
                    else
558
                      (*info->fprintf_func) (stream, "%%%s",
559
                                             v9a_asr_reg_names[X_RS1 (insn)-16]);
560
                    break;
561
 
562
                  case '_':
563
                    if (X_RD (insn) < 16 || X_RD (insn) > 23)
564
                      (*info->fprintf_func) (stream, "%%reserved");
565
                    else
566
                      (*info->fprintf_func) (stream, "%%%s",
567
                                             v9a_asr_reg_names[X_RD (insn)-16]);
568
                    break;
569
 
570
                  case '*':
571
                    {
572
                      const char *name = sparc_decode_prefetch (X_RD (insn));
573
 
574
                      if (name)
575
                        (*info->fprintf_func) (stream, "%s", name);
576
                      else
577
                        (*info->fprintf_func) (stream, "%d", X_RD (insn));
578
                      break;
579
                    }
580
 
581
                  case 'M':
582
                    (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
583
                    break;
584
 
585
                  case 'm':
586
                    (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
587
                    break;
588
 
589
                  case 'L':
590
                    info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
591
                    (*info->print_address_func) (info->target, info);
592
                    break;
593
 
594
                  case 'n':
595
                    (*info->fprintf_func)
596
                      (stream, "%#x", SEX (X_DISP22 (insn), 22));
597
                    break;
598
 
599
                  case 'l':
600
                    info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
601
                    (*info->print_address_func) (info->target, info);
602
                    break;
603
 
604
                  case 'A':
605
                    {
606
                      const char *name = sparc_decode_asi (X_ASI (insn));
607
 
608
                      if (name)
609
                        (*info->fprintf_func) (stream, "%s", name);
610
                      else
611
                        (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
612
                      break;
613
                    }
614
 
615
                  case 'C':
616
                    (*info->fprintf_func) (stream, "%%csr");
617
                    break;
618
 
619
                  case 'F':
620
                    (*info->fprintf_func) (stream, "%%fsr");
621
                    break;
622
 
623
                  case 'p':
624
                    (*info->fprintf_func) (stream, "%%psr");
625
                    break;
626
 
627
                  case 'q':
628
                    (*info->fprintf_func) (stream, "%%fq");
629
                    break;
630
 
631
                  case 'Q':
632
                    (*info->fprintf_func) (stream, "%%cq");
633
                    break;
634
 
635
                  case 't':
636
                    (*info->fprintf_func) (stream, "%%tbr");
637
                    break;
638
 
639
                  case 'w':
640
                    (*info->fprintf_func) (stream, "%%wim");
641
                    break;
642
 
643
                  case 'x':
644
                    (*info->fprintf_func) (stream, "%d",
645
                                           ((X_LDST_I (insn) << 8)
646
                                            + X_ASI (insn)));
647
                    break;
648
 
649
                  case 'y':
650
                    (*info->fprintf_func) (stream, "%%y");
651
                    break;
652
 
653
                  case 'u':
654
                  case 'U':
655
                    {
656
                      int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
657
                      const char *name = sparc_decode_sparclet_cpreg (val);
658
 
659
                      if (name)
660
                        (*info->fprintf_func) (stream, "%s", name);
661
                      else
662
                        (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
663
                      break;
664
                    }
665
                  }
666
              }
667
          }
668
 
669
          /* If we are adding or or'ing something to rs1, then
670
             check to see whether the previous instruction was
671
             a sethi to the same register as in the sethi.
672
             If so, attempt to print the result of the add or
673
             or (in this context add and or do the same thing)
674
             and its symbolic value.  */
675
          if (imm_ored_to_rs1 || imm_added_to_rs1)
676
            {
677
              unsigned long prev_insn;
678
              int errcode;
679
 
680
              errcode =
681
                (*info->read_memory_func)
682
                  (memaddr - 4, buffer, sizeof (buffer), info);
683
              prev_insn = getword (buffer);
684
 
685
              if (errcode == 0)
686
                {
687
                  /* If it is a delayed branch, we need to look at the
688
                     instruction before the delayed branch.  This handles
689
                     sequences such as
690
 
691
                     sethi %o1, %hi(_foo), %o1
692
                     call _printf
693
                     or %o1, %lo(_foo), %o1
694
                     */
695
 
696
                  if (is_delayed_branch (prev_insn))
697
                    {
698
                      errcode = (*info->read_memory_func)
699
                        (memaddr - 8, buffer, sizeof (buffer), info);
700
                      prev_insn = getword (buffer);
701
                    }
702
                }
703
 
704
              /* If there was a problem reading memory, then assume
705
                 the previous instruction was not sethi.  */
706
              if (errcode == 0)
707
                {
708
                  /* Is it sethi to the same register?  */
709
                  if ((prev_insn & 0xc1c00000) == 0x01000000
710
                      && X_RD (prev_insn) == X_RS1 (insn))
711
                    {
712
                      (*info->fprintf_func) (stream, "\t! ");
713
                      info->target =
714
                        (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10);
715
                      if (imm_added_to_rs1)
716
                        info->target += X_SIMM (insn, 13);
717
                      else
718
                        info->target |= X_SIMM (insn, 13);
719
                      (*info->print_address_func) (info->target, info);
720
                      info->insn_type = dis_dref;
721
                      info->data_size = 4;  /* FIXME!!! */
722
                    }
723
                }
724
            }
725
 
726
          if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
727
            {
728
                /* FIXME -- check is_annulled flag */
729
              if (opcode->flags & F_UNBR)
730
                info->insn_type = dis_branch;
731
              if (opcode->flags & F_CONDBR)
732
                info->insn_type = dis_condbranch;
733
              if (opcode->flags & F_JSR)
734
                info->insn_type = dis_jsr;
735
              if (opcode->flags & F_DELAYED)
736
                info->branch_delay_insns = 1;
737
            }
738
 
739
          return sizeof (buffer);
740
        }
741
    }
742
 
743
  info->insn_type = dis_noninsn;        /* Mark as non-valid instruction */
744
  (*info->fprintf_func) (stream, _("unknown"));
745
  return sizeof (buffer);
746
}
747
 
748
/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
749
 
750
static int
751
compute_arch_mask (mach)
752
     unsigned long mach;
753
{
754
  switch (mach)
755
    {
756
    case 0 :
757
    case bfd_mach_sparc :
758
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
759
    case bfd_mach_sparc_sparclet :
760
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
761
    case bfd_mach_sparc_sparclite :
762
    case bfd_mach_sparc_sparclite_le :
763
      /* sparclites insns are recognized by default (because that's how
764
         they've always been treated, for better or worse).  Kludge this by
765
         indicating generic v8 is also selected.  */
766
      return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
767
              | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
768
    case bfd_mach_sparc_v8plus :
769
    case bfd_mach_sparc_v9 :
770
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
771
    case bfd_mach_sparc_v8plusa :
772
    case bfd_mach_sparc_v9a :
773
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
774
    }
775
  abort ();
776
}
777
 
778
/* Compare opcodes A and B.  */
779
 
780
static int
781
compare_opcodes (a, b)
782
     const PTR a;
783
     const PTR b;
784
{
785
  struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
786
  struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
787
  unsigned long int match0 = op0->match, match1 = op1->match;
788
  unsigned long int lose0 = op0->lose, lose1 = op1->lose;
789
  register unsigned int i;
790
 
791
  /* If one (and only one) insn isn't supported by the current architecture,
792
     prefer the one that is.  If neither are supported, but they're both for
793
     the same architecture, continue processing.  Otherwise (both unsupported
794
     and for different architectures), prefer lower numbered arch's (fudged
795
     by comparing the bitmasks).  */
796
  if (op0->architecture & current_arch_mask)
797
    {
798
      if (! (op1->architecture & current_arch_mask))
799
        return -1;
800
    }
801
  else
802
    {
803
      if (op1->architecture & current_arch_mask)
804
        return 1;
805
      else if (op0->architecture != op1->architecture)
806
        return op0->architecture - op1->architecture;
807
    }
808
 
809
  /* If a bit is set in both match and lose, there is something
810
     wrong with the opcode table.  */
811
  if (match0 & lose0)
812
    {
813
      fprintf
814
        (stderr,
815
         /* xgettext:c-format */
816
         _("Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
817
         op0->name, match0, lose0);
818
      op0->lose &= ~op0->match;
819
      lose0 = op0->lose;
820
    }
821
 
822
  if (match1 & lose1)
823
    {
824
      fprintf
825
        (stderr,
826
         /* xgettext:c-format */
827
         _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
828
         op1->name, match1, lose1);
829
      op1->lose &= ~op1->match;
830
      lose1 = op1->lose;
831
    }
832
 
833
  /* Because the bits that are variable in one opcode are constant in
834
     another, it is important to order the opcodes in the right order.  */
835
  for (i = 0; i < 32; ++i)
836
    {
837
      unsigned long int x = 1 << i;
838
      int x0 = (match0 & x) != 0;
839
      int x1 = (match1 & x) != 0;
840
 
841
      if (x0 != x1)
842
        return x1 - x0;
843
    }
844
 
845
  for (i = 0; i < 32; ++i)
846
    {
847
      unsigned long int x = 1 << i;
848
      int x0 = (lose0 & x) != 0;
849
      int x1 = (lose1 & x) != 0;
850
 
851
      if (x0 != x1)
852
        return x1 - x0;
853
    }
854
 
855
  /* They are functionally equal.  So as long as the opcode table is
856
     valid, we can put whichever one first we want, on aesthetic grounds.  */
857
 
858
  /* Our first aesthetic ground is that aliases defer to real insns.  */
859
  {
860
    int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
861
    if (alias_diff != 0)
862
      /* Put the one that isn't an alias first.  */
863
      return alias_diff;
864
  }
865
 
866
  /* Except for aliases, two "identical" instructions had
867
     better have the same opcode.  This is a sanity check on the table.  */
868
  i = strcmp (op0->name, op1->name);
869
  if (i)
870
    {
871
      if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
872
        return i;
873
      else
874
        fprintf (stderr,
875
                 /* xgettext:c-format */
876
                 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
877
                 op0->name, op1->name);
878
    }
879
 
880
  /* Fewer arguments are preferred.  */
881
  {
882
    int length_diff = strlen (op0->args) - strlen (op1->args);
883
    if (length_diff != 0)
884
      /* Put the one with fewer arguments first.  */
885
      return length_diff;
886
  }
887
 
888
  /* Put 1+i before i+1.  */
889
  {
890
    char *p0 = (char *) strchr (op0->args, '+');
891
    char *p1 = (char *) strchr (op1->args, '+');
892
 
893
    if (p0 && p1)
894
      {
895
        /* There is a plus in both operands.  Note that a plus
896
           sign cannot be the first character in args,
897
           so the following [-1]'s are valid.  */
898
        if (p0[-1] == 'i' && p1[1] == 'i')
899
          /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
900
          return 1;
901
        if (p0[1] == 'i' && p1[-1] == 'i')
902
          /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
903
          return -1;
904
      }
905
  }
906
 
907
  /* Put 1,i before i,1.  */
908
  {
909
    int i0 = strncmp (op0->args, "i,1", 3) == 0;
910
    int i1 = strncmp (op1->args, "i,1", 3) == 0;
911
 
912
    if (i0 ^ i1)
913
      return i0 - i1;
914
  }
915
 
916
  /* They are, as far as we can tell, identical.
917
     Since qsort may have rearranged the table partially, there is
918
     no way to tell which one was first in the opcode table as
919
     written, so just say there are equal.  */
920
  /* ??? This is no longer true now that we sort a vector of pointers,
921
     not the table itself.  */
922
  return 0;
923
}
924
 
925
/* Build a hash table from the opcode table.
926
   OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
927
 
928
static void
929
build_hash_table (opcode_table, hash_table, num_opcodes)
930
     const struct sparc_opcode **opcode_table;
931
     struct opcode_hash **hash_table;
932
     int num_opcodes;
933
{
934
  register int i;
935
  int hash_count[HASH_SIZE];
936
  static struct opcode_hash *hash_buf = NULL;
937
 
938
  /* Start at the end of the table and work backwards so that each
939
     chain is sorted.  */
940
 
941
  memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
942
  memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
943
  if (hash_buf != NULL)
944
    free (hash_buf);
945
  hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
946
  for (i = num_opcodes - 1; i >= 0; --i)
947
    {
948
      register int hash = HASH_INSN (opcode_table[i]->match);
949
      register struct opcode_hash *h = &hash_buf[i];
950
      h->next = hash_table[hash];
951
      h->opcode = opcode_table[i];
952
      hash_table[hash] = h;
953
      ++hash_count[hash];
954
    }
955
 
956
#if 0 /* for debugging */
957
  {
958
    int min_count = num_opcodes, max_count = 0;
959
    int total;
960
 
961
    for (i = 0; i < HASH_SIZE; ++i)
962
      {
963
        if (hash_count[i] < min_count)
964
          min_count = hash_count[i];
965
        if (hash_count[i] > max_count)
966
          max_count = hash_count[i];
967
        total += hash_count[i];
968
      }
969
 
970
    printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
971
            min_count, max_count, (double) total / HASH_SIZE);
972
  }
973
#endif
974
}

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