OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.0/] [sim/] [m32r/] [cpux.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom 
/* CPU family header for m32rxf.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Simulators.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#ifndef CPU_M32RXF_H
26 
#define CPU_M32RXF_H
27 
 
28 
/* Maximum number of instructions that are fetched at a time.
29 
   This is for LIW type instructions sets (e.g. m32r).  */
30 
#define MAX_LIW_INSNS 2
31 
 
32 
/* Maximum number of instructions that can be executed in parallel.  */
33 
#define MAX_PARALLEL_INSNS 2
34 
 
35 
/* CPU state information.  */
36 
typedef struct {
37 
  /* Hardware elements.  */
38 
  struct {
39 
  /* program counter */
40 
  USI h_pc;
41 
#define GET_H_PC() CPU (h_pc)
42 
#define SET_H_PC(x) (CPU (h_pc) = (x))
43 
  /* general registers */
44 
  SI h_gr[16];
45 
#define GET_H_GR(a1) CPU (h_gr)[a1]
46 
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 
  /* control registers */
48 
  USI h_cr[16];
49 
#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
50 
#define SET_H_CR(index, x) \
51 
do { \
52 
m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
53 
} while (0)
54 
  /* accumulator */
55 
  DI h_accum;
56 
#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
57 
#define SET_H_ACCUM(x) \
58 
do { \
59 
m32rxf_h_accum_set_handler (current_cpu, (x));\
60 
} while (0)
61 
  /* accumulators */
62 
  DI h_accums[2];
63 
#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
64 
#define SET_H_ACCUMS(index, x) \
65 
do { \
66 
m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
67 
} while (0)
68 
  /* condition bit */
69 
  BI h_cond;
70 
#define GET_H_COND() CPU (h_cond)
71 
#define SET_H_COND(x) (CPU (h_cond) = (x))
72 
  /* psw part of psw */
73 
  UQI h_psw;
74 
#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
75 
#define SET_H_PSW(x) \
76 
do { \
77 
m32rxf_h_psw_set_handler (current_cpu, (x));\
78 
} while (0)
79 
  /* backup psw */
80 
  UQI h_bpsw;
81 
#define GET_H_BPSW() CPU (h_bpsw)
82 
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
83 
  /* backup bpsw */
84 
  UQI h_bbpsw;
85 
#define GET_H_BBPSW() CPU (h_bbpsw)
86 
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
87 
  /* lock */
88 
  BI h_lock;
89 
#define GET_H_LOCK() CPU (h_lock)
90 
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
91 
  } hardware;
92 
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
93 
} M32RXF_CPU_DATA;
94 
 
95 
/* Cover fns for register access.  */
96 
USI m32rxf_h_pc_get (SIM_CPU *);
97 
void m32rxf_h_pc_set (SIM_CPU *, USI);
98 
SI m32rxf_h_gr_get (SIM_CPU *, UINT);
99 
void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
100 
USI m32rxf_h_cr_get (SIM_CPU *, UINT);
101 
void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
102 
DI m32rxf_h_accum_get (SIM_CPU *);
103 
void m32rxf_h_accum_set (SIM_CPU *, DI);
104 
DI m32rxf_h_accums_get (SIM_CPU *, UINT);
105 
void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
106 
BI m32rxf_h_cond_get (SIM_CPU *);
107 
void m32rxf_h_cond_set (SIM_CPU *, BI);
108 
UQI m32rxf_h_psw_get (SIM_CPU *);
109 
void m32rxf_h_psw_set (SIM_CPU *, UQI);
110 
UQI m32rxf_h_bpsw_get (SIM_CPU *);
111 
void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
112 
UQI m32rxf_h_bbpsw_get (SIM_CPU *);
113 
void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
114 
BI m32rxf_h_lock_get (SIM_CPU *);
115 
void m32rxf_h_lock_set (SIM_CPU *, BI);
116 
 
117 
/* These must be hand-written.  */
118 
extern CPUREG_FETCH_FN m32rxf_fetch_register;
119 
extern CPUREG_STORE_FN m32rxf_store_register;
120 
 
121 
typedef struct {
122 
  int empty;
123 
} MODEL_M32RX_DATA;
124 
 
125 
/* Instruction argument buffer.  */
126 
 
127 
union sem_fields {
128 
  struct { /* no operands */
129 
    int empty;
130 
  } fmt_empty;
131 
  struct { /*  */
132 
    UINT f_uimm4;
133 
  } sfmt_trap;
134 
  struct { /*  */
135 
    IADDR i_disp24;
136 
    unsigned char out_h_gr_14;
137 
  } sfmt_bl24;
138 
  struct { /*  */
139 
    IADDR i_disp8;
140 
    unsigned char out_h_gr_14;
141 
  } sfmt_bl8;
142 
  struct { /*  */
143 
    SI* i_dr;
144 
    UINT f_hi16;
145 
    unsigned char out_dr;
146 
  } sfmt_seth;
147 
  struct { /*  */
148 
    SI f_imm1;
149 
    UINT f_accd;
150 
    UINT f_accs;
151 
  } sfmt_rac_dsi;
152 
  struct { /*  */
153 
    SI* i_sr;
154 
    UINT f_r1;
155 
    unsigned char in_sr;
156 
  } sfmt_mvtc;
157 
  struct { /*  */
158 
    SI* i_src1;
159 
    UINT f_accs;
160 
    unsigned char in_src1;
161 
  } sfmt_mvtachi_a;
162 
  struct { /*  */
163 
    SI* i_dr;
164 
    UINT f_r2;
165 
    unsigned char out_dr;
166 
  } sfmt_mvfc;
167 
  struct { /*  */
168 
    SI* i_dr;
169 
    UINT f_accs;
170 
    unsigned char out_dr;
171 
  } sfmt_mvfachi_a;
172 
  struct { /*  */
173 
    ADDR i_uimm24;
174 
    SI* i_dr;
175 
    unsigned char out_dr;
176 
  } sfmt_ld24;
177 
  struct { /*  */
178 
    SI* i_sr;
179 
    unsigned char in_sr;
180 
    unsigned char out_h_gr_14;
181 
  } sfmt_jl;
182 
  struct { /*  */
183 
    SI* i_dr;
184 
    UINT f_uimm5;
185 
    unsigned char in_dr;
186 
    unsigned char out_dr;
187 
  } sfmt_slli;
188 
  struct { /*  */
189 
    SI* i_dr;
190 
    INT f_simm8;
191 
    unsigned char in_dr;
192 
    unsigned char out_dr;
193 
  } sfmt_addi;
194 
  struct { /*  */
195 
    SI* i_src1;
196 
    SI* i_src2;
197 
    unsigned char in_src1;
198 
    unsigned char in_src2;
199 
    unsigned char out_src2;
200 
  } sfmt_st_plus;
201 
  struct { /*  */
202 
    SI* i_src1;
203 
    SI* i_src2;
204 
    INT f_simm16;
205 
    unsigned char in_src1;
206 
    unsigned char in_src2;
207 
  } sfmt_st_d;
208 
  struct { /*  */
209 
    SI* i_src1;
210 
    SI* i_src2;
211 
    UINT f_acc;
212 
    unsigned char in_src1;
213 
    unsigned char in_src2;
214 
  } sfmt_machi_a;
215 
  struct { /*  */
216 
    SI* i_dr;
217 
    SI* i_sr;
218 
    unsigned char in_sr;
219 
    unsigned char out_dr;
220 
    unsigned char out_sr;
221 
  } sfmt_ld_plus;
222 
  struct { /*  */
223 
    IADDR i_disp16;
224 
    SI* i_src1;
225 
    SI* i_src2;
226 
    unsigned char in_src1;
227 
    unsigned char in_src2;
228 
  } sfmt_beq;
229 
  struct { /*  */
230 
    SI* i_dr;
231 
    SI* i_sr;
232 
    UINT f_uimm16;
233 
    unsigned char in_sr;
234 
    unsigned char out_dr;
235 
  } sfmt_and3;
236 
  struct { /*  */
237 
    SI* i_dr;
238 
    SI* i_sr;
239 
    INT f_simm16;
240 
    unsigned char in_sr;
241 
    unsigned char out_dr;
242 
  } sfmt_add3;
243 
  struct { /*  */
244 
    SI* i_dr;
245 
    SI* i_sr;
246 
    unsigned char in_dr;
247 
    unsigned char in_sr;
248 
    unsigned char out_dr;
249 
  } sfmt_add;
250 
#if WITH_SCACHE_PBB
251 
  /* Writeback handler.  */
252 
  struct {
253 
    /* Pointer to argbuf entry for insn whose results need writing back.  */
254 
    const struct argbuf *abuf;
255 
  } write;
256 
  /* x-before handler */
257 
  struct {
258 
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
259 
    int first_p;
260 
  } before;
261 
  /* x-after handler */
262 
  struct {
263 
    int empty;
264 
  } after;
265 
  /* This entry is used to terminate each pbb.  */
266 
  struct {
267 
    /* Number of insns in pbb.  */
268 
    int insn_count;
269 
    /* Next pbb to execute.  */
270 
    SCACHE *next;
271 
    SCACHE *branch_target;
272 
  } chain;
273 
#endif
274 
};
275 
 
276 
/* The ARGBUF struct.  */
277 
struct argbuf {
278 
  /* These are the baseclass definitions.  */
279 
  IADDR addr;
280 
  const IDESC *idesc;
281 
  char trace_p;
282 
  char profile_p;
283 
  /* ??? Temporary hack for skip insns.  */
284 
  char skip_count;
285 
  char unused;
286 
  /* cpu specific data follows */
287 
  union sem semantic;
288 
  int written;
289 
  union sem_fields fields;
290 
};
291 
 
292 
/* A cached insn.
293 
 
294 
   ??? SCACHE used to contain more than just argbuf.  We could delete the
295 
   type entirely and always just use ARGBUF, but for future concerns and as
296 
   a level of abstraction it is left in.  */
297 
 
298 
struct scache {
299 
  struct argbuf argbuf;
300 
};
301 
 
302 
/* Macros to simplify extraction, reading and semantic code.
303 
   These define and assign the local vars that contain the insn's fields.  */
304 
 
305 
#define EXTRACT_IFMT_EMPTY_VARS \
306 
  unsigned int length;
307 
#define EXTRACT_IFMT_EMPTY_CODE \
308 
  length = 0; \
309 
 
310 
#define EXTRACT_IFMT_ADD_VARS \
311 
  UINT f_op1; \
312 
  UINT f_r1; \
313 
  UINT f_op2; \
314 
  UINT f_r2; \
315 
  unsigned int length;
316 
#define EXTRACT_IFMT_ADD_CODE \
317 
  length = 2; \
318 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
319 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
320 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
321 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
322 
 
323 
#define EXTRACT_IFMT_ADD3_VARS \
324 
  UINT f_op1; \
325 
  UINT f_r1; \
326 
  UINT f_op2; \
327 
  UINT f_r2; \
328 
  INT f_simm16; \
329 
  unsigned int length;
330 
#define EXTRACT_IFMT_ADD3_CODE \
331 
  length = 4; \
332 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
333 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
334 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
335 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
336 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
337 
 
338 
#define EXTRACT_IFMT_AND3_VARS \
339 
  UINT f_op1; \
340 
  UINT f_r1; \
341 
  UINT f_op2; \
342 
  UINT f_r2; \
343 
  UINT f_uimm16; \
344 
  unsigned int length;
345 
#define EXTRACT_IFMT_AND3_CODE \
346 
  length = 4; \
347 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
348 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
349 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
350 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
351 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
352 
 
353 
#define EXTRACT_IFMT_OR3_VARS \
354 
  UINT f_op1; \
355 
  UINT f_r1; \
356 
  UINT f_op2; \
357 
  UINT f_r2; \
358 
  UINT f_uimm16; \
359 
  unsigned int length;
360 
#define EXTRACT_IFMT_OR3_CODE \
361 
  length = 4; \
362 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
363 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
364 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
365 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
366 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
367 
 
368 
#define EXTRACT_IFMT_ADDI_VARS \
369 
  UINT f_op1; \
370 
  UINT f_r1; \
371 
  INT f_simm8; \
372 
  unsigned int length;
373 
#define EXTRACT_IFMT_ADDI_CODE \
374 
  length = 2; \
375 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
376 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
377 
  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
378 
 
379 
#define EXTRACT_IFMT_ADDV3_VARS \
380 
  UINT f_op1; \
381 
  UINT f_r1; \
382 
  UINT f_op2; \
383 
  UINT f_r2; \
384 
  INT f_simm16; \
385 
  unsigned int length;
386 
#define EXTRACT_IFMT_ADDV3_CODE \
387 
  length = 4; \
388 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
389 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
390 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
391 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
392 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
393 
 
394 
#define EXTRACT_IFMT_BC8_VARS \
395 
  UINT f_op1; \
396 
  UINT f_r1; \
397 
  SI f_disp8; \
398 
  unsigned int length;
399 
#define EXTRACT_IFMT_BC8_CODE \
400 
  length = 2; \
401 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
402 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
403 
  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
404 
 
405 
#define EXTRACT_IFMT_BC24_VARS \
406 
  UINT f_op1; \
407 
  UINT f_r1; \
408 
  SI f_disp24; \
409 
  unsigned int length;
410 
#define EXTRACT_IFMT_BC24_CODE \
411 
  length = 4; \
412 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
413 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
414 
  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
415 
 
416 
#define EXTRACT_IFMT_BEQ_VARS \
417 
  UINT f_op1; \
418 
  UINT f_r1; \
419 
  UINT f_op2; \
420 
  UINT f_r2; \
421 
  SI f_disp16; \
422 
  unsigned int length;
423 
#define EXTRACT_IFMT_BEQ_CODE \
424 
  length = 4; \
425 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
426 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
427 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
428 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
429 
  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
430 
 
431 
#define EXTRACT_IFMT_BEQZ_VARS \
432 
  UINT f_op1; \
433 
  UINT f_r1; \
434 
  UINT f_op2; \
435 
  UINT f_r2; \
436 
  SI f_disp16; \
437 
  unsigned int length;
438 
#define EXTRACT_IFMT_BEQZ_CODE \
439 
  length = 4; \
440 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
441 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
442 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
443 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
444 
  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
445 
 
446 
#define EXTRACT_IFMT_CMP_VARS \
447 
  UINT f_op1; \
448 
  UINT f_r1; \
449 
  UINT f_op2; \
450 
  UINT f_r2; \
451 
  unsigned int length;
452 
#define EXTRACT_IFMT_CMP_CODE \
453 
  length = 2; \
454 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
455 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
456 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
457 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
458 
 
459 
#define EXTRACT_IFMT_CMPI_VARS \
460 
  UINT f_op1; \
461 
  UINT f_r1; \
462 
  UINT f_op2; \
463 
  UINT f_r2; \
464 
  INT f_simm16; \
465 
  unsigned int length;
466 
#define EXTRACT_IFMT_CMPI_CODE \
467 
  length = 4; \
468 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
469 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
470 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
471 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
472 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
473 
 
474 
#define EXTRACT_IFMT_CMPZ_VARS \
475 
  UINT f_op1; \
476 
  UINT f_r1; \
477 
  UINT f_op2; \
478 
  UINT f_r2; \
479 
  unsigned int length;
480 
#define EXTRACT_IFMT_CMPZ_CODE \
481 
  length = 2; \
482 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
483 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
484 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
485 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
486 
 
487 
#define EXTRACT_IFMT_DIV_VARS \
488 
  UINT f_op1; \
489 
  UINT f_r1; \
490 
  UINT f_op2; \
491 
  UINT f_r2; \
492 
  INT f_simm16; \
493 
  unsigned int length;
494 
#define EXTRACT_IFMT_DIV_CODE \
495 
  length = 4; \
496 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
497 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
498 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
499 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
500 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
501 
 
502 
#define EXTRACT_IFMT_JC_VARS \
503 
  UINT f_op1; \
504 
  UINT f_r1; \
505 
  UINT f_op2; \
506 
  UINT f_r2; \
507 
  unsigned int length;
508 
#define EXTRACT_IFMT_JC_CODE \
509 
  length = 2; \
510 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
511 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
512 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
513 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
514 
 
515 
#define EXTRACT_IFMT_LD24_VARS \
516 
  UINT f_op1; \
517 
  UINT f_r1; \
518 
  UINT f_uimm24; \
519 
  unsigned int length;
520 
#define EXTRACT_IFMT_LD24_CODE \
521 
  length = 4; \
522 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
523 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
524 
  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
525 
 
526 
#define EXTRACT_IFMT_LDI16_VARS \
527 
  UINT f_op1; \
528 
  UINT f_r1; \
529 
  UINT f_op2; \
530 
  UINT f_r2; \
531 
  INT f_simm16; \
532 
  unsigned int length;
533 
#define EXTRACT_IFMT_LDI16_CODE \
534 
  length = 4; \
535 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
536 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
537 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
538 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
539 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
540 
 
541 
#define EXTRACT_IFMT_MACHI_A_VARS \
542 
  UINT f_op1; \
543 
  UINT f_r1; \
544 
  UINT f_acc; \
545 
  UINT f_op23; \
546 
  UINT f_r2; \
547 
  unsigned int length;
548 
#define EXTRACT_IFMT_MACHI_A_CODE \
549 
  length = 2; \
550 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
551 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
552 
  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
553 
  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
554 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
555 
 
556 
#define EXTRACT_IFMT_MVFACHI_A_VARS \
557 
  UINT f_op1; \
558 
  UINT f_r1; \
559 
  UINT f_op2; \
560 
  UINT f_accs; \
561 
  UINT f_op3; \
562 
  unsigned int length;
563 
#define EXTRACT_IFMT_MVFACHI_A_CODE \
564 
  length = 2; \
565 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
566 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
567 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
568 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
569 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
570 
 
571 
#define EXTRACT_IFMT_MVFC_VARS \
572 
  UINT f_op1; \
573 
  UINT f_r1; \
574 
  UINT f_op2; \
575 
  UINT f_r2; \
576 
  unsigned int length;
577 
#define EXTRACT_IFMT_MVFC_CODE \
578 
  length = 2; \
579 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
582 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
583 
 
584 
#define EXTRACT_IFMT_MVTACHI_A_VARS \
585 
  UINT f_op1; \
586 
  UINT f_r1; \
587 
  UINT f_op2; \
588 
  UINT f_accs; \
589 
  UINT f_op3; \
590 
  unsigned int length;
591 
#define EXTRACT_IFMT_MVTACHI_A_CODE \
592 
  length = 2; \
593 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
594 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
595 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
596 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
597 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
598 
 
599 
#define EXTRACT_IFMT_MVTC_VARS \
600 
  UINT f_op1; \
601 
  UINT f_r1; \
602 
  UINT f_op2; \
603 
  UINT f_r2; \
604 
  unsigned int length;
605 
#define EXTRACT_IFMT_MVTC_CODE \
606 
  length = 2; \
607 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
610 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
611 
 
612 
#define EXTRACT_IFMT_NOP_VARS \
613 
  UINT f_op1; \
614 
  UINT f_r1; \
615 
  UINT f_op2; \
616 
  UINT f_r2; \
617 
  unsigned int length;
618 
#define EXTRACT_IFMT_NOP_CODE \
619 
  length = 2; \
620 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
621 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
622 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
623 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
624 
 
625 
#define EXTRACT_IFMT_RAC_DSI_VARS \
626 
  UINT f_op1; \
627 
  UINT f_accd; \
628 
  UINT f_bits67; \
629 
  UINT f_op2; \
630 
  UINT f_accs; \
631 
  UINT f_bit14; \
632 
  SI f_imm1; \
633 
  unsigned int length;
634 
#define EXTRACT_IFMT_RAC_DSI_CODE \
635 
  length = 2; \
636 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
637 
  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
638 
  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
639 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
640 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
641 
  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
642 
  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
643 
 
644 
#define EXTRACT_IFMT_SETH_VARS \
645 
  UINT f_op1; \
646 
  UINT f_r1; \
647 
  UINT f_op2; \
648 
  UINT f_r2; \
649 
  UINT f_hi16; \
650 
  unsigned int length;
651 
#define EXTRACT_IFMT_SETH_CODE \
652 
  length = 4; \
653 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
654 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
655 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
656 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
657 
  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
658 
 
659 
#define EXTRACT_IFMT_SLLI_VARS \
660 
  UINT f_op1; \
661 
  UINT f_r1; \
662 
  UINT f_shift_op2; \
663 
  UINT f_uimm5; \
664 
  unsigned int length;
665 
#define EXTRACT_IFMT_SLLI_CODE \
666 
  length = 2; \
667 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
668 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
669 
  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
670 
  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
671 
 
672 
#define EXTRACT_IFMT_ST_D_VARS \
673 
  UINT f_op1; \
674 
  UINT f_r1; \
675 
  UINT f_op2; \
676 
  UINT f_r2; \
677 
  INT f_simm16; \
678 
  unsigned int length;
679 
#define EXTRACT_IFMT_ST_D_CODE \
680 
  length = 4; \
681 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
682 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
683 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
684 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
685 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
686 
 
687 
#define EXTRACT_IFMT_TRAP_VARS \
688 
  UINT f_op1; \
689 
  UINT f_r1; \
690 
  UINT f_op2; \
691 
  UINT f_uimm4; \
692 
  unsigned int length;
693 
#define EXTRACT_IFMT_TRAP_CODE \
694 
  length = 2; \
695 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
696 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
697 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
698 
  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
699 
 
700 
#define EXTRACT_IFMT_SATB_VARS \
701 
  UINT f_op1; \
702 
  UINT f_r1; \
703 
  UINT f_op2; \
704 
  UINT f_r2; \
705 
  UINT f_uimm16; \
706 
  unsigned int length;
707 
#define EXTRACT_IFMT_SATB_CODE \
708 
  length = 4; \
709 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
710 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
711 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
712 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
713 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
714 
 
715 
/* Queued output values of an instruction.  */
716 
 
717 
struct parexec {
718 
  union {
719 
    struct { /* empty sformat for unspecified field list */
720 
      int empty;
721 
    } sfmt_empty;
722 
    struct { /* e.g. add $dr,$sr */
723 
      SI dr;
724 
    } sfmt_add;
725 
    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
726 
      SI dr;
727 
    } sfmt_add3;
728 
    struct { /* e.g. and3 $dr,$sr,$uimm16 */
729 
      SI dr;
730 
    } sfmt_and3;
731 
    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
732 
      SI dr;
733 
    } sfmt_or3;
734 
    struct { /* e.g. addi $dr,$simm8 */
735 
      SI dr;
736 
    } sfmt_addi;
737 
    struct { /* e.g. addv $dr,$sr */
738 
      BI condbit;
739 
      SI dr;
740 
    } sfmt_addv;
741 
    struct { /* e.g. addv3 $dr,$sr,$simm16 */
742 
      BI condbit;
743 
      SI dr;
744 
    } sfmt_addv3;
745 
    struct { /* e.g. addx $dr,$sr */
746 
      BI condbit;
747 
      SI dr;
748 
    } sfmt_addx;
749 
    struct { /* e.g. bc.s $disp8 */
750 
      USI pc;
751 
    } sfmt_bc8;
752 
    struct { /* e.g. bc.l $disp24 */
753 
      USI pc;
754 
    } sfmt_bc24;
755 
    struct { /* e.g. beq $src1,$src2,$disp16 */
756 
      USI pc;
757 
    } sfmt_beq;
758 
    struct { /* e.g. beqz $src2,$disp16 */
759 
      USI pc;
760 
    } sfmt_beqz;
761 
    struct { /* e.g. bl.s $disp8 */
762 
      SI h_gr_14;
763 
      USI pc;
764 
    } sfmt_bl8;
765 
    struct { /* e.g. bl.l $disp24 */
766 
      SI h_gr_14;
767 
      USI pc;
768 
    } sfmt_bl24;
769 
    struct { /* e.g. bcl.s $disp8 */
770 
      SI h_gr_14;
771 
      USI pc;
772 
    } sfmt_bcl8;
773 
    struct { /* e.g. bcl.l $disp24 */
774 
      SI h_gr_14;
775 
      USI pc;
776 
    } sfmt_bcl24;
777 
    struct { /* e.g. bra.s $disp8 */
778 
      USI pc;
779 
    } sfmt_bra8;
780 
    struct { /* e.g. bra.l $disp24 */
781 
      USI pc;
782 
    } sfmt_bra24;
783 
    struct { /* e.g. cmp $src1,$src2 */
784 
      BI condbit;
785 
    } sfmt_cmp;
786 
    struct { /* e.g. cmpi $src2,$simm16 */
787 
      BI condbit;
788 
    } sfmt_cmpi;
789 
    struct { /* e.g. cmpz $src2 */
790 
      BI condbit;
791 
    } sfmt_cmpz;
792 
    struct { /* e.g. div $dr,$sr */
793 
      SI dr;
794 
    } sfmt_div;
795 
    struct { /* e.g. jc $sr */
796 
      USI pc;
797 
    } sfmt_jc;
798 
    struct { /* e.g. jl $sr */
799 
      SI h_gr_14;
800 
      USI pc;
801 
    } sfmt_jl;
802 
    struct { /* e.g. jmp $sr */
803 
      USI pc;
804 
    } sfmt_jmp;
805 
    struct { /* e.g. ld $dr,@$sr */
806 
      SI dr;
807 
    } sfmt_ld;
808 
    struct { /* e.g. ld $dr,@($slo16,$sr) */
809 
      SI dr;
810 
    } sfmt_ld_d;
811 
    struct { /* e.g. ld $dr,@$sr+ */
812 
      SI dr;
813 
      SI sr;
814 
    } sfmt_ld_plus;
815 
    struct { /* e.g. ld24 $dr,$uimm24 */
816 
      SI dr;
817 
    } sfmt_ld24;
818 
    struct { /* e.g. ldi8 $dr,$simm8 */
819 
      SI dr;
820 
    } sfmt_ldi8;
821 
    struct { /* e.g. ldi16 $dr,$hash$slo16 */
822 
      SI dr;
823 
    } sfmt_ldi16;
824 
    struct { /* e.g. lock $dr,@$sr */
825 
      SI dr;
826 
      BI h_lock;
827 
    } sfmt_lock;
828 
    struct { /* e.g. machi $src1,$src2,$acc */
829 
      DI acc;
830 
    } sfmt_machi_a;
831 
    struct { /* e.g. mulhi $src1,$src2,$acc */
832 
      DI acc;
833 
    } sfmt_mulhi_a;
834 
    struct { /* e.g. mv $dr,$sr */
835 
      SI dr;
836 
    } sfmt_mv;
837 
    struct { /* e.g. mvfachi $dr,$accs */
838 
      SI dr;
839 
    } sfmt_mvfachi_a;
840 
    struct { /* e.g. mvfc $dr,$scr */
841 
      SI dr;
842 
    } sfmt_mvfc;
843 
    struct { /* e.g. mvtachi $src1,$accs */
844 
      DI accs;
845 
    } sfmt_mvtachi_a;
846 
    struct { /* e.g. mvtc $sr,$dcr */
847 
      USI dcr;
848 
    } sfmt_mvtc;
849 
    struct { /* e.g. nop */
850 
      int empty;
851 
    } sfmt_nop;
852 
    struct { /* e.g. rac $accd,$accs,$imm1 */
853 
      DI accd;
854 
    } sfmt_rac_dsi;
855 
    struct { /* e.g. rte */
856 
      UQI h_bpsw;
857 
      USI h_cr_6;
858 
      UQI h_psw;
859 
      USI pc;
860 
    } sfmt_rte;
861 
    struct { /* e.g. seth $dr,$hash$hi16 */
862 
      SI dr;
863 
    } sfmt_seth;
864 
    struct { /* e.g. sll3 $dr,$sr,$simm16 */
865 
      SI dr;
866 
    } sfmt_sll3;
867 
    struct { /* e.g. slli $dr,$uimm5 */
868 
      SI dr;
869 
    } sfmt_slli;
870 
    struct { /* e.g. st $src1,@$src2 */
871 
      SI h_memory_src2;
872 
      USI h_memory_src2_idx;
873 
    } sfmt_st;
874 
    struct { /* e.g. st $src1,@($slo16,$src2) */
875 
      SI h_memory_add__DFLT_src2_slo16;
876 
      USI h_memory_add__DFLT_src2_slo16_idx;
877 
    } sfmt_st_d;
878 
    struct { /* e.g. stb $src1,@$src2 */
879 
      QI h_memory_src2;
880 
      USI h_memory_src2_idx;
881 
    } sfmt_stb;
882 
    struct { /* e.g. stb $src1,@($slo16,$src2) */
883 
      QI h_memory_add__DFLT_src2_slo16;
884 
      USI h_memory_add__DFLT_src2_slo16_idx;
885 
    } sfmt_stb_d;
886 
    struct { /* e.g. sth $src1,@$src2 */
887 
      HI h_memory_src2;
888 
      USI h_memory_src2_idx;
889 
    } sfmt_sth;
890 
    struct { /* e.g. sth $src1,@($slo16,$src2) */
891 
      HI h_memory_add__DFLT_src2_slo16;
892 
      USI h_memory_add__DFLT_src2_slo16_idx;
893 
    } sfmt_sth_d;
894 
    struct { /* e.g. st $src1,@+$src2 */
895 
      SI h_memory_new_src2;
896 
      USI h_memory_new_src2_idx;
897 
      SI src2;
898 
    } sfmt_st_plus;
899 
    struct { /* e.g. trap $uimm4 */
900 
      UQI h_bbpsw;
901 
      UQI h_bpsw;
902 
      USI h_cr_14;
903 
      USI h_cr_6;
904 
      UQI h_psw;
905 
      SI pc;
906 
    } sfmt_trap;
907 
    struct { /* e.g. unlock $src1,@$src2 */
908 
      BI h_lock;
909 
      SI h_memory_src2;
910 
      USI h_memory_src2_idx;
911 
    } sfmt_unlock;
912 
    struct { /* e.g. satb $dr,$sr */
913 
      SI dr;
914 
    } sfmt_satb;
915 
    struct { /* e.g. sat $dr,$sr */
916 
      SI dr;
917 
    } sfmt_sat;
918 
    struct { /* e.g. sadd */
919 
      DI h_accums_0;
920 
    } sfmt_sadd;
921 
    struct { /* e.g. macwu1 $src1,$src2 */
922 
      DI h_accums_1;
923 
    } sfmt_macwu1;
924 
    struct { /* e.g. msblo $src1,$src2 */
925 
      DI accum;
926 
    } sfmt_msblo;
927 
    struct { /* e.g. mulwu1 $src1,$src2 */
928 
      DI h_accums_1;
929 
    } sfmt_mulwu1;
930 
    struct { /* e.g. sc */
931 
      int empty;
932 
    } sfmt_sc;
933 
  } operands;
934 
  /* For conditionally written operands, bitmask of which ones were.  */
935 
  int written;
936 
};
937 
 
938 
/* Collection of various things for the trace handler to use.  */
939 
 
940 
typedef struct trace_record {
941 
  IADDR pc;
942 
  /* FIXME:wip */
943 
} TRACE_RECORD;
944 
 
945 
#endif /* CPU_M32RXF_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.