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1 1181 sfurman
@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct symbol_cache_entry **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is
88
the pointer into the table returned by the back end's
89
@code{get_symtab} action. @xref{Symbols}. The symbol is referenced
90
through a pointer to a pointer so that tools like the linker
91
can fix up all the symbols of the same name by modifying only
92
one pointer. The relocation routine looks in the symbol and
93
uses the base of the section the symbol is attached to and the
94
value of the symbol as the initial relocation offset. If the
95
symbol pointer is zero, then the section provided is looked up.
96
 
97
@itemize @bullet
98
 
99
@item
100
@code{address}
101
@end itemize
102
The @code{address} field gives the offset in bytes from the base of
103
the section data which owns the relocation record to the first
104
byte of relocatable information. The actual data relocated
105
will be relative to this point; for example, a relocation
106
type which modifies the bottom two bytes of a four byte word
107
would not touch the first byte pointed to in a big endian
108
world.
109
 
110
@itemize @bullet
111
 
112
@item
113
@code{addend}
114
@end itemize
115
The @code{addend} is a value provided by the back end to be added (!)
116
to the relocation offset. Its interpretation is dependent upon
117
the howto. For example, on the 68k the code:
118
 
119
@example
120
        char foo[];
121
        main()
122
                @{
123
                return foo[0x12345678];
124
                @}
125
@end example
126
 
127
Could be compiled into:
128
 
129
@example
130
        linkw fp,#-4
131
        moveb @@#12345678,d0
132
        extbl d0
133
        unlk fp
134
        rts
135
@end example
136
 
137
This could create a reloc pointing to @code{foo}, but leave the
138
offset in the data, something like:
139
 
140
@example
141
RELOCATION RECORDS FOR [.text]:
142
offset   type      value
143
00000006 32        _foo
144
 
145
00000000 4e56 fffc          ; linkw fp,#-4
146
00000004 1039 1234 5678     ; moveb @@#12345678,d0
147
0000000a 49c0               ; extbl d0
148
0000000c 4e5e               ; unlk fp
149
0000000e 4e75               ; rts
150
@end example
151
 
152
Using coff and an 88k, some instructions don't have enough
153
space in them to represent the full address range, and
154
pointers have to be loaded in two parts. So you'd get something like:
155
 
156
@example
157
        or.u     r13,r0,hi16(_foo+0x12345678)
158
        ld.b     r2,r13,lo16(_foo+0x12345678)
159
        jmp      r1
160
@end example
161
 
162
This should create two relocs, both pointing to @code{_foo}, and with
163
0x12340000 in their addend field. The data would consist of:
164
 
165
@example
166
RELOCATION RECORDS FOR [.text]:
167
offset   type      value
168
00000002 HVRT16    _foo+0x12340000
169
00000006 LVRT16    _foo+0x12340000
170
 
171
00000000 5da05678           ; or.u r13,r0,0x5678
172
00000004 1c4d5678           ; ld.b r2,r13,0x5678
173
00000008 f400c001           ; jmp r1
174
@end example
175
 
176
The relocation routine digs out the value from the data, adds
177
it to the addend to get the original offset, and then adds the
178
value of @code{_foo}. Note that all 32 bits have to be kept around
179
somewhere, to cope with carry from bit 15 to bit 16.
180
 
181
One further example is the sparc and the a.out format. The
182
sparc has a similar problem to the 88k, in that some
183
instructions don't have room for an entire offset, but on the
184
sparc the parts are created in odd sized lumps. The designers of
185
the a.out format chose to not use the data within the section
186
for storing part of the offset; all the offset is kept within
187
the reloc. Anything in the data should be ignored.
188
 
189
@example
190
        save %sp,-112,%sp
191
        sethi %hi(_foo+0x12345678),%g2
192
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
193
        ret
194
        restore
195
@end example
196
 
197
Both relocs contain a pointer to @code{foo}, and the offsets
198
contain junk.
199
 
200
@example
201
RELOCATION RECORDS FOR [.text]:
202
offset   type      value
203
00000004 HI22      _foo+0x12345678
204
00000008 LO10      _foo+0x12345678
205
 
206
00000000 9de3bf90     ; save %sp,-112,%sp
207
00000004 05000000     ; sethi %hi(_foo+0),%g2
208
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
209
0000000c 81c7e008     ; ret
210
00000010 81e80000     ; restore
211
@end example
212
 
213
@itemize @bullet
214
 
215
@item
216
@code{howto}
217
@end itemize
218
The @code{howto} field can be imagined as a
219
relocation instruction. It is a pointer to a structure which
220
contains information on what to do with all of the other
221
information in the reloc record and data section. A back end
222
would normally have a relocation instruction set and turn
223
relocations into pointers to the correct structure on input -
224
but it would be possible to create each howto field on demand.
225
 
226
@subsubsection @code{enum complain_overflow}
227
Indicates what sort of overflow checking should be done when
228
performing a relocation.
229
 
230
 
231
@example
232
 
233
enum complain_overflow
234
@{
235
  /* Do not complain on overflow.  */
236
  complain_overflow_dont,
237
 
238
  /* Complain if the bitfield overflows, whether it is considered
239
     as signed or unsigned.  */
240
  complain_overflow_bitfield,
241
 
242
  /* Complain if the value overflows when considered as signed
243
     number.  */
244
  complain_overflow_signed,
245
 
246
  /* Complain if the value overflows when considered as an
247
     unsigned number.  */
248
  complain_overflow_unsigned
249
@};
250
@end example
251
@subsubsection @code{reloc_howto_type}
252
The @code{reloc_howto_type} is a structure which contains all the
253
information that libbfd needs to know to tie up a back end's data.
254
 
255
 
256
@example
257
struct symbol_cache_entry;             /* Forward declaration.  */
258
 
259
struct reloc_howto_struct
260
@{
261
  /*  The type field has mainly a documentary use - the back end can
262
      do what it wants with it, though normally the back end's
263
      external idea of what a reloc number is stored
264
      in this field.  For example, a PC relative word relocation
265
      in a coff environment has the type 023 - because that's
266
      what the outside world calls a R_PCRWORD reloc.  */
267
  unsigned int type;
268
 
269
  /*  The value the final relocation is shifted right by.  This drops
270
      unwanted data from the relocation.  */
271
  unsigned int rightshift;
272
 
273
  /*  The size of the item to be relocated.  This is *not* a
274
      power-of-two measure.  To get the number of bytes operated
275
      on by a type of relocation, use bfd_get_reloc_size.  */
276
  int size;
277
 
278
  /*  The number of bits in the item to be relocated.  This is used
279
      when doing overflow checking.  */
280
  unsigned int bitsize;
281
 
282
  /*  Notes that the relocation is relative to the location in the
283
      data section of the addend.  The relocation function will
284
      subtract from the relocation value the address of the location
285
      being relocated.  */
286
  boolean pc_relative;
287
 
288
  /*  The bit position of the reloc value in the destination.
289
      The relocated value is left shifted by this amount.  */
290
  unsigned int bitpos;
291
 
292
  /* What type of overflow error should be checked for when
293
     relocating.  */
294
  enum complain_overflow complain_on_overflow;
295
 
296
  /* If this field is non null, then the supplied function is
297
     called rather than the normal function.  This allows really
298
     strange relocation methods to be accomodated (e.g., i960 callj
299
     instructions).  */
300
  bfd_reloc_status_type (*special_function)
301
    PARAMS ((bfd *, arelent *, struct symbol_cache_entry *, PTR, asection *,
302
             bfd *, char **));
303
 
304
  /* The textual name of the relocation type.  */
305
  char *name;
306
 
307
  /* Some formats record a relocation addend in the section contents
308
     rather than with the relocation.  For ELF formats this is the
309
     distinction between USE_REL and USE_RELA (though the code checks
310
     for USE_REL == 1/0).  The value of this field is TRUE if the
311
     addend is recorded with the section contents; when performing a
312
     partial link (ld -r) the section contents (the data) will be
313
     modified.  The value of this field is FALSE if addends are
314
     recorded with the relocation (in arelent.addend); when performing
315
     a partial link the relocation will be modified.
316
     All relocations for all ELF USE_RELA targets should set this field
317
     to FALSE (values of TRUE should be looked on with suspicion).
318
     However, the converse is not true: not all relocations of all ELF
319
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
320
     to each particular target.  For relocs that aren't used in partial
321
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
322
  boolean partial_inplace;
323
 
324
  /* The src_mask selects which parts of the read in data
325
     are to be used in the relocation sum.  E.g., if this was an 8 bit
326
     byte of data which we read and relocated, this would be
327
     0x000000ff.  When we have relocs which have an addend, such as
328
     sun4 extended relocs, the value in the offset part of a
329
     relocating field is garbage so we never use it.  In this case
330
     the mask would be 0x00000000.  */
331
  bfd_vma src_mask;
332
 
333
  /* The dst_mask selects which parts of the instruction are replaced
334
     into the instruction.  In most cases src_mask == dst_mask,
335
     except in the above special case, where dst_mask would be
336
     0x000000ff, and src_mask would be 0x00000000.  */
337
  bfd_vma dst_mask;
338
 
339
  /* When some formats create PC relative instructions, they leave
340
     the value of the pc of the place being relocated in the offset
341
     slot of the instruction, so that a PC relative relocation can
342
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
343
     Some formats leave the displacement part of an instruction
344
     empty (e.g., m88k bcs); this flag signals the fact.  */
345
  boolean pcrel_offset;
346
@};
347
 
348
@end example
349
@findex The HOWTO Macro
350
@subsubsection @code{The HOWTO Macro}
351
@strong{Description}@*
352
The HOWTO define is horrible and will go away.
353
@example
354
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
355
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
356
@end example
357
 
358
@strong{Description}@*
359
And will be replaced with the totally magic way. But for the
360
moment, we are compatible, so do it this way.
361
@example
362
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
363
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
364
         NAME, false, 0, 0, IN)
365
 
366
@end example
367
 
368
@strong{Description}@*
369
This is used to fill in an empty howto entry in an array.
370
@example
371
#define EMPTY_HOWTO(C) \
372
  HOWTO ((C), 0, 0, 0, false, 0, complain_overflow_dont, NULL, \
373
         NULL, false, 0, 0, false)
374
 
375
@end example
376
 
377
@strong{Description}@*
378
Helper routine to turn a symbol into a relocation value.
379
@example
380
#define HOWTO_PREPARE(relocation, symbol)               \
381
  @{                                                     \
382
    if (symbol != (asymbol *) NULL)                     \
383
      @{                                                 \
384
        if (bfd_is_com_section (symbol->section))       \
385
          @{                                             \
386
            relocation = 0;                             \
387
          @}                                             \
388
        else                                            \
389
          @{                                             \
390
            relocation = symbol->value;                 \
391
          @}                                             \
392
      @}                                                 \
393
  @}
394
 
395
@end example
396
 
397
@findex bfd_get_reloc_size
398
@subsubsection @code{bfd_get_reloc_size}
399
@strong{Synopsis}
400
@example
401
unsigned int bfd_get_reloc_size (reloc_howto_type *);
402
@end example
403
@strong{Description}@*
404
For a reloc_howto_type that operates on a fixed number of bytes,
405
this returns the number of bytes operated on.
406
 
407
@findex arelent_chain
408
@subsubsection @code{arelent_chain}
409
@strong{Description}@*
410
How relocs are tied together in an @code{asection}:
411
@example
412
typedef struct relent_chain
413
@{
414
  arelent relent;
415
  struct relent_chain *next;
416
@}
417
arelent_chain;
418
 
419
@end example
420
 
421
@findex bfd_check_overflow
422
@subsubsection @code{bfd_check_overflow}
423
@strong{Synopsis}
424
@example
425
bfd_reloc_status_type
426
bfd_check_overflow
427
   (enum complain_overflow how,
428
    unsigned int bitsize,
429
    unsigned int rightshift,
430
    unsigned int addrsize,
431
    bfd_vma relocation);
432
@end example
433
@strong{Description}@*
434
Perform overflow checking on @var{relocation} which has
435
@var{bitsize} significant bits and will be shifted right by
436
@var{rightshift} bits, on a machine with addresses containing
437
@var{addrsize} significant bits.  The result is either of
438
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439
 
440
@findex bfd_perform_relocation
441
@subsubsection @code{bfd_perform_relocation}
442
@strong{Synopsis}
443
@example
444
bfd_reloc_status_type
445
bfd_perform_relocation
446
   (bfd *abfd,
447
    arelent *reloc_entry,
448
    PTR data,
449
    asection *input_section,
450
    bfd *output_bfd,
451
    char **error_message);
452
@end example
453
@strong{Description}@*
454
If @var{output_bfd} is supplied to this function, the
455
generated image will be relocatable; the relocations are
456
copied to the output file after they have been changed to
457
reflect the new state of the world. There are two ways of
458
reflecting the results of partial linkage in an output file:
459
by modifying the output data in place, and by modifying the
460
relocation record.  Some native formats (e.g., basic a.out and
461
basic coff) have no way of specifying an addend in the
462
relocation type, so the addend has to go in the output data.
463
This is no big deal since in these formats the output data
464
slot will always be big enough for the addend. Complex reloc
465
types with addends were invented to solve just this problem.
466
The @var{error_message} argument is set to an error message if
467
this return @code{bfd_reloc_dangerous}.
468
 
469
@findex bfd_install_relocation
470
@subsubsection @code{bfd_install_relocation}
471
@strong{Synopsis}
472
@example
473
bfd_reloc_status_type
474
bfd_install_relocation
475
   (bfd *abfd,
476
    arelent *reloc_entry,
477
    PTR data, bfd_vma data_start,
478
    asection *input_section,
479
    char **error_message);
480
@end example
481
@strong{Description}@*
482
This looks remarkably like @code{bfd_perform_relocation}, except it
483
does not expect that the section contents have been filled in.
484
I.e., it's suitable for use when creating, rather than applying
485
a relocation.
486
 
487
For now, this function should be considered reserved for the
488
assembler.
489
 
490
 
491
@node howto manager,  , typedef arelent, Relocations
492
@section The howto manager
493
When an application wants to create a relocation, but doesn't
494
know what the target machine might call it, it can find out by
495
using this bit of code.
496
 
497
@findex bfd_reloc_code_type
498
@subsubsection @code{bfd_reloc_code_type}
499
@strong{Description}@*
500
The insides of a reloc code.  The idea is that, eventually, there
501
will be one enumerator for every type of relocation we ever do.
502
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
503
return a howto pointer.
504
 
505
This does mean that the application must determine the correct
506
enumerator value; you can't get a howto pointer from a random set
507
of attributes.
508
 
509
Here are the possible values for @code{enum bfd_reloc_code_real}:
510
 
511
@deffn {} BFD_RELOC_64
512
@deffnx {} BFD_RELOC_32
513
@deffnx {} BFD_RELOC_26
514
@deffnx {} BFD_RELOC_24
515
@deffnx {} BFD_RELOC_16
516
@deffnx {} BFD_RELOC_14
517
@deffnx {} BFD_RELOC_8
518
Basic absolute relocations of N bits.
519
@end deffn
520
@deffn {} BFD_RELOC_64_PCREL
521
@deffnx {} BFD_RELOC_32_PCREL
522
@deffnx {} BFD_RELOC_24_PCREL
523
@deffnx {} BFD_RELOC_16_PCREL
524
@deffnx {} BFD_RELOC_12_PCREL
525
@deffnx {} BFD_RELOC_8_PCREL
526
PC-relative relocations.  Sometimes these are relative to the address
527
of the relocation itself; sometimes they are relative to the start of
528
the section containing the relocation.  It depends on the specific target.
529
 
530
The 24-bit relocation is used in some Intel 960 configurations.
531
@end deffn
532
@deffn {} BFD_RELOC_32_GOT_PCREL
533
@deffnx {} BFD_RELOC_16_GOT_PCREL
534
@deffnx {} BFD_RELOC_8_GOT_PCREL
535
@deffnx {} BFD_RELOC_32_GOTOFF
536
@deffnx {} BFD_RELOC_16_GOTOFF
537
@deffnx {} BFD_RELOC_LO16_GOTOFF
538
@deffnx {} BFD_RELOC_HI16_GOTOFF
539
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
540
@deffnx {} BFD_RELOC_8_GOTOFF
541
@deffnx {} BFD_RELOC_64_PLT_PCREL
542
@deffnx {} BFD_RELOC_32_PLT_PCREL
543
@deffnx {} BFD_RELOC_24_PLT_PCREL
544
@deffnx {} BFD_RELOC_16_PLT_PCREL
545
@deffnx {} BFD_RELOC_8_PLT_PCREL
546
@deffnx {} BFD_RELOC_64_PLTOFF
547
@deffnx {} BFD_RELOC_32_PLTOFF
548
@deffnx {} BFD_RELOC_16_PLTOFF
549
@deffnx {} BFD_RELOC_LO16_PLTOFF
550
@deffnx {} BFD_RELOC_HI16_PLTOFF
551
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
552
@deffnx {} BFD_RELOC_8_PLTOFF
553
For ELF.
554
@end deffn
555
@deffn {} BFD_RELOC_68K_GLOB_DAT
556
@deffnx {} BFD_RELOC_68K_JMP_SLOT
557
@deffnx {} BFD_RELOC_68K_RELATIVE
558
Relocations used by 68K ELF.
559
@end deffn
560
@deffn {} BFD_RELOC_32_BASEREL
561
@deffnx {} BFD_RELOC_16_BASEREL
562
@deffnx {} BFD_RELOC_LO16_BASEREL
563
@deffnx {} BFD_RELOC_HI16_BASEREL
564
@deffnx {} BFD_RELOC_HI16_S_BASEREL
565
@deffnx {} BFD_RELOC_8_BASEREL
566
@deffnx {} BFD_RELOC_RVA
567
Linkage-table relative.
568
@end deffn
569
@deffn {} BFD_RELOC_8_FFnn
570
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
571
@end deffn
572
@deffn {} BFD_RELOC_32_PCREL_S2
573
@deffnx {} BFD_RELOC_16_PCREL_S2
574
@deffnx {} BFD_RELOC_23_PCREL_S2
575
These PC-relative relocations are stored as word displacements --
576
i.e., byte displacements shifted right two bits.  The 30-bit word
577
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
578
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
579
signed 16-bit displacement is used on the MIPS, and the 23-bit
580
displacement is used on the Alpha.
581
@end deffn
582
@deffn {} BFD_RELOC_HI22
583
@deffnx {} BFD_RELOC_LO10
584
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
585
the target word.  These are used on the SPARC.
586
@end deffn
587
@deffn {} BFD_RELOC_GPREL16
588
@deffnx {} BFD_RELOC_GPREL32
589
For systems that allocate a Global Pointer register, these are
590
displacements off that register.  These relocation types are
591
handled specially, because the value the register will have is
592
decided relatively late.
593
@end deffn
594
@deffn {} BFD_RELOC_I960_CALLJ
595
Reloc types used for i960/b.out.
596
@end deffn
597
@deffn {} BFD_RELOC_NONE
598
@deffnx {} BFD_RELOC_SPARC_WDISP22
599
@deffnx {} BFD_RELOC_SPARC22
600
@deffnx {} BFD_RELOC_SPARC13
601
@deffnx {} BFD_RELOC_SPARC_GOT10
602
@deffnx {} BFD_RELOC_SPARC_GOT13
603
@deffnx {} BFD_RELOC_SPARC_GOT22
604
@deffnx {} BFD_RELOC_SPARC_PC10
605
@deffnx {} BFD_RELOC_SPARC_PC22
606
@deffnx {} BFD_RELOC_SPARC_WPLT30
607
@deffnx {} BFD_RELOC_SPARC_COPY
608
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
609
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
610
@deffnx {} BFD_RELOC_SPARC_RELATIVE
611
@deffnx {} BFD_RELOC_SPARC_UA16
612
@deffnx {} BFD_RELOC_SPARC_UA32
613
@deffnx {} BFD_RELOC_SPARC_UA64
614
SPARC ELF relocations.  There is probably some overlap with other
615
relocation types already defined.
616
@end deffn
617
@deffn {} BFD_RELOC_SPARC_BASE13
618
@deffnx {} BFD_RELOC_SPARC_BASE22
619
I think these are specific to SPARC a.out (e.g., Sun 4).
620
@end deffn
621
@deffn {} BFD_RELOC_SPARC_64
622
@deffnx {} BFD_RELOC_SPARC_10
623
@deffnx {} BFD_RELOC_SPARC_11
624
@deffnx {} BFD_RELOC_SPARC_OLO10
625
@deffnx {} BFD_RELOC_SPARC_HH22
626
@deffnx {} BFD_RELOC_SPARC_HM10
627
@deffnx {} BFD_RELOC_SPARC_LM22
628
@deffnx {} BFD_RELOC_SPARC_PC_HH22
629
@deffnx {} BFD_RELOC_SPARC_PC_HM10
630
@deffnx {} BFD_RELOC_SPARC_PC_LM22
631
@deffnx {} BFD_RELOC_SPARC_WDISP16
632
@deffnx {} BFD_RELOC_SPARC_WDISP19
633
@deffnx {} BFD_RELOC_SPARC_7
634
@deffnx {} BFD_RELOC_SPARC_6
635
@deffnx {} BFD_RELOC_SPARC_5
636
@deffnx {} BFD_RELOC_SPARC_DISP64
637
@deffnx {} BFD_RELOC_SPARC_PLT32
638
@deffnx {} BFD_RELOC_SPARC_PLT64
639
@deffnx {} BFD_RELOC_SPARC_HIX22
640
@deffnx {} BFD_RELOC_SPARC_LOX10
641
@deffnx {} BFD_RELOC_SPARC_H44
642
@deffnx {} BFD_RELOC_SPARC_M44
643
@deffnx {} BFD_RELOC_SPARC_L44
644
@deffnx {} BFD_RELOC_SPARC_REGISTER
645
SPARC64 relocations
646
@end deffn
647
@deffn {} BFD_RELOC_SPARC_REV32
648
SPARC little endian relocation
649
@end deffn
650
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
651
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
652
"addend" in some special way.
653
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
654
writing; when reading, it will be the absolute section symbol.  The
655
addend is the displacement in bytes of the "lda" instruction from
656
the "ldah" instruction (which is at the address of this reloc).
657
@end deffn
658
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
659
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
660
with GPDISP_HI16 relocs.  The addend is ignored when writing the
661
relocations out, and is filled in with the file's GP value on
662
reading, for convenience.
663
@end deffn
664
@deffn {} BFD_RELOC_ALPHA_GPDISP
665
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
666
relocation except that there is no accompanying GPDISP_LO16
667
relocation.
668
@end deffn
669
@deffn {} BFD_RELOC_ALPHA_LITERAL
670
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
671
@deffnx {} BFD_RELOC_ALPHA_LITUSE
672
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
673
the assembler turns it into a LDQ instruction to load the address of
674
the symbol, and then fills in a register in the real instruction.
675
 
676
The LITERAL reloc, at the LDQ instruction, refers to the .lita
677
section symbol.  The addend is ignored when writing, but is filled
678
in with the file's GP value on reading, for convenience, as with the
679
GPDISP_LO16 reloc.
680
 
681
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
682
It should refer to the symbol to be referenced, as with 16_GOTOFF,
683
but it generates output not based on the position within the .got
684
section, but relative to the GP value chosen for the file during the
685
final link stage.
686
 
687
The LITUSE reloc, on the instruction using the loaded address, gives
688
information to the linker that it might be able to use to optimize
689
away some literal section references.  The symbol is ignored (read
690
as the absolute section symbol), and the "addend" indicates the type
691
of instruction using the register:
692
1 - "memory" fmt insn
693
2 - byte-manipulation (byte offset reg)
694
3 - jsr (target of branch)
695
@end deffn
696
@deffn {} BFD_RELOC_ALPHA_HINT
697
The HINT relocation indicates a value that should be filled into the
698
"hint" field of a jmp/jsr/ret instruction, for possible branch-
699
prediction logic which may be provided on some processors.
700
@end deffn
701
@deffn {} BFD_RELOC_ALPHA_LINKAGE
702
The LINKAGE relocation outputs a linkage pair in the object file,
703
which is filled by the linker.
704
@end deffn
705
@deffn {} BFD_RELOC_ALPHA_CODEADDR
706
The CODEADDR relocation outputs a STO_CA in the object file,
707
which is filled by the linker.
708
@end deffn
709
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
710
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
711
The GPREL_HI/LO relocations together form a 32-bit offset from the
712
GP register.
713
@end deffn
714
@deffn {} BFD_RELOC_ALPHA_BRSGP
715
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
716
share a common GP, and the target address is adjusted for
717
STO_ALPHA_STD_GPLOAD.
718
@end deffn
719
@deffn {} BFD_RELOC_ALPHA_TLSGD
720
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
721
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
722
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
723
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
724
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
725
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
726
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
727
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
728
@deffnx {} BFD_RELOC_ALPHA_TPREL64
729
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
730
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
731
@deffnx {} BFD_RELOC_ALPHA_TPREL16
732
Alpha thread-local storage relocations.
733
@end deffn
734
@deffn {} BFD_RELOC_MIPS_JMP
735
Bits 27..2 of the relocation address shifted right 2 bits;
736
simple reloc otherwise.
737
@end deffn
738
@deffn {} BFD_RELOC_MIPS16_JMP
739
The MIPS16 jump instruction.
740
@end deffn
741
@deffn {} BFD_RELOC_MIPS16_GPREL
742
MIPS16 GP relative reloc.
743
@end deffn
744
@deffn {} BFD_RELOC_HI16
745
High 16 bits of 32-bit value; simple reloc.
746
@end deffn
747
@deffn {} BFD_RELOC_HI16_S
748
High 16 bits of 32-bit value but the low 16 bits will be sign
749
extended and added to form the final result.  If the low 16
750
bits form a negative number, we need to add one to the high value
751
to compensate for the borrow when the low bits are added.
752
@end deffn
753
@deffn {} BFD_RELOC_LO16
754
Low 16 bits.
755
@end deffn
756
@deffn {} BFD_RELOC_PCREL_HI16_S
757
Like BFD_RELOC_HI16_S, but PC relative.
758
@end deffn
759
@deffn {} BFD_RELOC_PCREL_LO16
760
Like BFD_RELOC_LO16, but PC relative.
761
@end deffn
762
@deffn {} BFD_RELOC_MIPS_LITERAL
763
Relocation against a MIPS literal section.
764
@end deffn
765
@deffn {} BFD_RELOC_MIPS_GOT16
766
@deffnx {} BFD_RELOC_MIPS_CALL16
767
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
768
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
769
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
770
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
771
@deffnx {} BFD_RELOC_MIPS_SUB
772
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
773
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
774
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
775
@deffnx {} BFD_RELOC_MIPS_SHIFT5
776
@deffnx {} BFD_RELOC_MIPS_SHIFT6
777
@deffnx {} BFD_RELOC_MIPS_INSERT_A
778
@deffnx {} BFD_RELOC_MIPS_INSERT_B
779
@deffnx {} BFD_RELOC_MIPS_DELETE
780
@deffnx {} BFD_RELOC_MIPS_HIGHEST
781
@deffnx {} BFD_RELOC_MIPS_HIGHER
782
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
783
@deffnx {} BFD_RELOC_MIPS_REL16
784
@deffnx {} BFD_RELOC_MIPS_RELGOT
785
@deffnx {} BFD_RELOC_MIPS_JALR
786
@deffn {} BFD_RELOC_FRV_LABEL16
787
@deffnx {} BFD_RELOC_FRV_LABEL24
788
@deffnx {} BFD_RELOC_FRV_LO16
789
@deffnx {} BFD_RELOC_FRV_HI16
790
@deffnx {} BFD_RELOC_FRV_GPREL12
791
@deffnx {} BFD_RELOC_FRV_GPRELU12
792
@deffnx {} BFD_RELOC_FRV_GPREL32
793
@deffnx {} BFD_RELOC_FRV_GPRELHI
794
@deffnx {} BFD_RELOC_FRV_GPRELLO
795
Fujitsu Frv Relocations.
796
@end deffn
797
MIPS ELF relocations.
798
@end deffn
799
@deffn {} BFD_RELOC_386_GOT32
800
@deffnx {} BFD_RELOC_386_PLT32
801
@deffnx {} BFD_RELOC_386_COPY
802
@deffnx {} BFD_RELOC_386_GLOB_DAT
803
@deffnx {} BFD_RELOC_386_JUMP_SLOT
804
@deffnx {} BFD_RELOC_386_RELATIVE
805
@deffnx {} BFD_RELOC_386_GOTOFF
806
@deffnx {} BFD_RELOC_386_GOTPC
807
@deffnx {} BFD_RELOC_386_TLS_LE
808
@deffnx {} BFD_RELOC_386_TLS_GD
809
@deffnx {} BFD_RELOC_386_TLS_LDM
810
@deffnx {} BFD_RELOC_386_TLS_LDO_32
811
@deffnx {} BFD_RELOC_386_TLS_IE_32
812
@deffnx {} BFD_RELOC_386_TLS_LE_32
813
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
814
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
815
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
816
i386/elf relocations
817
@end deffn
818
@deffn {} BFD_RELOC_X86_64_GOT32
819
@deffnx {} BFD_RELOC_X86_64_PLT32
820
@deffnx {} BFD_RELOC_X86_64_COPY
821
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
822
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
823
@deffnx {} BFD_RELOC_X86_64_RELATIVE
824
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
825
@deffnx {} BFD_RELOC_X86_64_32S
826
x86-64/elf relocations
827
@end deffn
828
@deffn {} BFD_RELOC_NS32K_IMM_8
829
@deffnx {} BFD_RELOC_NS32K_IMM_16
830
@deffnx {} BFD_RELOC_NS32K_IMM_32
831
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
832
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
833
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
834
@deffnx {} BFD_RELOC_NS32K_DISP_8
835
@deffnx {} BFD_RELOC_NS32K_DISP_16
836
@deffnx {} BFD_RELOC_NS32K_DISP_32
837
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
838
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
839
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
840
ns32k relocations
841
@end deffn
842
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
843
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
844
PDP11 relocations
845
@end deffn
846
@deffn {} BFD_RELOC_PJ_CODE_HI16
847
@deffnx {} BFD_RELOC_PJ_CODE_LO16
848
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
849
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
850
@deffnx {} BFD_RELOC_PJ_CODE_REL16
851
@deffnx {} BFD_RELOC_PJ_CODE_REL32
852
Picojava relocs.  Not all of these appear in object files.
853
@end deffn
854
@deffn {} BFD_RELOC_PPC_B26
855
@deffnx {} BFD_RELOC_PPC_BA26
856
@deffnx {} BFD_RELOC_PPC_TOC16
857
@deffnx {} BFD_RELOC_PPC_B16
858
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
859
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
860
@deffnx {} BFD_RELOC_PPC_BA16
861
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
862
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
863
@deffnx {} BFD_RELOC_PPC_COPY
864
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
865
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
866
@deffnx {} BFD_RELOC_PPC_RELATIVE
867
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
868
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
869
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
870
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
871
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
872
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
873
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
874
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
875
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
876
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
877
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
878
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
879
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
880
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
881
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
882
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
883
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
884
@deffnx {} BFD_RELOC_PPC64_HIGHER
885
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
886
@deffnx {} BFD_RELOC_PPC64_HIGHEST
887
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
888
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
889
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
890
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
891
@deffnx {} BFD_RELOC_PPC64_TOC
892
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
893
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
894
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
895
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
896
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
897
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
898
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
899
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
900
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
901
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
902
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
903
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
904
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
905
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
906
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
907
Power(rs6000) and PowerPC relocations.
908
@end deffn
909
@deffn {} BFD_RELOC_I370_D12
910
IBM 370/390 relocations
911
@end deffn
912
@deffn {} BFD_RELOC_CTOR
913
The type of reloc used to build a contructor table - at the moment
914
probably a 32 bit wide absolute relocation, but the target can choose.
915
It generally does map to one of the other relocation types.
916
@end deffn
917
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
918
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
919
not stored in the instruction.
920
@end deffn
921
@deffn {} BFD_RELOC_ARM_PCREL_BLX
922
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
923
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
924
field in the instruction.
925
@end deffn
926
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
927
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
928
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
929
field in the instruction.
930
@end deffn
931
@deffn {} BFD_RELOC_ARM_IMMEDIATE
932
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
933
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM
934
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
935
@deffnx {} BFD_RELOC_ARM_SWI
936
@deffnx {} BFD_RELOC_ARM_MULTI
937
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
938
@deffnx {} BFD_RELOC_ARM_ADR_IMM
939
@deffnx {} BFD_RELOC_ARM_LDR_IMM
940
@deffnx {} BFD_RELOC_ARM_LITERAL
941
@deffnx {} BFD_RELOC_ARM_IN_POOL
942
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
943
@deffnx {} BFD_RELOC_ARM_HWLITERAL
944
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
945
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
946
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
947
@deffnx {} BFD_RELOC_ARM_THUMB_OFFSET
948
@deffnx {} BFD_RELOC_ARM_GOT12
949
@deffnx {} BFD_RELOC_ARM_GOT32
950
@deffnx {} BFD_RELOC_ARM_JUMP_SLOT
951
@deffnx {} BFD_RELOC_ARM_COPY
952
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
953
@deffnx {} BFD_RELOC_ARM_PLT32
954
@deffnx {} BFD_RELOC_ARM_RELATIVE
955
@deffnx {} BFD_RELOC_ARM_GOTOFF
956
@deffnx {} BFD_RELOC_ARM_GOTPC
957
These relocs are only used within the ARM assembler.  They are not
958
(at present) written to any object files.
959
@end deffn
960
@deffn {} BFD_RELOC_SH_PCDISP8BY2
961
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
962
@deffnx {} BFD_RELOC_SH_IMM4
963
@deffnx {} BFD_RELOC_SH_IMM4BY2
964
@deffnx {} BFD_RELOC_SH_IMM4BY4
965
@deffnx {} BFD_RELOC_SH_IMM8
966
@deffnx {} BFD_RELOC_SH_IMM8BY2
967
@deffnx {} BFD_RELOC_SH_IMM8BY4
968
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
969
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
970
@deffnx {} BFD_RELOC_SH_SWITCH16
971
@deffnx {} BFD_RELOC_SH_SWITCH32
972
@deffnx {} BFD_RELOC_SH_USES
973
@deffnx {} BFD_RELOC_SH_COUNT
974
@deffnx {} BFD_RELOC_SH_ALIGN
975
@deffnx {} BFD_RELOC_SH_CODE
976
@deffnx {} BFD_RELOC_SH_DATA
977
@deffnx {} BFD_RELOC_SH_LABEL
978
@deffnx {} BFD_RELOC_SH_LOOP_START
979
@deffnx {} BFD_RELOC_SH_LOOP_END
980
@deffnx {} BFD_RELOC_SH_COPY
981
@deffnx {} BFD_RELOC_SH_GLOB_DAT
982
@deffnx {} BFD_RELOC_SH_JMP_SLOT
983
@deffnx {} BFD_RELOC_SH_RELATIVE
984
@deffnx {} BFD_RELOC_SH_GOTPC
985
@deffnx {} BFD_RELOC_SH_GOT_LOW16
986
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
987
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
988
@deffnx {} BFD_RELOC_SH_GOT_HI16
989
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
990
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
991
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
992
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
993
@deffnx {} BFD_RELOC_SH_PLT_LOW16
994
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
995
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
996
@deffnx {} BFD_RELOC_SH_PLT_HI16
997
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
998
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
999
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1000
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1001
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1002
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1003
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1004
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1005
@deffnx {} BFD_RELOC_SH_COPY64
1006
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1007
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1008
@deffnx {} BFD_RELOC_SH_RELATIVE64
1009
@deffnx {} BFD_RELOC_SH_GOT10BY4
1010
@deffnx {} BFD_RELOC_SH_GOT10BY8
1011
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1012
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1013
@deffnx {} BFD_RELOC_SH_GOTPLT32
1014
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1015
@deffnx {} BFD_RELOC_SH_IMMU5
1016
@deffnx {} BFD_RELOC_SH_IMMS6
1017
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1018
@deffnx {} BFD_RELOC_SH_IMMU6
1019
@deffnx {} BFD_RELOC_SH_IMMS10
1020
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1021
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1022
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1023
@deffnx {} BFD_RELOC_SH_IMMS16
1024
@deffnx {} BFD_RELOC_SH_IMMU16
1025
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1026
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1027
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1028
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1029
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1030
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1031
@deffnx {} BFD_RELOC_SH_IMM_HI16
1032
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1033
@deffnx {} BFD_RELOC_SH_PT_16
1034
Hitachi SH relocs.  Not all of these appear in object files.
1035
@end deffn
1036
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9
1037
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1038
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1039
Thumb 23-, 12- and 9-bit pc-relative branches.  The lowest bit must
1040
be zero and is not stored in the instruction.
1041
@end deffn
1042
@deffn {} BFD_RELOC_ARC_B22_PCREL
1043
ARC Cores relocs.
1044
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1045
not stored in the instruction.  The high 20 bits are installed in bits 26
1046
through 7 of the instruction.
1047
@end deffn
1048
@deffn {} BFD_RELOC_ARC_B26
1049
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1050
stored in the instruction.  The high 24 bits are installed in bits 23
1051
through 0.
1052
@end deffn
1053
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1054
Mitsubishi D10V relocs.
1055
This is a 10-bit reloc with the right 2 bits
1056
assumed to be 0.
1057
@end deffn
1058
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1059
Mitsubishi D10V relocs.
1060
This is a 10-bit reloc with the right 2 bits
1061
assumed to be 0.  This is the same as the previous reloc
1062
except it is in the left container, i.e.,
1063
shifted left 15 bits.
1064
@end deffn
1065
@deffn {} BFD_RELOC_D10V_18
1066
This is an 18-bit reloc with the right 2 bits
1067
assumed to be 0.
1068
@end deffn
1069
@deffn {} BFD_RELOC_D10V_18_PCREL
1070
This is an 18-bit reloc with the right 2 bits
1071
assumed to be 0.
1072
@end deffn
1073
@deffn {} BFD_RELOC_D30V_6
1074
Mitsubishi D30V relocs.
1075
This is a 6-bit absolute reloc.
1076
@end deffn
1077
@deffn {} BFD_RELOC_D30V_9_PCREL
1078
This is a 6-bit pc-relative reloc with
1079
the right 3 bits assumed to be 0.
1080
@end deffn
1081
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1082
This is a 6-bit pc-relative reloc with
1083
the right 3 bits assumed to be 0. Same
1084
as the previous reloc but on the right side
1085
of the container.
1086
@end deffn
1087
@deffn {} BFD_RELOC_D30V_15
1088
This is a 12-bit absolute reloc with the
1089
right 3 bitsassumed to be 0.
1090
@end deffn
1091
@deffn {} BFD_RELOC_D30V_15_PCREL
1092
This is a 12-bit pc-relative reloc with
1093
the right 3 bits assumed to be 0.
1094
@end deffn
1095
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1096
This is a 12-bit pc-relative reloc with
1097
the right 3 bits assumed to be 0. Same
1098
as the previous reloc but on the right side
1099
of the container.
1100
@end deffn
1101
@deffn {} BFD_RELOC_D30V_21
1102
This is an 18-bit absolute reloc with
1103
the right 3 bits assumed to be 0.
1104
@end deffn
1105
@deffn {} BFD_RELOC_D30V_21_PCREL
1106
This is an 18-bit pc-relative reloc with
1107
the right 3 bits assumed to be 0.
1108
@end deffn
1109
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1110
This is an 18-bit pc-relative reloc with
1111
the right 3 bits assumed to be 0. Same
1112
as the previous reloc but on the right side
1113
of the container.
1114
@end deffn
1115
@deffn {} BFD_RELOC_D30V_32
1116
This is a 32-bit absolute reloc.
1117
@end deffn
1118
@deffn {} BFD_RELOC_D30V_32_PCREL
1119
This is a 32-bit pc-relative reloc.
1120
@end deffn
1121
@deffn {} BFD_RELOC_DLX_HI16_S
1122
DLX relocs
1123
@end deffn
1124
@deffn {} BFD_RELOC_DLX_LO16
1125
DLX relocs
1126
@end deffn
1127
@deffn {} BFD_RELOC_DLX_JMP26
1128
DLX relocs
1129
@end deffn
1130
@deffn {} BFD_RELOC_M32R_24
1131
Mitsubishi M32R relocs.
1132
This is a 24 bit absolute address.
1133
@end deffn
1134
@deffn {} BFD_RELOC_M32R_10_PCREL
1135
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1136
@end deffn
1137
@deffn {} BFD_RELOC_M32R_18_PCREL
1138
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1139
@end deffn
1140
@deffn {} BFD_RELOC_M32R_26_PCREL
1141
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1142
@end deffn
1143
@deffn {} BFD_RELOC_M32R_HI16_ULO
1144
This is a 16-bit reloc containing the high 16 bits of an address
1145
used when the lower 16 bits are treated as unsigned.
1146
@end deffn
1147
@deffn {} BFD_RELOC_M32R_HI16_SLO
1148
This is a 16-bit reloc containing the high 16 bits of an address
1149
used when the lower 16 bits are treated as signed.
1150
@end deffn
1151
@deffn {} BFD_RELOC_M32R_LO16
1152
This is a 16-bit reloc containing the lower 16 bits of an address.
1153
@end deffn
1154
@deffn {} BFD_RELOC_M32R_SDA16
1155
This is a 16-bit reloc containing the small data area offset for use in
1156
add3, load, and store instructions.
1157
@end deffn
1158
@deffn {} BFD_RELOC_V850_9_PCREL
1159
This is a 9-bit reloc
1160
@end deffn
1161
@deffn {} BFD_RELOC_V850_22_PCREL
1162
This is a 22-bit reloc
1163
@end deffn
1164
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1165
This is a 16 bit offset from the short data area pointer.
1166
@end deffn
1167
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1168
This is a 16 bit offset (of which only 15 bits are used) from the
1169
short data area pointer.
1170
@end deffn
1171
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1172
This is a 16 bit offset from the zero data area pointer.
1173
@end deffn
1174
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1175
This is a 16 bit offset (of which only 15 bits are used) from the
1176
zero data area pointer.
1177
@end deffn
1178
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1179
This is an 8 bit offset (of which only 6 bits are used) from the
1180
tiny data area pointer.
1181
@end deffn
1182
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1183
This is an 8bit offset (of which only 7 bits are used) from the tiny
1184
data area pointer.
1185
@end deffn
1186
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1187
This is a 7 bit offset from the tiny data area pointer.
1188
@end deffn
1189
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1190
This is a 16 bit offset from the tiny data area pointer.
1191
@end deffn
1192
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1193
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1194
data area pointer.
1195
@end deffn
1196
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1197
This is a 4 bit offset from the tiny data area pointer.
1198
@end deffn
1199
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1200
This is a 16 bit offset from the short data area pointer, with the
1201
bits placed non-contigously in the instruction.
1202
@end deffn
1203
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1204
This is a 16 bit offset from the zero data area pointer, with the
1205
bits placed non-contigously in the instruction.
1206
@end deffn
1207
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1208
This is a 6 bit offset from the call table base pointer.
1209
@end deffn
1210
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1211
This is a 16 bit offset from the call table base pointer.
1212
@end deffn
1213
@deffn {} BFD_RELOC_V850_LONGCALL
1214
Used for relaxing indirect function calls.
1215
@end deffn
1216
@deffn {} BFD_RELOC_V850_LONGJUMP
1217
Used for relaxing indirect jumps.
1218
@end deffn
1219
@deffn {} BFD_RELOC_V850_ALIGN
1220
Used to maintain alignment whilst relaxing.
1221
@end deffn
1222
@deffn {} BFD_RELOC_MN10300_32_PCREL
1223
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1224
instruction.
1225
@end deffn
1226
@deffn {} BFD_RELOC_MN10300_16_PCREL
1227
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1228
instruction.
1229
@end deffn
1230
@deffn {} BFD_RELOC_TIC30_LDP
1231
This is a 8bit DP reloc for the tms320c30, where the most
1232
significant 8 bits of a 24 bit word are placed into the least
1233
significant 8 bits of the opcode.
1234
@end deffn
1235
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1236
This is a 7bit reloc for the tms320c54x, where the least
1237
significant 7 bits of a 16 bit word are placed into the least
1238
significant 7 bits of the opcode.
1239
@end deffn
1240
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1241
This is a 9bit DP reloc for the tms320c54x, where the most
1242
significant 9 bits of a 16 bit word are placed into the least
1243
significant 9 bits of the opcode.
1244
@end deffn
1245
@deffn {} BFD_RELOC_TIC54X_23
1246
This is an extended address 23-bit reloc for the tms320c54x.
1247
@end deffn
1248
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1249
This is a 16-bit reloc for the tms320c54x, where the least
1250
significant 16 bits of a 23-bit extended address are placed into
1251
the opcode.
1252
@end deffn
1253
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1254
This is a reloc for the tms320c54x, where the most
1255
significant 7 bits of a 23-bit extended address are placed into
1256
the opcode.
1257
@end deffn
1258
@deffn {} BFD_RELOC_FR30_48
1259
This is a 48 bit reloc for the FR30 that stores 32 bits.
1260
@end deffn
1261
@deffn {} BFD_RELOC_FR30_20
1262
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1263
two sections.
1264
@end deffn
1265
@deffn {} BFD_RELOC_FR30_6_IN_4
1266
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1267
4 bits.
1268
@end deffn
1269
@deffn {} BFD_RELOC_FR30_8_IN_8
1270
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1271
into 8 bits.
1272
@end deffn
1273
@deffn {} BFD_RELOC_FR30_9_IN_8
1274
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1275
into 8 bits.
1276
@end deffn
1277
@deffn {} BFD_RELOC_FR30_10_IN_8
1278
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1279
into 8 bits.
1280
@end deffn
1281
@deffn {} BFD_RELOC_FR30_9_PCREL
1282
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1283
short offset into 8 bits.
1284
@end deffn
1285
@deffn {} BFD_RELOC_FR30_12_PCREL
1286
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1287
short offset into 11 bits.
1288
@end deffn
1289
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1290
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1291
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1292
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1293
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1294
@deffnx {} BFD_RELOC_MCORE_RVA
1295
Motorola Mcore relocations.
1296
@end deffn
1297
@deffn {} BFD_RELOC_MMIX_GETA
1298
@deffnx {} BFD_RELOC_MMIX_GETA_1
1299
@deffnx {} BFD_RELOC_MMIX_GETA_2
1300
@deffnx {} BFD_RELOC_MMIX_GETA_3
1301
These are relocations for the GETA instruction.
1302
@end deffn
1303
@deffn {} BFD_RELOC_MMIX_CBRANCH
1304
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1305
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1306
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1307
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1308
These are relocations for a conditional branch instruction.
1309
@end deffn
1310
@deffn {} BFD_RELOC_MMIX_PUSHJ
1311
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1312
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1313
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1314
These are relocations for the PUSHJ instruction.
1315
@end deffn
1316
@deffn {} BFD_RELOC_MMIX_JMP
1317
@deffnx {} BFD_RELOC_MMIX_JMP_1
1318
@deffnx {} BFD_RELOC_MMIX_JMP_2
1319
@deffnx {} BFD_RELOC_MMIX_JMP_3
1320
These are relocations for the JMP instruction.
1321
@end deffn
1322
@deffn {} BFD_RELOC_MMIX_ADDR19
1323
This is a relocation for a relative address as in a GETA instruction or
1324
a branch.
1325
@end deffn
1326
@deffn {} BFD_RELOC_MMIX_ADDR27
1327
This is a relocation for a relative address as in a JMP instruction.
1328
@end deffn
1329
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1330
This is a relocation for an instruction field that may be a general
1331
register or a value 0..255.
1332
@end deffn
1333
@deffn {} BFD_RELOC_MMIX_REG
1334
This is a relocation for an instruction field that may be a general
1335
register.
1336
@end deffn
1337
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1338
This is a relocation for two instruction fields holding a register and
1339
an offset, the equivalent of the relocation.
1340
@end deffn
1341
@deffn {} BFD_RELOC_MMIX_LOCAL
1342
This relocation is an assertion that the expression is not allocated as
1343
a global register.  It does not modify contents.
1344
@end deffn
1345
@deffn {} BFD_RELOC_AVR_7_PCREL
1346
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1347
short offset into 7 bits.
1348
@end deffn
1349
@deffn {} BFD_RELOC_AVR_13_PCREL
1350
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1351
short offset into 12 bits.
1352
@end deffn
1353
@deffn {} BFD_RELOC_AVR_16_PM
1354
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1355
program memory address) into 16 bits.
1356
@end deffn
1357
@deffn {} BFD_RELOC_AVR_LO8_LDI
1358
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1359
data memory address) into 8 bit immediate value of LDI insn.
1360
@end deffn
1361
@deffn {} BFD_RELOC_AVR_HI8_LDI
1362
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1363
of data memory address) into 8 bit immediate value of LDI insn.
1364
@end deffn
1365
@deffn {} BFD_RELOC_AVR_HH8_LDI
1366
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1367
of program memory address) into 8 bit immediate value of LDI insn.
1368
@end deffn
1369
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1370
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1371
(usually data memory address) into 8 bit immediate value of SUBI insn.
1372
@end deffn
1373
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1374
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1375
(high 8 bit of data memory address) into 8 bit immediate value of
1376
SUBI insn.
1377
@end deffn
1378
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1379
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1380
(most high 8 bit of program memory address) into 8 bit immediate value
1381
of LDI or SUBI insn.
1382
@end deffn
1383
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1384
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1385
command address) into 8 bit immediate value of LDI insn.
1386
@end deffn
1387
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1388
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1389
of command address) into 8 bit immediate value of LDI insn.
1390
@end deffn
1391
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1392
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1393
of command address) into 8 bit immediate value of LDI insn.
1394
@end deffn
1395
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1396
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1397
(usually command address) into 8 bit immediate value of SUBI insn.
1398
@end deffn
1399
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1400
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1401
(high 8 bit of 16 bit command address) into 8 bit immediate value
1402
of SUBI insn.
1403
@end deffn
1404
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1405
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1406
(high 6 bit of 22 bit command address) into 8 bit immediate
1407
value of SUBI insn.
1408
@end deffn
1409
@deffn {} BFD_RELOC_AVR_CALL
1410
This is a 32 bit reloc for the AVR that stores 23 bit value
1411
into 22 bits.
1412
@end deffn
1413
@deffn {} BFD_RELOC_390_12
1414
Direct 12 bit.
1415
@end deffn
1416
@deffn {} BFD_RELOC_390_GOT12
1417
12 bit GOT offset.
1418
@end deffn
1419
@deffn {} BFD_RELOC_390_PLT32
1420
32 bit PC relative PLT address.
1421
@end deffn
1422
@deffn {} BFD_RELOC_390_COPY
1423
Copy symbol at runtime.
1424
@end deffn
1425
@deffn {} BFD_RELOC_390_GLOB_DAT
1426
Create GOT entry.
1427
@end deffn
1428
@deffn {} BFD_RELOC_390_JMP_SLOT
1429
Create PLT entry.
1430
@end deffn
1431
@deffn {} BFD_RELOC_390_RELATIVE
1432
Adjust by program base.
1433
@end deffn
1434
@deffn {} BFD_RELOC_390_GOTPC
1435
32 bit PC relative offset to GOT.
1436
@end deffn
1437
@deffn {} BFD_RELOC_390_GOT16
1438
16 bit GOT offset.
1439
@end deffn
1440
@deffn {} BFD_RELOC_390_PC16DBL
1441
PC relative 16 bit shifted by 1.
1442
@end deffn
1443
@deffn {} BFD_RELOC_390_PLT16DBL
1444
16 bit PC rel. PLT shifted by 1.
1445
@end deffn
1446
@deffn {} BFD_RELOC_390_PC32DBL
1447
PC relative 32 bit shifted by 1.
1448
@end deffn
1449
@deffn {} BFD_RELOC_390_PLT32DBL
1450
32 bit PC rel. PLT shifted by 1.
1451
@end deffn
1452
@deffn {} BFD_RELOC_390_GOTPCDBL
1453
32 bit PC rel. GOT shifted by 1.
1454
@end deffn
1455
@deffn {} BFD_RELOC_390_GOT64
1456
64 bit GOT offset.
1457
@end deffn
1458
@deffn {} BFD_RELOC_390_PLT64
1459
64 bit PC relative PLT address.
1460
@end deffn
1461
@deffn {} BFD_RELOC_390_GOTENT
1462
32 bit rel. offset to GOT entry.
1463
@end deffn
1464
@deffn {} BFD_RELOC_IP2K_FR9
1465
Scenix IP2K - 9-bit register number / data address
1466
@end deffn
1467
@deffn {} BFD_RELOC_IP2K_BANK
1468
Scenix IP2K - 4-bit register/data bank number
1469
@end deffn
1470
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
1471
Scenix IP2K - low 13 bits of instruction word address
1472
@end deffn
1473
@deffn {} BFD_RELOC_IP2K_PAGE3
1474
Scenix IP2K - high 3 bits of instruction word address
1475
@end deffn
1476
@deffn {} BFD_RELOC_IP2K_LO8DATA
1477
@deffnx {} BFD_RELOC_IP2K_HI8DATA
1478
@deffnx {} BFD_RELOC_IP2K_EX8DATA
1479
Scenix IP2K - ext/low/high 8 bits of data address
1480
@end deffn
1481
@deffn {} BFD_RELOC_IP2K_LO8INSN
1482
@deffnx {} BFD_RELOC_IP2K_HI8INSN
1483
Scenix IP2K - low/high 8 bits of instruction word address
1484
@end deffn
1485
@deffn {} BFD_RELOC_IP2K_PC_SKIP
1486
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
1487
@end deffn
1488
@deffn {} BFD_RELOC_IP2K_TEXT
1489
Scenix IP2K - 16 bit word address in text section.
1490
@end deffn
1491
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
1492
Scenix IP2K - 7-bit sp or dp offset
1493
@end deffn
1494
@deffn {} BFD_RELOC_VPE4KMATH_DATA
1495
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
1496
Scenix VPE4K coprocessor - data/insn-space addressing
1497
@end deffn
1498
@deffn {} BFD_RELOC_VTABLE_INHERIT
1499
@deffnx {} BFD_RELOC_VTABLE_ENTRY
1500
These two relocations are used by the linker to determine which of
1501
the entries in a C++ virtual function table are actually used.  When
1502
the --gc-sections option is given, the linker will zero out the entries
1503
that are not used, so that the code for those functions need not be
1504
included in the output.
1505
 
1506
VTABLE_INHERIT is a zero-space relocation used to describe to the
1507
linker the inheritence tree of a C++ virtual function table.  The
1508
relocation's symbol should be the parent class' vtable, and the
1509
relocation should be located at the child vtable.
1510
 
1511
VTABLE_ENTRY is a zero-space relocation that describes the use of a
1512
virtual function table entry.  The reloc's symbol should refer to the
1513
table of the class mentioned in the code.  Off of that base, an offset
1514
describes the entry that is being used.  For Rela hosts, this offset
1515
is stored in the reloc's addend.  For Rel hosts, we are forced to put
1516
this offset in the reloc's section offset.
1517
@end deffn
1518
@deffn {} BFD_RELOC_IA64_IMM14
1519
@deffnx {} BFD_RELOC_IA64_IMM22
1520
@deffnx {} BFD_RELOC_IA64_IMM64
1521
@deffnx {} BFD_RELOC_IA64_DIR32MSB
1522
@deffnx {} BFD_RELOC_IA64_DIR32LSB
1523
@deffnx {} BFD_RELOC_IA64_DIR64MSB
1524
@deffnx {} BFD_RELOC_IA64_DIR64LSB
1525
@deffnx {} BFD_RELOC_IA64_GPREL22
1526
@deffnx {} BFD_RELOC_IA64_GPREL64I
1527
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
1528
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
1529
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
1530
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
1531
@deffnx {} BFD_RELOC_IA64_LTOFF22
1532
@deffnx {} BFD_RELOC_IA64_LTOFF64I
1533
@deffnx {} BFD_RELOC_IA64_PLTOFF22
1534
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
1535
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
1536
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
1537
@deffnx {} BFD_RELOC_IA64_FPTR64I
1538
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
1539
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
1540
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
1541
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
1542
@deffnx {} BFD_RELOC_IA64_PCREL21B
1543
@deffnx {} BFD_RELOC_IA64_PCREL21BI
1544
@deffnx {} BFD_RELOC_IA64_PCREL21M
1545
@deffnx {} BFD_RELOC_IA64_PCREL21F
1546
@deffnx {} BFD_RELOC_IA64_PCREL22
1547
@deffnx {} BFD_RELOC_IA64_PCREL60B
1548
@deffnx {} BFD_RELOC_IA64_PCREL64I
1549
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
1550
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
1551
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
1552
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
1553
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
1554
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
1555
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
1556
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
1557
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
1558
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
1559
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
1560
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
1561
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
1562
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
1563
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
1564
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
1565
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
1566
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
1567
@deffnx {} BFD_RELOC_IA64_REL32MSB
1568
@deffnx {} BFD_RELOC_IA64_REL32LSB
1569
@deffnx {} BFD_RELOC_IA64_REL64MSB
1570
@deffnx {} BFD_RELOC_IA64_REL64LSB
1571
@deffnx {} BFD_RELOC_IA64_LTV32MSB
1572
@deffnx {} BFD_RELOC_IA64_LTV32LSB
1573
@deffnx {} BFD_RELOC_IA64_LTV64MSB
1574
@deffnx {} BFD_RELOC_IA64_LTV64LSB
1575
@deffnx {} BFD_RELOC_IA64_IPLTMSB
1576
@deffnx {} BFD_RELOC_IA64_IPLTLSB
1577
@deffnx {} BFD_RELOC_IA64_COPY
1578
@deffnx {} BFD_RELOC_IA64_LTOFF22X
1579
@deffnx {} BFD_RELOC_IA64_LDXMOV
1580
@deffnx {} BFD_RELOC_IA64_TPREL14
1581
@deffnx {} BFD_RELOC_IA64_TPREL22
1582
@deffnx {} BFD_RELOC_IA64_TPREL64I
1583
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
1584
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
1585
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
1586
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
1587
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
1588
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
1589
@deffnx {} BFD_RELOC_IA64_DTPREL14
1590
@deffnx {} BFD_RELOC_IA64_DTPREL22
1591
@deffnx {} BFD_RELOC_IA64_DTPREL64I
1592
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
1593
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
1594
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
1595
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
1596
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
1597
Intel IA64 Relocations.
1598
@end deffn
1599
@deffn {} BFD_RELOC_M68HC11_HI8
1600
Motorola 68HC11 reloc.
1601
This is the 8 bit high part of an absolute address.
1602
@end deffn
1603
@deffn {} BFD_RELOC_M68HC11_LO8
1604
Motorola 68HC11 reloc.
1605
This is the 8 bit low part of an absolute address.
1606
@end deffn
1607
@deffn {} BFD_RELOC_M68HC11_3B
1608
Motorola 68HC11 reloc.
1609
This is the 3 bit of a value.
1610
@end deffn
1611
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
1612
Motorola 68HC11 reloc.
1613
This reloc marks the beginning of a jump/call instruction.
1614
It is used for linker relaxation to correctly identify beginning
1615
of instruction and change some branchs to use PC-relative
1616
addressing mode.
1617
@end deffn
1618
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
1619
Motorola 68HC11 reloc.
1620
This reloc marks a group of several instructions that gcc generates
1621
and for which the linker relaxation pass can modify and/or remove
1622
some of them.
1623
@end deffn
1624
@deffn {} BFD_RELOC_M68HC11_LO16
1625
Motorola 68HC11 reloc.
1626
This is the 16-bit lower part of an address.  It is used for 'call'
1627
instruction to specify the symbol address without any special
1628
transformation (due to memory bank window).
1629
@end deffn
1630
@deffn {} BFD_RELOC_M68HC11_PAGE
1631
Motorola 68HC11 reloc.
1632
This is a 8-bit reloc that specifies the page number of an address.
1633
It is used by 'call' instruction to specify the page number of
1634
the symbol.
1635
@end deffn
1636
@deffn {} BFD_RELOC_M68HC11_24
1637
Motorola 68HC11 reloc.
1638
This is a 24-bit reloc that represents the address with a 16-bit
1639
value and a 8-bit page number.  The symbol address is transformed
1640
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
1641
@end deffn
1642
@deffn {} BFD_RELOC_CRIS_BDISP8
1643
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
1644
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
1645
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
1646
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
1647
These relocs are only used within the CRIS assembler.  They are not
1648
(at present) written to any object files.
1649
@end deffn
1650
@deffn {} BFD_RELOC_CRIS_COPY
1651
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
1652
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
1653
@deffnx {} BFD_RELOC_CRIS_RELATIVE
1654
Relocs used in ELF shared libraries for CRIS.
1655
@end deffn
1656
@deffn {} BFD_RELOC_CRIS_32_GOT
1657
32-bit offset to symbol-entry within GOT.
1658
@end deffn
1659
@deffn {} BFD_RELOC_CRIS_16_GOT
1660
16-bit offset to symbol-entry within GOT.
1661
@end deffn
1662
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
1663
32-bit offset to symbol-entry within GOT, with PLT handling.
1664
@end deffn
1665
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
1666
16-bit offset to symbol-entry within GOT, with PLT handling.
1667
@end deffn
1668
@deffn {} BFD_RELOC_CRIS_32_GOTREL
1669
32-bit offset to symbol, relative to GOT.
1670
@end deffn
1671
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
1672
32-bit offset to symbol with PLT entry, relative to GOT.
1673
@end deffn
1674
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
1675
32-bit offset to symbol with PLT entry, relative to this relocation.
1676
@end deffn
1677
@deffn {} BFD_RELOC_860_COPY
1678
@deffnx {} BFD_RELOC_860_GLOB_DAT
1679
@deffnx {} BFD_RELOC_860_JUMP_SLOT
1680
@deffnx {} BFD_RELOC_860_RELATIVE
1681
@deffnx {} BFD_RELOC_860_PC26
1682
@deffnx {} BFD_RELOC_860_PLT26
1683
@deffnx {} BFD_RELOC_860_PC16
1684
@deffnx {} BFD_RELOC_860_LOW0
1685
@deffnx {} BFD_RELOC_860_SPLIT0
1686
@deffnx {} BFD_RELOC_860_LOW1
1687
@deffnx {} BFD_RELOC_860_SPLIT1
1688
@deffnx {} BFD_RELOC_860_LOW2
1689
@deffnx {} BFD_RELOC_860_SPLIT2
1690
@deffnx {} BFD_RELOC_860_LOW3
1691
@deffnx {} BFD_RELOC_860_LOGOT0
1692
@deffnx {} BFD_RELOC_860_SPGOT0
1693
@deffnx {} BFD_RELOC_860_LOGOT1
1694
@deffnx {} BFD_RELOC_860_SPGOT1
1695
@deffnx {} BFD_RELOC_860_LOGOTOFF0
1696
@deffnx {} BFD_RELOC_860_SPGOTOFF0
1697
@deffnx {} BFD_RELOC_860_LOGOTOFF1
1698
@deffnx {} BFD_RELOC_860_SPGOTOFF1
1699
@deffnx {} BFD_RELOC_860_LOGOTOFF2
1700
@deffnx {} BFD_RELOC_860_LOGOTOFF3
1701
@deffnx {} BFD_RELOC_860_LOPC
1702
@deffnx {} BFD_RELOC_860_HIGHADJ
1703
@deffnx {} BFD_RELOC_860_HAGOT
1704
@deffnx {} BFD_RELOC_860_HAGOTOFF
1705
@deffnx {} BFD_RELOC_860_HAPC
1706
@deffnx {} BFD_RELOC_860_HIGH
1707
@deffnx {} BFD_RELOC_860_HIGOT
1708
@deffnx {} BFD_RELOC_860_HIGOTOFF
1709
Intel i860 Relocations.
1710
@end deffn
1711
@deffn {} BFD_RELOC_OPENRISC_ABS_26
1712
@deffnx {} BFD_RELOC_OPENRISC_REL_26
1713
OpenRISC Relocations.
1714
@end deffn
1715
@deffn {} BFD_RELOC_H8_DIR16A8
1716
@deffnx {} BFD_RELOC_H8_DIR16R8
1717
@deffnx {} BFD_RELOC_H8_DIR24A8
1718
@deffnx {} BFD_RELOC_H8_DIR24R8
1719
@deffnx {} BFD_RELOC_H8_DIR32A16
1720
H8 elf Relocations.
1721
@end deffn
1722
@deffn {} BFD_RELOC_XSTORMY16_REL_12
1723
@deffnx {} BFD_RELOC_XSTORMY16_24
1724
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
1725
Sony Xstormy16 Relocations.
1726
@end deffn
1727
@deffn {} BFD_RELOC_VAX_GLOB_DAT
1728
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
1729
@deffnx {} BFD_RELOC_VAX_RELATIVE
1730
Relocations used by VAX ELF.
1731
@end deffn
1732
 
1733
@example
1734
 
1735
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
1736
@end example
1737
@findex bfd_reloc_type_lookup
1738
@subsubsection @code{bfd_reloc_type_lookup}
1739
@strong{Synopsis}
1740
@example
1741
reloc_howto_type *
1742
bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code);
1743
@end example
1744
@strong{Description}@*
1745
Return a pointer to a howto structure which, when
1746
invoked, will perform the relocation @var{code} on data from the
1747
architecture noted.
1748
 
1749
@findex bfd_default_reloc_type_lookup
1750
@subsubsection @code{bfd_default_reloc_type_lookup}
1751
@strong{Synopsis}
1752
@example
1753
reloc_howto_type *bfd_default_reloc_type_lookup
1754
   (bfd *abfd, bfd_reloc_code_real_type  code);
1755
@end example
1756
@strong{Description}@*
1757
Provides a default relocation lookup routine for any architecture.
1758
 
1759
@findex bfd_get_reloc_code_name
1760
@subsubsection @code{bfd_get_reloc_code_name}
1761
@strong{Synopsis}
1762
@example
1763
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
1764
@end example
1765
@strong{Description}@*
1766
Provides a printable name for the supplied relocation code.
1767
Useful mainly for printing error messages.
1768
 
1769
@findex bfd_generic_relax_section
1770
@subsubsection @code{bfd_generic_relax_section}
1771
@strong{Synopsis}
1772
@example
1773
boolean bfd_generic_relax_section
1774
   (bfd *abfd,
1775
    asection *section,
1776
    struct bfd_link_info *,
1777
    boolean *);
1778
@end example
1779
@strong{Description}@*
1780
Provides default handling for relaxing for back ends which
1781
don't do relaxing -- i.e., does nothing.
1782
 
1783
@findex bfd_generic_gc_sections
1784
@subsubsection @code{bfd_generic_gc_sections}
1785
@strong{Synopsis}
1786
@example
1787
boolean bfd_generic_gc_sections
1788
   (bfd *, struct bfd_link_info *);
1789
@end example
1790
@strong{Description}@*
1791
Provides default handling for relaxing for back ends which
1792
don't do section gc -- i.e., does nothing.
1793
 
1794
@findex bfd_generic_merge_sections
1795
@subsubsection @code{bfd_generic_merge_sections}
1796
@strong{Synopsis}
1797
@example
1798
boolean bfd_generic_merge_sections
1799
   (bfd *, struct bfd_link_info *);
1800
@end example
1801
@strong{Description}@*
1802
Provides default handling for SEC_MERGE section merging for back ends
1803
which don't have SEC_MERGE support -- i.e., does nothing.
1804
 
1805
@findex bfd_generic_get_relocated_section_contents
1806
@subsubsection @code{bfd_generic_get_relocated_section_contents}
1807
@strong{Synopsis}
1808
@example
1809
bfd_byte *
1810
bfd_generic_get_relocated_section_contents (bfd *abfd,
1811
    struct bfd_link_info *link_info,
1812
    struct bfd_link_order *link_order,
1813
    bfd_byte *data,
1814
    boolean relocateable,
1815
    asymbol **symbols);
1816
@end example
1817
@strong{Description}@*
1818
Provides default handling of relocation effort for back ends
1819
which can't be bothered to do it efficiently.
1820
 

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