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1181 |
sfurman |
/* Common target dependent code for GDB on ARM systems.
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Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
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2001, 2002 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <ctype.h> /* XXX for isupper () */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "gdbcmd.h"
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#include "gdbcore.h"
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#include "symfile.h"
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#include "gdb_string.h"
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#include "dis-asm.h" /* For register flavors. */
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#include "regcache.h"
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#include "doublest.h"
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#include "value.h"
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#include "arch-utils.h"
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#include "solib-svr4.h"
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#include "arm-tdep.h"
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#include "gdb/sim-arm.h"
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#include "elf-bfd.h"
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#include "coff/internal.h"
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#include "elf/arm.h"
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#include "gdb_assert.h"
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static int arm_debug;
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/* Each OS has a different mechanism for accessing the various
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registers stored in the sigcontext structure.
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SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
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function pointer) which may be used to determine the addresses
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of the various saved registers in the sigcontext structure.
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For the ARM target, there are three parameters to this function.
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The first is the pc value of the frame under consideration, the
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second the stack pointer of this frame, and the last is the
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register number to fetch.
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If the tm.h file does not define this macro, then it's assumed that
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no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
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be 0.
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When it comes time to multi-arching this code, see the identically
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named machinery in ia64-tdep.c for an example of how it could be
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done. It should not be necessary to modify the code below where
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this macro is used. */
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#ifdef SIGCONTEXT_REGISTER_ADDRESS
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#ifndef SIGCONTEXT_REGISTER_ADDRESS_P
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#define SIGCONTEXT_REGISTER_ADDRESS_P() 1
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#endif
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#else
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#define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
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#define SIGCONTEXT_REGISTER_ADDRESS_P() 0
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#endif
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/* Macros for setting and testing a bit in a minimal symbol that marks
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it as Thumb function. The MSB of the minimal symbol's "info" field
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is used for this purpose. This field is already being used to store
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the symbol size, so the assumption is that the symbol size cannot
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exceed 2^31.
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MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
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MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
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MSYMBOL_SIZE Returns the size of the minimal symbol,
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i.e. the "info" field with the "special" bit
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masked out. */
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#define MSYMBOL_SET_SPECIAL(msym) \
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MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
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| 0x80000000)
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#define MSYMBOL_IS_SPECIAL(msym) \
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(((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
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#define MSYMBOL_SIZE(msym) \
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((long) MSYMBOL_INFO (msym) & 0x7fffffff)
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/* Number of different reg name sets (options). */
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static int num_flavor_options;
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/* We have more registers than the disassembler as gdb can print the value
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of special registers as well.
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The general register names are overwritten by whatever is being used by
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the disassembler at the moment. We also adjust the case of cpsr and fps. */
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/* Initial value: Register names used in ARM's ISA documentation. */
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static char * arm_register_name_strings[] =
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{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
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"r4", "r5", "r6", "r7", /* 4 5 6 7 */
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"r8", "r9", "r10", "r11", /* 8 9 10 11 */
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"r12", "sp", "lr", "pc", /* 12 13 14 15 */
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"f0", "f1", "f2", "f3", /* 16 17 18 19 */
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"f4", "f5", "f6", "f7", /* 20 21 22 23 */
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"fps", "cpsr" }; /* 24 25 */
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static char **arm_register_names = arm_register_name_strings;
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/* Valid register name flavors. */
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static const char **valid_flavors;
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/* Disassembly flavor to use. Default to "std" register names. */
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static const char *disassembly_flavor;
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/* Index to that option in the opcodes table. */
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static int current_option;
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/* This is used to keep the bfd arch_info in sync with the disassembly
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flavor. */
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static void set_disassembly_flavor_sfunc(char *, int,
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struct cmd_list_element *);
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static void set_disassembly_flavor (void);
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static void convert_from_extended (void *ptr, void *dbl);
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/* Define other aspects of the stack frame. We keep the offsets of
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all saved registers, 'cause we need 'em a lot! We also keep the
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current size of the stack frame, and the offset of the frame
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pointer from the stack pointer (for frameless functions, and when
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we're still in the prologue of a function with a frame). */
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struct frame_extra_info
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{
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int framesize;
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int frameoffset;
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int framereg;
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};
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/* Addresses for calling Thumb functions have the bit 0 set.
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Here are some macros to test, set, or clear bit 0 of addresses. */
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#define IS_THUMB_ADDR(addr) ((addr) & 1)
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#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
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#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
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static int
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arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
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{
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return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
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}
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/* Set to true if the 32-bit mode is in use. */
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int arm_apcs_32 = 1;
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/* Flag set by arm_fix_call_dummy that tells whether the target
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function is a Thumb function. This flag is checked by
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arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
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its use in valops.c) to pass the function address as an additional
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parameter. */
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static int target_is_thumb;
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/* Flag set by arm_fix_call_dummy that tells whether the calling
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function is a Thumb function. This flag is checked by
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arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
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static int caller_is_thumb;
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/* Determine if the program counter specified in MEMADDR is in a Thumb
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function. */
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int
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arm_pc_is_thumb (CORE_ADDR memaddr)
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{
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struct minimal_symbol *sym;
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/* If bit 0 of the address is set, assume this is a Thumb address. */
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if (IS_THUMB_ADDR (memaddr))
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return 1;
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/* Thumb functions have a "special" bit set in minimal symbols. */
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sym = lookup_minimal_symbol_by_pc (memaddr);
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if (sym)
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{
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return (MSYMBOL_IS_SPECIAL (sym));
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}
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else
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{
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return 0;
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}
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}
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/* Determine if the program counter specified in MEMADDR is in a call
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dummy being called from a Thumb function. */
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int
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arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
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{
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CORE_ADDR sp = read_sp ();
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/* FIXME: Until we switch for the new call dummy macros, this heuristic
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is the best we can do. We are trying to determine if the pc is on
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the stack, which (hopefully) will only happen in a call dummy.
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We hope the current stack pointer is not so far alway from the dummy
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frame location (true if we have not pushed large data structures or
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gone too many levels deep) and that our 1024 is not enough to consider
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code regions as part of the stack (true for most practical purposes). */
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if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
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return caller_is_thumb;
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else
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return 0;
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}
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/* Remove useless bits from addresses in a running program. */
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static CORE_ADDR
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arm_addr_bits_remove (CORE_ADDR val)
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{
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if (arm_pc_is_thumb (val))
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return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
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else
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return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
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}
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/* When reading symbols, we need to zap the low bit of the address,
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which may be set to 1 for Thumb functions. */
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static CORE_ADDR
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arm_smash_text_address (CORE_ADDR val)
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{
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return val & ~1;
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}
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/* Immediately after a function call, return the saved pc. Can't
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always go through the frames for this because on some machines the
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new frame is not set up until the new function executes some
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instructions. */
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static CORE_ADDR
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arm_saved_pc_after_call (struct frame_info *frame)
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{
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return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
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}
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/* Determine whether the function invocation represented by FI has a
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frame on the stack associated with it. If it does return zero,
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otherwise return 1. */
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static int
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arm_frameless_function_invocation (struct frame_info *fi)
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{
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CORE_ADDR func_start, after_prologue;
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int frameless;
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/* Sometimes we have functions that do a little setup (like saving the
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vN registers with the stmdb instruction, but DO NOT set up a frame.
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The symbol table will report this as a prologue. However, it is
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important not to try to parse these partial frames as frames, or we
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will get really confused.
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So I will demand 3 instructions between the start & end of the
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prologue before I call it a real prologue, i.e. at least
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mov ip, sp,
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stmdb sp!, {}
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sub sp, ip, #4. */
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func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
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after_prologue = SKIP_PROLOGUE (func_start);
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/* There are some frameless functions whose first two instructions
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follow the standard APCS form, in which case after_prologue will
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be func_start + 8. */
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frameless = (after_prologue < func_start + 12);
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return frameless;
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}
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/* The address of the arguments in the frame. */
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static CORE_ADDR
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arm_frame_args_address (struct frame_info *fi)
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{
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return fi->frame;
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}
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/* The address of the local variables in the frame. */
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static CORE_ADDR
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arm_frame_locals_address (struct frame_info *fi)
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{
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return fi->frame;
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}
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/* The number of arguments being passed in the frame. */
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static int
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arm_frame_num_args (struct frame_info *fi)
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{
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/* We have no way of knowing. */
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return -1;
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}
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/* A typical Thumb prologue looks like this:
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push {r7, lr}
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add sp, sp, #-28
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add r7, sp, #12
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Sometimes the latter instruction may be replaced by:
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mov r7, sp
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or like this:
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push {r7, lr}
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mov r7, sp
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sub sp, #12
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or, on tpcs, like this:
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sub sp,#16
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push {r7, lr}
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(many instructions)
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mov r7, sp
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sub sp, #12
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There is always one instruction of three classes:
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1 - push
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2 - setting of r7
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3 - adjusting of sp
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When we have found at least one of each class we are done with the prolog.
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Note that the "sub sp, #NN" before the push does not count.
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*/
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static CORE_ADDR
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thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
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{
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CORE_ADDR current_pc;
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/* findmask:
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bit 0 - push { rlist }
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bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
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bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
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*/
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int findmask = 0;
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for (current_pc = pc;
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current_pc + 2 < func_end && current_pc < pc + 40;
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current_pc += 2)
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{
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unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
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if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
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{
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|
|
findmask |= 1; /* push found */
|
356 |
|
|
}
|
357 |
|
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
|
358 |
|
|
sub sp, #simm */
|
359 |
|
|
{
|
360 |
|
|
if ((findmask & 1) == 0) /* before push ? */
|
361 |
|
|
continue;
|
362 |
|
|
else
|
363 |
|
|
findmask |= 4; /* add/sub sp found */
|
364 |
|
|
}
|
365 |
|
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
366 |
|
|
{
|
367 |
|
|
findmask |= 2; /* setting of r7 found */
|
368 |
|
|
}
|
369 |
|
|
else if (insn == 0x466f) /* mov r7, sp */
|
370 |
|
|
{
|
371 |
|
|
findmask |= 2; /* setting of r7 found */
|
372 |
|
|
}
|
373 |
|
|
else if (findmask == (4+2+1))
|
374 |
|
|
{
|
375 |
|
|
/* We have found one of each type of prologue instruction */
|
376 |
|
|
break;
|
377 |
|
|
}
|
378 |
|
|
else
|
379 |
|
|
/* Something in the prolog that we don't care about or some
|
380 |
|
|
instruction from outside the prolog scheduled here for
|
381 |
|
|
optimization. */
|
382 |
|
|
continue;
|
383 |
|
|
}
|
384 |
|
|
|
385 |
|
|
return current_pc;
|
386 |
|
|
}
|
387 |
|
|
|
388 |
|
|
/* Advance the PC across any function entry prologue instructions to
|
389 |
|
|
reach some "real" code.
|
390 |
|
|
|
391 |
|
|
The APCS (ARM Procedure Call Standard) defines the following
|
392 |
|
|
prologue:
|
393 |
|
|
|
394 |
|
|
mov ip, sp
|
395 |
|
|
[stmfd sp!, {a1,a2,a3,a4}]
|
396 |
|
|
stmfd sp!, {...,fp,ip,lr,pc}
|
397 |
|
|
[stfe f7, [sp, #-12]!]
|
398 |
|
|
[stfe f6, [sp, #-12]!]
|
399 |
|
|
[stfe f5, [sp, #-12]!]
|
400 |
|
|
[stfe f4, [sp, #-12]!]
|
401 |
|
|
sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
|
402 |
|
|
|
403 |
|
|
static CORE_ADDR
|
404 |
|
|
arm_skip_prologue (CORE_ADDR pc)
|
405 |
|
|
{
|
406 |
|
|
unsigned long inst;
|
407 |
|
|
CORE_ADDR skip_pc;
|
408 |
|
|
CORE_ADDR func_addr, func_end = 0;
|
409 |
|
|
char *func_name;
|
410 |
|
|
struct symtab_and_line sal;
|
411 |
|
|
|
412 |
|
|
/* If we're in a dummy frame, don't even try to skip the prologue. */
|
413 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
414 |
|
|
&& PC_IN_CALL_DUMMY (pc, 0, 0))
|
415 |
|
|
return pc;
|
416 |
|
|
|
417 |
|
|
/* See what the symbol table says. */
|
418 |
|
|
|
419 |
|
|
if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
|
420 |
|
|
{
|
421 |
|
|
struct symbol *sym;
|
422 |
|
|
|
423 |
|
|
/* Found a function. */
|
424 |
|
|
sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
|
425 |
|
|
if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
|
426 |
|
|
{
|
427 |
|
|
/* Don't use this trick for assembly source files. */
|
428 |
|
|
sal = find_pc_line (func_addr, 0);
|
429 |
|
|
if ((sal.line != 0) && (sal.end < func_end))
|
430 |
|
|
return sal.end;
|
431 |
|
|
}
|
432 |
|
|
}
|
433 |
|
|
|
434 |
|
|
/* Check if this is Thumb code. */
|
435 |
|
|
if (arm_pc_is_thumb (pc))
|
436 |
|
|
return thumb_skip_prologue (pc, func_end);
|
437 |
|
|
|
438 |
|
|
/* Can't find the prologue end in the symbol table, try it the hard way
|
439 |
|
|
by disassembling the instructions. */
|
440 |
|
|
|
441 |
|
|
/* Like arm_scan_prologue, stop no later than pc + 64. */
|
442 |
|
|
if (func_end == 0 || func_end > pc + 64)
|
443 |
|
|
func_end = pc + 64;
|
444 |
|
|
|
445 |
|
|
for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
|
446 |
|
|
{
|
447 |
|
|
inst = read_memory_integer (skip_pc, 4);
|
448 |
|
|
|
449 |
|
|
/* "mov ip, sp" is no longer a required part of the prologue. */
|
450 |
|
|
if (inst == 0xe1a0c00d) /* mov ip, sp */
|
451 |
|
|
continue;
|
452 |
|
|
|
453 |
|
|
/* Some prologues begin with "str lr, [sp, #-4]!". */
|
454 |
|
|
if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
|
455 |
|
|
continue;
|
456 |
|
|
|
457 |
|
|
if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
|
458 |
|
|
continue;
|
459 |
|
|
|
460 |
|
|
if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
|
461 |
|
|
continue;
|
462 |
|
|
|
463 |
|
|
/* Any insns after this point may float into the code, if it makes
|
464 |
|
|
for better instruction scheduling, so we skip them only if we
|
465 |
|
|
find them, but still consider the function to be frame-ful. */
|
466 |
|
|
|
467 |
|
|
/* We may have either one sfmfd instruction here, or several stfe
|
468 |
|
|
insns, depending on the version of floating point code we
|
469 |
|
|
support. */
|
470 |
|
|
if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
|
471 |
|
|
continue;
|
472 |
|
|
|
473 |
|
|
if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
|
474 |
|
|
continue;
|
475 |
|
|
|
476 |
|
|
if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
|
477 |
|
|
continue;
|
478 |
|
|
|
479 |
|
|
if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
|
480 |
|
|
continue;
|
481 |
|
|
|
482 |
|
|
if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
|
483 |
|
|
(inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
|
484 |
|
|
(inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
|
485 |
|
|
continue;
|
486 |
|
|
|
487 |
|
|
if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
|
488 |
|
|
(inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
|
489 |
|
|
(inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
|
490 |
|
|
continue;
|
491 |
|
|
|
492 |
|
|
/* Un-recognized instruction; stop scanning. */
|
493 |
|
|
break;
|
494 |
|
|
}
|
495 |
|
|
|
496 |
|
|
return skip_pc; /* End of prologue */
|
497 |
|
|
}
|
498 |
|
|
|
499 |
|
|
/* *INDENT-OFF* */
|
500 |
|
|
/* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
|
501 |
|
|
This function decodes a Thumb function prologue to determine:
|
502 |
|
|
1) the size of the stack frame
|
503 |
|
|
2) which registers are saved on it
|
504 |
|
|
3) the offsets of saved regs
|
505 |
|
|
4) the offset from the stack pointer to the frame pointer
|
506 |
|
|
This information is stored in the "extra" fields of the frame_info.
|
507 |
|
|
|
508 |
|
|
A typical Thumb function prologue would create this stack frame
|
509 |
|
|
(offsets relative to FP)
|
510 |
|
|
old SP -> 24 stack parameters
|
511 |
|
|
20 LR
|
512 |
|
|
16 R7
|
513 |
|
|
R7 -> 0 local variables (16 bytes)
|
514 |
|
|
SP -> -12 additional stack space (12 bytes)
|
515 |
|
|
The frame size would thus be 36 bytes, and the frame offset would be
|
516 |
|
|
12 bytes. The frame register is R7.
|
517 |
|
|
|
518 |
|
|
The comments for thumb_skip_prolog() describe the algorithm we use
|
519 |
|
|
to detect the end of the prolog. */
|
520 |
|
|
/* *INDENT-ON* */
|
521 |
|
|
|
522 |
|
|
static void
|
523 |
|
|
thumb_scan_prologue (struct frame_info *fi)
|
524 |
|
|
{
|
525 |
|
|
CORE_ADDR prologue_start;
|
526 |
|
|
CORE_ADDR prologue_end;
|
527 |
|
|
CORE_ADDR current_pc;
|
528 |
|
|
/* Which register has been copied to register n? */
|
529 |
|
|
int saved_reg[16];
|
530 |
|
|
/* findmask:
|
531 |
|
|
bit 0 - push { rlist }
|
532 |
|
|
bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
|
533 |
|
|
bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
|
534 |
|
|
*/
|
535 |
|
|
int findmask = 0;
|
536 |
|
|
int i;
|
537 |
|
|
|
538 |
|
|
/* Don't try to scan dummy frames. */
|
539 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
540 |
|
|
&& fi != NULL
|
541 |
|
|
&& PC_IN_CALL_DUMMY (fi->pc, 0, 0))
|
542 |
|
|
return;
|
543 |
|
|
|
544 |
|
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
545 |
|
|
{
|
546 |
|
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
547 |
|
|
|
548 |
|
|
if (sal.line == 0) /* no line info, use current PC */
|
549 |
|
|
prologue_end = fi->pc;
|
550 |
|
|
else if (sal.end < prologue_end) /* next line begins after fn end */
|
551 |
|
|
prologue_end = sal.end; /* (probably means no prologue) */
|
552 |
|
|
}
|
553 |
|
|
else
|
554 |
|
|
/* We're in the boondocks: allow for
|
555 |
|
|
16 pushes, an add, and "mv fp,sp". */
|
556 |
|
|
prologue_end = prologue_start + 40;
|
557 |
|
|
|
558 |
|
|
prologue_end = min (prologue_end, fi->pc);
|
559 |
|
|
|
560 |
|
|
/* Initialize the saved register map. When register H is copied to
|
561 |
|
|
register L, we will put H in saved_reg[L]. */
|
562 |
|
|
for (i = 0; i < 16; i++)
|
563 |
|
|
saved_reg[i] = i;
|
564 |
|
|
|
565 |
|
|
/* Search the prologue looking for instructions that set up the
|
566 |
|
|
frame pointer, adjust the stack pointer, and save registers.
|
567 |
|
|
Do this until all basic prolog instructions are found. */
|
568 |
|
|
|
569 |
|
|
fi->extra_info->framesize = 0;
|
570 |
|
|
for (current_pc = prologue_start;
|
571 |
|
|
(current_pc < prologue_end) && ((findmask & 7) != 7);
|
572 |
|
|
current_pc += 2)
|
573 |
|
|
{
|
574 |
|
|
unsigned short insn;
|
575 |
|
|
int regno;
|
576 |
|
|
int offset;
|
577 |
|
|
|
578 |
|
|
insn = read_memory_unsigned_integer (current_pc, 2);
|
579 |
|
|
|
580 |
|
|
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
|
581 |
|
|
{
|
582 |
|
|
int mask;
|
583 |
|
|
findmask |= 1; /* push found */
|
584 |
|
|
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
|
585 |
|
|
whether to save LR (R14). */
|
586 |
|
|
mask = (insn & 0xff) | ((insn & 0x100) << 6);
|
587 |
|
|
|
588 |
|
|
/* Calculate offsets of saved R0-R7 and LR. */
|
589 |
|
|
for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
|
590 |
|
|
if (mask & (1 << regno))
|
591 |
|
|
{
|
592 |
|
|
fi->extra_info->framesize += 4;
|
593 |
|
|
fi->saved_regs[saved_reg[regno]] =
|
594 |
|
|
-(fi->extra_info->framesize);
|
595 |
|
|
/* Reset saved register map. */
|
596 |
|
|
saved_reg[regno] = regno;
|
597 |
|
|
}
|
598 |
|
|
}
|
599 |
|
|
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
|
600 |
|
|
sub sp, #simm */
|
601 |
|
|
{
|
602 |
|
|
if ((findmask & 1) == 0) /* before push? */
|
603 |
|
|
continue;
|
604 |
|
|
else
|
605 |
|
|
findmask |= 4; /* add/sub sp found */
|
606 |
|
|
|
607 |
|
|
offset = (insn & 0x7f) << 2; /* get scaled offset */
|
608 |
|
|
if (insn & 0x80) /* is it signed? (==subtracting) */
|
609 |
|
|
{
|
610 |
|
|
fi->extra_info->frameoffset += offset;
|
611 |
|
|
offset = -offset;
|
612 |
|
|
}
|
613 |
|
|
fi->extra_info->framesize -= offset;
|
614 |
|
|
}
|
615 |
|
|
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
|
616 |
|
|
{
|
617 |
|
|
findmask |= 2; /* setting of r7 found */
|
618 |
|
|
fi->extra_info->framereg = THUMB_FP_REGNUM;
|
619 |
|
|
/* get scaled offset */
|
620 |
|
|
fi->extra_info->frameoffset = (insn & 0xff) << 2;
|
621 |
|
|
}
|
622 |
|
|
else if (insn == 0x466f) /* mov r7, sp */
|
623 |
|
|
{
|
624 |
|
|
findmask |= 2; /* setting of r7 found */
|
625 |
|
|
fi->extra_info->framereg = THUMB_FP_REGNUM;
|
626 |
|
|
fi->extra_info->frameoffset = 0;
|
627 |
|
|
saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
|
628 |
|
|
}
|
629 |
|
|
else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
|
630 |
|
|
{
|
631 |
|
|
int lo_reg = insn & 7; /* dest. register (r0-r7) */
|
632 |
|
|
int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
|
633 |
|
|
saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
|
634 |
|
|
}
|
635 |
|
|
else
|
636 |
|
|
/* Something in the prolog that we don't care about or some
|
637 |
|
|
instruction from outside the prolog scheduled here for
|
638 |
|
|
optimization. */
|
639 |
|
|
continue;
|
640 |
|
|
}
|
641 |
|
|
}
|
642 |
|
|
|
643 |
|
|
/* Check if prologue for this frame's PC has already been scanned. If
|
644 |
|
|
it has, copy the relevant information about that prologue and
|
645 |
|
|
return non-zero. Otherwise do not copy anything and return zero.
|
646 |
|
|
|
647 |
|
|
The information saved in the cache includes:
|
648 |
|
|
* the frame register number;
|
649 |
|
|
* the size of the stack frame;
|
650 |
|
|
* the offsets of saved regs (relative to the old SP); and
|
651 |
|
|
* the offset from the stack pointer to the frame pointer
|
652 |
|
|
|
653 |
|
|
The cache contains only one entry, since this is adequate for the
|
654 |
|
|
typical sequence of prologue scan requests we get. When performing
|
655 |
|
|
a backtrace, GDB will usually ask to scan the same function twice
|
656 |
|
|
in a row (once to get the frame chain, and once to fill in the
|
657 |
|
|
extra frame information). */
|
658 |
|
|
|
659 |
|
|
static struct frame_info prologue_cache;
|
660 |
|
|
|
661 |
|
|
static int
|
662 |
|
|
check_prologue_cache (struct frame_info *fi)
|
663 |
|
|
{
|
664 |
|
|
int i;
|
665 |
|
|
|
666 |
|
|
if (fi->pc == prologue_cache.pc)
|
667 |
|
|
{
|
668 |
|
|
fi->extra_info->framereg = prologue_cache.extra_info->framereg;
|
669 |
|
|
fi->extra_info->framesize = prologue_cache.extra_info->framesize;
|
670 |
|
|
fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset;
|
671 |
|
|
for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
|
672 |
|
|
fi->saved_regs[i] = prologue_cache.saved_regs[i];
|
673 |
|
|
return 1;
|
674 |
|
|
}
|
675 |
|
|
else
|
676 |
|
|
return 0;
|
677 |
|
|
}
|
678 |
|
|
|
679 |
|
|
|
680 |
|
|
/* Copy the prologue information from fi to the prologue cache. */
|
681 |
|
|
|
682 |
|
|
static void
|
683 |
|
|
save_prologue_cache (struct frame_info *fi)
|
684 |
|
|
{
|
685 |
|
|
int i;
|
686 |
|
|
|
687 |
|
|
prologue_cache.pc = fi->pc;
|
688 |
|
|
prologue_cache.extra_info->framereg = fi->extra_info->framereg;
|
689 |
|
|
prologue_cache.extra_info->framesize = fi->extra_info->framesize;
|
690 |
|
|
prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset;
|
691 |
|
|
|
692 |
|
|
for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
|
693 |
|
|
prologue_cache.saved_regs[i] = fi->saved_regs[i];
|
694 |
|
|
}
|
695 |
|
|
|
696 |
|
|
|
697 |
|
|
/* This function decodes an ARM function prologue to determine:
|
698 |
|
|
1) the size of the stack frame
|
699 |
|
|
2) which registers are saved on it
|
700 |
|
|
3) the offsets of saved regs
|
701 |
|
|
4) the offset from the stack pointer to the frame pointer
|
702 |
|
|
This information is stored in the "extra" fields of the frame_info.
|
703 |
|
|
|
704 |
|
|
There are two basic forms for the ARM prologue. The fixed argument
|
705 |
|
|
function call will look like:
|
706 |
|
|
|
707 |
|
|
mov ip, sp
|
708 |
|
|
stmfd sp!, {fp, ip, lr, pc}
|
709 |
|
|
sub fp, ip, #4
|
710 |
|
|
[sub sp, sp, #4]
|
711 |
|
|
|
712 |
|
|
Which would create this stack frame (offsets relative to FP):
|
713 |
|
|
IP -> 4 (caller's stack)
|
714 |
|
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
715 |
|
|
-4 LR (return address in caller)
|
716 |
|
|
-8 IP (copy of caller's SP)
|
717 |
|
|
-12 FP (caller's FP)
|
718 |
|
|
SP -> -28 Local variables
|
719 |
|
|
|
720 |
|
|
The frame size would thus be 32 bytes, and the frame offset would be
|
721 |
|
|
28 bytes. The stmfd call can also save any of the vN registers it
|
722 |
|
|
plans to use, which increases the frame size accordingly.
|
723 |
|
|
|
724 |
|
|
Note: The stored PC is 8 off of the STMFD instruction that stored it
|
725 |
|
|
because the ARM Store instructions always store PC + 8 when you read
|
726 |
|
|
the PC register.
|
727 |
|
|
|
728 |
|
|
A variable argument function call will look like:
|
729 |
|
|
|
730 |
|
|
mov ip, sp
|
731 |
|
|
stmfd sp!, {a1, a2, a3, a4}
|
732 |
|
|
stmfd sp!, {fp, ip, lr, pc}
|
733 |
|
|
sub fp, ip, #20
|
734 |
|
|
|
735 |
|
|
Which would create this stack frame (offsets relative to FP):
|
736 |
|
|
IP -> 20 (caller's stack)
|
737 |
|
|
16 A4
|
738 |
|
|
12 A3
|
739 |
|
|
8 A2
|
740 |
|
|
4 A1
|
741 |
|
|
FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
|
742 |
|
|
-4 LR (return address in caller)
|
743 |
|
|
-8 IP (copy of caller's SP)
|
744 |
|
|
-12 FP (caller's FP)
|
745 |
|
|
SP -> -28 Local variables
|
746 |
|
|
|
747 |
|
|
The frame size would thus be 48 bytes, and the frame offset would be
|
748 |
|
|
28 bytes.
|
749 |
|
|
|
750 |
|
|
There is another potential complication, which is that the optimizer
|
751 |
|
|
will try to separate the store of fp in the "stmfd" instruction from
|
752 |
|
|
the "sub fp, ip, #NN" instruction. Almost anything can be there, so
|
753 |
|
|
we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
|
754 |
|
|
|
755 |
|
|
Also, note, the original version of the ARM toolchain claimed that there
|
756 |
|
|
should be an
|
757 |
|
|
|
758 |
|
|
instruction at the end of the prologue. I have never seen GCC produce
|
759 |
|
|
this, and the ARM docs don't mention it. We still test for it below in
|
760 |
|
|
case it happens...
|
761 |
|
|
|
762 |
|
|
*/
|
763 |
|
|
|
764 |
|
|
static void
|
765 |
|
|
arm_scan_prologue (struct frame_info *fi)
|
766 |
|
|
{
|
767 |
|
|
int regno, sp_offset, fp_offset;
|
768 |
|
|
LONGEST return_value;
|
769 |
|
|
CORE_ADDR prologue_start, prologue_end, current_pc;
|
770 |
|
|
|
771 |
|
|
/* Check if this function is already in the cache of frame information. */
|
772 |
|
|
if (check_prologue_cache (fi))
|
773 |
|
|
return;
|
774 |
|
|
|
775 |
|
|
/* Assume there is no frame until proven otherwise. */
|
776 |
|
|
fi->extra_info->framereg = ARM_SP_REGNUM;
|
777 |
|
|
fi->extra_info->framesize = 0;
|
778 |
|
|
fi->extra_info->frameoffset = 0;
|
779 |
|
|
|
780 |
|
|
/* Check for Thumb prologue. */
|
781 |
|
|
if (arm_pc_is_thumb (fi->pc))
|
782 |
|
|
{
|
783 |
|
|
thumb_scan_prologue (fi);
|
784 |
|
|
save_prologue_cache (fi);
|
785 |
|
|
return;
|
786 |
|
|
}
|
787 |
|
|
|
788 |
|
|
/* Find the function prologue. If we can't find the function in
|
789 |
|
|
the symbol table, peek in the stack frame to find the PC. */
|
790 |
|
|
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
|
791 |
|
|
{
|
792 |
|
|
/* One way to find the end of the prologue (which works well
|
793 |
|
|
for unoptimized code) is to do the following:
|
794 |
|
|
|
795 |
|
|
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
796 |
|
|
|
797 |
|
|
if (sal.line == 0)
|
798 |
|
|
prologue_end = fi->pc;
|
799 |
|
|
else if (sal.end < prologue_end)
|
800 |
|
|
prologue_end = sal.end;
|
801 |
|
|
|
802 |
|
|
This mechanism is very accurate so long as the optimizer
|
803 |
|
|
doesn't move any instructions from the function body into the
|
804 |
|
|
prologue. If this happens, sal.end will be the last
|
805 |
|
|
instruction in the first hunk of prologue code just before
|
806 |
|
|
the first instruction that the scheduler has moved from
|
807 |
|
|
the body to the prologue.
|
808 |
|
|
|
809 |
|
|
In order to make sure that we scan all of the prologue
|
810 |
|
|
instructions, we use a slightly less accurate mechanism which
|
811 |
|
|
may scan more than necessary. To help compensate for this
|
812 |
|
|
lack of accuracy, the prologue scanning loop below contains
|
813 |
|
|
several clauses which'll cause the loop to terminate early if
|
814 |
|
|
an implausible prologue instruction is encountered.
|
815 |
|
|
|
816 |
|
|
The expression
|
817 |
|
|
|
818 |
|
|
prologue_start + 64
|
819 |
|
|
|
820 |
|
|
is a suitable endpoint since it accounts for the largest
|
821 |
|
|
possible prologue plus up to five instructions inserted by
|
822 |
|
|
the scheduler. */
|
823 |
|
|
|
824 |
|
|
if (prologue_end > prologue_start + 64)
|
825 |
|
|
{
|
826 |
|
|
prologue_end = prologue_start + 64; /* See above. */
|
827 |
|
|
}
|
828 |
|
|
}
|
829 |
|
|
else
|
830 |
|
|
{
|
831 |
|
|
/* Get address of the stmfd in the prologue of the callee;
|
832 |
|
|
the saved PC is the address of the stmfd + 8. */
|
833 |
|
|
if (!safe_read_memory_integer (fi->frame, 4, &return_value))
|
834 |
|
|
return;
|
835 |
|
|
else
|
836 |
|
|
{
|
837 |
|
|
prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
|
838 |
|
|
prologue_end = prologue_start + 64; /* See above. */
|
839 |
|
|
}
|
840 |
|
|
}
|
841 |
|
|
|
842 |
|
|
/* Now search the prologue looking for instructions that set up the
|
843 |
|
|
frame pointer, adjust the stack pointer, and save registers.
|
844 |
|
|
|
845 |
|
|
Be careful, however, and if it doesn't look like a prologue,
|
846 |
|
|
don't try to scan it. If, for instance, a frameless function
|
847 |
|
|
begins with stmfd sp!, then we will tell ourselves there is
|
848 |
|
|
a frame, which will confuse stack traceback, as well as "finish"
|
849 |
|
|
and other operations that rely on a knowledge of the stack
|
850 |
|
|
traceback.
|
851 |
|
|
|
852 |
|
|
In the APCS, the prologue should start with "mov ip, sp" so
|
853 |
|
|
if we don't see this as the first insn, we will stop.
|
854 |
|
|
|
855 |
|
|
[Note: This doesn't seem to be true any longer, so it's now an
|
856 |
|
|
optional part of the prologue. - Kevin Buettner, 2001-11-20]
|
857 |
|
|
|
858 |
|
|
[Note further: The "mov ip,sp" only seems to be missing in
|
859 |
|
|
frameless functions at optimization level "-O2" or above,
|
860 |
|
|
in which case it is often (but not always) replaced by
|
861 |
|
|
"str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
|
862 |
|
|
|
863 |
|
|
sp_offset = fp_offset = 0;
|
864 |
|
|
|
865 |
|
|
for (current_pc = prologue_start;
|
866 |
|
|
current_pc < prologue_end;
|
867 |
|
|
current_pc += 4)
|
868 |
|
|
{
|
869 |
|
|
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
|
870 |
|
|
|
871 |
|
|
if (insn == 0xe1a0c00d) /* mov ip, sp */
|
872 |
|
|
{
|
873 |
|
|
continue;
|
874 |
|
|
}
|
875 |
|
|
else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
|
876 |
|
|
{
|
877 |
|
|
/* Function is frameless: extra_info defaults OK? */
|
878 |
|
|
continue;
|
879 |
|
|
}
|
880 |
|
|
else if ((insn & 0xffff0000) == 0xe92d0000)
|
881 |
|
|
/* stmfd sp!, {..., fp, ip, lr, pc}
|
882 |
|
|
or
|
883 |
|
|
stmfd sp!, {a1, a2, a3, a4} */
|
884 |
|
|
{
|
885 |
|
|
int mask = insn & 0xffff;
|
886 |
|
|
|
887 |
|
|
/* Calculate offsets of saved registers. */
|
888 |
|
|
for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
|
889 |
|
|
if (mask & (1 << regno))
|
890 |
|
|
{
|
891 |
|
|
sp_offset -= 4;
|
892 |
|
|
fi->saved_regs[regno] = sp_offset;
|
893 |
|
|
}
|
894 |
|
|
}
|
895 |
|
|
else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
|
896 |
|
|
(insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
|
897 |
|
|
(insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
|
898 |
|
|
{
|
899 |
|
|
/* No need to add this to saved_regs -- it's just an arg reg. */
|
900 |
|
|
continue;
|
901 |
|
|
}
|
902 |
|
|
else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
|
903 |
|
|
(insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
|
904 |
|
|
(insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
|
905 |
|
|
{
|
906 |
|
|
/* No need to add this to saved_regs -- it's just an arg reg. */
|
907 |
|
|
continue;
|
908 |
|
|
}
|
909 |
|
|
else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
|
910 |
|
|
{
|
911 |
|
|
unsigned imm = insn & 0xff; /* immediate value */
|
912 |
|
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
913 |
|
|
imm = (imm >> rot) | (imm << (32 - rot));
|
914 |
|
|
fp_offset = -imm;
|
915 |
|
|
fi->extra_info->framereg = ARM_FP_REGNUM;
|
916 |
|
|
}
|
917 |
|
|
else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
|
918 |
|
|
{
|
919 |
|
|
unsigned imm = insn & 0xff; /* immediate value */
|
920 |
|
|
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
|
921 |
|
|
imm = (imm >> rot) | (imm << (32 - rot));
|
922 |
|
|
sp_offset -= imm;
|
923 |
|
|
}
|
924 |
|
|
else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
|
925 |
|
|
{
|
926 |
|
|
sp_offset -= 12;
|
927 |
|
|
regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
|
928 |
|
|
fi->saved_regs[regno] = sp_offset;
|
929 |
|
|
}
|
930 |
|
|
else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
|
931 |
|
|
{
|
932 |
|
|
int n_saved_fp_regs;
|
933 |
|
|
unsigned int fp_start_reg, fp_bound_reg;
|
934 |
|
|
|
935 |
|
|
if ((insn & 0x800) == 0x800) /* N0 is set */
|
936 |
|
|
{
|
937 |
|
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
938 |
|
|
n_saved_fp_regs = 3;
|
939 |
|
|
else
|
940 |
|
|
n_saved_fp_regs = 1;
|
941 |
|
|
}
|
942 |
|
|
else
|
943 |
|
|
{
|
944 |
|
|
if ((insn & 0x40000) == 0x40000) /* N1 is set */
|
945 |
|
|
n_saved_fp_regs = 2;
|
946 |
|
|
else
|
947 |
|
|
n_saved_fp_regs = 4;
|
948 |
|
|
}
|
949 |
|
|
|
950 |
|
|
fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
|
951 |
|
|
fp_bound_reg = fp_start_reg + n_saved_fp_regs;
|
952 |
|
|
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
|
953 |
|
|
{
|
954 |
|
|
sp_offset -= 12;
|
955 |
|
|
fi->saved_regs[fp_start_reg++] = sp_offset;
|
956 |
|
|
}
|
957 |
|
|
}
|
958 |
|
|
else if ((insn & 0xf0000000) != 0xe0000000)
|
959 |
|
|
break; /* Condition not true, exit early */
|
960 |
|
|
else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
|
961 |
|
|
break; /* Don't scan past a block load */
|
962 |
|
|
else
|
963 |
|
|
/* The optimizer might shove anything into the prologue,
|
964 |
|
|
so we just skip what we don't recognize. */
|
965 |
|
|
continue;
|
966 |
|
|
}
|
967 |
|
|
|
968 |
|
|
/* The frame size is just the negative of the offset (from the
|
969 |
|
|
original SP) of the last thing thing we pushed on the stack.
|
970 |
|
|
The frame offset is [new FP] - [new SP]. */
|
971 |
|
|
fi->extra_info->framesize = -sp_offset;
|
972 |
|
|
if (fi->extra_info->framereg == ARM_FP_REGNUM)
|
973 |
|
|
fi->extra_info->frameoffset = fp_offset - sp_offset;
|
974 |
|
|
else
|
975 |
|
|
fi->extra_info->frameoffset = 0;
|
976 |
|
|
|
977 |
|
|
save_prologue_cache (fi);
|
978 |
|
|
}
|
979 |
|
|
|
980 |
|
|
/* Find REGNUM on the stack. Otherwise, it's in an active register.
|
981 |
|
|
One thing we might want to do here is to check REGNUM against the
|
982 |
|
|
clobber mask, and somehow flag it as invalid if it isn't saved on
|
983 |
|
|
the stack somewhere. This would provide a graceful failure mode
|
984 |
|
|
when trying to get the value of caller-saves registers for an inner
|
985 |
|
|
frame. */
|
986 |
|
|
|
987 |
|
|
static CORE_ADDR
|
988 |
|
|
arm_find_callers_reg (struct frame_info *fi, int regnum)
|
989 |
|
|
{
|
990 |
|
|
/* NOTE: cagney/2002-05-03: This function really shouldn't be
|
991 |
|
|
needed. Instead the (still being written) register unwind
|
992 |
|
|
function could be called directly. */
|
993 |
|
|
for (; fi; fi = fi->next)
|
994 |
|
|
{
|
995 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
996 |
|
|
&& PC_IN_CALL_DUMMY (fi->pc, 0, 0))
|
997 |
|
|
{
|
998 |
|
|
return generic_read_register_dummy (fi->pc, fi->frame, regnum);
|
999 |
|
|
}
|
1000 |
|
|
else if (fi->saved_regs[regnum] != 0)
|
1001 |
|
|
{
|
1002 |
|
|
/* NOTE: cagney/2002-05-03: This would normally need to
|
1003 |
|
|
handle ARM_SP_REGNUM as a special case as, according to
|
1004 |
|
|
the frame.h comments, saved_regs[SP_REGNUM] contains the
|
1005 |
|
|
SP value not its address. It appears that the ARM isn't
|
1006 |
|
|
doing this though. */
|
1007 |
|
|
return read_memory_integer (fi->saved_regs[regnum],
|
1008 |
|
|
REGISTER_RAW_SIZE (regnum));
|
1009 |
|
|
}
|
1010 |
|
|
}
|
1011 |
|
|
return read_register (regnum);
|
1012 |
|
|
}
|
1013 |
|
|
/* Function: frame_chain Given a GDB frame, determine the address of
|
1014 |
|
|
the calling function's frame. This will be used to create a new
|
1015 |
|
|
GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
|
1016 |
|
|
will be called for the new frame. For ARM, we save the frame size
|
1017 |
|
|
when we initialize the frame_info. */
|
1018 |
|
|
|
1019 |
|
|
static CORE_ADDR
|
1020 |
|
|
arm_frame_chain (struct frame_info *fi)
|
1021 |
|
|
{
|
1022 |
|
|
CORE_ADDR caller_pc;
|
1023 |
|
|
int framereg = fi->extra_info->framereg;
|
1024 |
|
|
|
1025 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
1026 |
|
|
&& PC_IN_CALL_DUMMY (fi->pc, 0, 0))
|
1027 |
|
|
/* A generic call dummy's frame is the same as caller's. */
|
1028 |
|
|
return fi->frame;
|
1029 |
|
|
|
1030 |
|
|
if (fi->pc < LOWEST_PC)
|
1031 |
|
|
return 0;
|
1032 |
|
|
|
1033 |
|
|
/* If the caller is the startup code, we're at the end of the chain. */
|
1034 |
|
|
caller_pc = FRAME_SAVED_PC (fi);
|
1035 |
|
|
|
1036 |
|
|
/* If the caller is Thumb and the caller is ARM, or vice versa,
|
1037 |
|
|
the frame register of the caller is different from ours.
|
1038 |
|
|
So we must scan the prologue of the caller to determine its
|
1039 |
|
|
frame register number. */
|
1040 |
|
|
/* XXX Fixme, we should try to do this without creating a temporary
|
1041 |
|
|
caller_fi. */
|
1042 |
|
|
if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
|
1043 |
|
|
{
|
1044 |
|
|
struct frame_info caller_fi;
|
1045 |
|
|
struct cleanup *old_chain;
|
1046 |
|
|
|
1047 |
|
|
/* Create a temporary frame suitable for scanning the caller's
|
1048 |
|
|
prologue. (Ugh.) */
|
1049 |
|
|
memset (&caller_fi, 0, sizeof (caller_fi));
|
1050 |
|
|
caller_fi.extra_info = (struct frame_extra_info *)
|
1051 |
|
|
xcalloc (1, sizeof (struct frame_extra_info));
|
1052 |
|
|
old_chain = make_cleanup (xfree, caller_fi.extra_info);
|
1053 |
|
|
caller_fi.saved_regs = (CORE_ADDR *)
|
1054 |
|
|
xcalloc (1, SIZEOF_FRAME_SAVED_REGS);
|
1055 |
|
|
make_cleanup (xfree, caller_fi.saved_regs);
|
1056 |
|
|
|
1057 |
|
|
/* Now, scan the prologue and obtain the frame register. */
|
1058 |
|
|
caller_fi.pc = caller_pc;
|
1059 |
|
|
arm_scan_prologue (&caller_fi);
|
1060 |
|
|
framereg = caller_fi.extra_info->framereg;
|
1061 |
|
|
|
1062 |
|
|
/* Deallocate the storage associated with the temporary frame
|
1063 |
|
|
created above. */
|
1064 |
|
|
do_cleanups (old_chain);
|
1065 |
|
|
}
|
1066 |
|
|
|
1067 |
|
|
/* If the caller used a frame register, return its value.
|
1068 |
|
|
Otherwise, return the caller's stack pointer. */
|
1069 |
|
|
if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
|
1070 |
|
|
return arm_find_callers_reg (fi, framereg);
|
1071 |
|
|
else
|
1072 |
|
|
return fi->frame + fi->extra_info->framesize;
|
1073 |
|
|
}
|
1074 |
|
|
|
1075 |
|
|
/* This function actually figures out the frame address for a given pc
|
1076 |
|
|
and sp. This is tricky because we sometimes don't use an explicit
|
1077 |
|
|
frame pointer, and the previous stack pointer isn't necessarily
|
1078 |
|
|
recorded on the stack. The only reliable way to get this info is
|
1079 |
|
|
to examine the prologue. FROMLEAF is a little confusing, it means
|
1080 |
|
|
this is the next frame up the chain AFTER a frameless function. If
|
1081 |
|
|
this is true, then the frame value for this frame is still in the
|
1082 |
|
|
fp register. */
|
1083 |
|
|
|
1084 |
|
|
static void
|
1085 |
|
|
arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
|
1086 |
|
|
{
|
1087 |
|
|
int reg;
|
1088 |
|
|
CORE_ADDR sp;
|
1089 |
|
|
|
1090 |
|
|
if (fi->saved_regs == NULL)
|
1091 |
|
|
frame_saved_regs_zalloc (fi);
|
1092 |
|
|
|
1093 |
|
|
fi->extra_info = (struct frame_extra_info *)
|
1094 |
|
|
frame_obstack_alloc (sizeof (struct frame_extra_info));
|
1095 |
|
|
|
1096 |
|
|
fi->extra_info->framesize = 0;
|
1097 |
|
|
fi->extra_info->frameoffset = 0;
|
1098 |
|
|
fi->extra_info->framereg = 0;
|
1099 |
|
|
|
1100 |
|
|
if (fi->next)
|
1101 |
|
|
fi->pc = FRAME_SAVED_PC (fi->next);
|
1102 |
|
|
|
1103 |
|
|
memset (fi->saved_regs, '\000', sizeof fi->saved_regs);
|
1104 |
|
|
|
1105 |
|
|
/* Compute stack pointer for this frame. We use this value for both
|
1106 |
|
|
the sigtramp and call dummy cases. */
|
1107 |
|
|
if (!fi->next)
|
1108 |
|
|
sp = read_sp();
|
1109 |
|
|
else if (USE_GENERIC_DUMMY_FRAMES
|
1110 |
|
|
&& PC_IN_CALL_DUMMY (fi->next->pc, 0, 0))
|
1111 |
|
|
/* For generic dummy frames, pull the value direct from the frame.
|
1112 |
|
|
Having an unwind function to do this would be nice. */
|
1113 |
|
|
sp = generic_read_register_dummy (fi->next->pc, fi->next->frame,
|
1114 |
|
|
ARM_SP_REGNUM);
|
1115 |
|
|
else
|
1116 |
|
|
sp = (fi->next->frame - fi->next->extra_info->frameoffset
|
1117 |
|
|
+ fi->next->extra_info->framesize);
|
1118 |
|
|
|
1119 |
|
|
/* Determine whether or not we're in a sigtramp frame.
|
1120 |
|
|
Unfortunately, it isn't sufficient to test
|
1121 |
|
|
fi->signal_handler_caller because this value is sometimes set
|
1122 |
|
|
after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
|
1123 |
|
|
fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
|
1124 |
|
|
need to use the sigcontext addresses for the saved registers.
|
1125 |
|
|
|
1126 |
|
|
Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
|
1127 |
|
|
against the name of the function, the code below will have to be
|
1128 |
|
|
changed to first fetch the name of the function and then pass
|
1129 |
|
|
this name to PC_IN_SIGTRAMP. */
|
1130 |
|
|
|
1131 |
|
|
if (SIGCONTEXT_REGISTER_ADDRESS_P ()
|
1132 |
|
|
&& (fi->signal_handler_caller || PC_IN_SIGTRAMP (fi->pc, (char *)0)))
|
1133 |
|
|
{
|
1134 |
|
|
for (reg = 0; reg < NUM_REGS; reg++)
|
1135 |
|
|
fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg);
|
1136 |
|
|
|
1137 |
|
|
/* FIXME: What about thumb mode? */
|
1138 |
|
|
fi->extra_info->framereg = ARM_SP_REGNUM;
|
1139 |
|
|
fi->frame =
|
1140 |
|
|
read_memory_integer (fi->saved_regs[fi->extra_info->framereg],
|
1141 |
|
|
REGISTER_RAW_SIZE (fi->extra_info->framereg));
|
1142 |
|
|
fi->extra_info->framesize = 0;
|
1143 |
|
|
fi->extra_info->frameoffset = 0;
|
1144 |
|
|
|
1145 |
|
|
}
|
1146 |
|
|
else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame))
|
1147 |
|
|
{
|
1148 |
|
|
CORE_ADDR rp;
|
1149 |
|
|
CORE_ADDR callers_sp;
|
1150 |
|
|
|
1151 |
|
|
/* Set rp point at the high end of the saved registers. */
|
1152 |
|
|
rp = fi->frame - REGISTER_SIZE;
|
1153 |
|
|
|
1154 |
|
|
/* Fill in addresses of saved registers. */
|
1155 |
|
|
fi->saved_regs[ARM_PS_REGNUM] = rp;
|
1156 |
|
|
rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM);
|
1157 |
|
|
for (reg = ARM_PC_REGNUM; reg >= 0; reg--)
|
1158 |
|
|
{
|
1159 |
|
|
fi->saved_regs[reg] = rp;
|
1160 |
|
|
rp -= REGISTER_RAW_SIZE (reg);
|
1161 |
|
|
}
|
1162 |
|
|
|
1163 |
|
|
callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM],
|
1164 |
|
|
REGISTER_RAW_SIZE (ARM_SP_REGNUM));
|
1165 |
|
|
fi->extra_info->framereg = ARM_FP_REGNUM;
|
1166 |
|
|
fi->extra_info->framesize = callers_sp - sp;
|
1167 |
|
|
fi->extra_info->frameoffset = fi->frame - sp;
|
1168 |
|
|
}
|
1169 |
|
|
else
|
1170 |
|
|
{
|
1171 |
|
|
arm_scan_prologue (fi);
|
1172 |
|
|
|
1173 |
|
|
if (!fi->next)
|
1174 |
|
|
/* This is the innermost frame? */
|
1175 |
|
|
fi->frame = read_register (fi->extra_info->framereg);
|
1176 |
|
|
else if (USE_GENERIC_DUMMY_FRAMES
|
1177 |
|
|
&& PC_IN_CALL_DUMMY (fi->next->pc, 0, 0))
|
1178 |
|
|
/* Next inner most frame is a dummy, just grab its frame.
|
1179 |
|
|
Dummy frames always have the same FP as their caller. */
|
1180 |
|
|
fi->frame = fi->next->frame;
|
1181 |
|
|
else if (fi->extra_info->framereg == ARM_FP_REGNUM
|
1182 |
|
|
|| fi->extra_info->framereg == THUMB_FP_REGNUM)
|
1183 |
|
|
{
|
1184 |
|
|
/* not the innermost frame */
|
1185 |
|
|
/* If we have an FP, the callee saved it. */
|
1186 |
|
|
if (fi->next->saved_regs[fi->extra_info->framereg] != 0)
|
1187 |
|
|
fi->frame =
|
1188 |
|
|
read_memory_integer (fi->next
|
1189 |
|
|
->saved_regs[fi->extra_info->framereg], 4);
|
1190 |
|
|
else if (fromleaf)
|
1191 |
|
|
/* If we were called by a frameless fn. then our frame is
|
1192 |
|
|
still in the frame pointer register on the board... */
|
1193 |
|
|
fi->frame = read_fp ();
|
1194 |
|
|
}
|
1195 |
|
|
|
1196 |
|
|
/* Calculate actual addresses of saved registers using offsets
|
1197 |
|
|
determined by arm_scan_prologue. */
|
1198 |
|
|
for (reg = 0; reg < NUM_REGS; reg++)
|
1199 |
|
|
if (fi->saved_regs[reg] != 0)
|
1200 |
|
|
fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize
|
1201 |
|
|
- fi->extra_info->frameoffset);
|
1202 |
|
|
}
|
1203 |
|
|
}
|
1204 |
|
|
|
1205 |
|
|
|
1206 |
|
|
/* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
|
1207 |
|
|
is saved in the stack anywhere, otherwise we get it from the
|
1208 |
|
|
registers.
|
1209 |
|
|
|
1210 |
|
|
The old definition of this function was a macro:
|
1211 |
|
|
#define FRAME_SAVED_PC(FRAME) \
|
1212 |
|
|
ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
|
1213 |
|
|
|
1214 |
|
|
static CORE_ADDR
|
1215 |
|
|
arm_frame_saved_pc (struct frame_info *fi)
|
1216 |
|
|
{
|
1217 |
|
|
/* If a dummy frame, pull the PC out of the frame's register buffer. */
|
1218 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
1219 |
|
|
&& PC_IN_CALL_DUMMY (fi->pc, 0, 0))
|
1220 |
|
|
return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM);
|
1221 |
|
|
|
1222 |
|
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset,
|
1223 |
|
|
fi->frame))
|
1224 |
|
|
{
|
1225 |
|
|
return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM],
|
1226 |
|
|
REGISTER_RAW_SIZE (ARM_PC_REGNUM));
|
1227 |
|
|
}
|
1228 |
|
|
else
|
1229 |
|
|
{
|
1230 |
|
|
CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
|
1231 |
|
|
return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
|
1232 |
|
|
}
|
1233 |
|
|
}
|
1234 |
|
|
|
1235 |
|
|
/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
|
1236 |
|
|
Examine the Program Status Register to decide which state we're in. */
|
1237 |
|
|
|
1238 |
|
|
static CORE_ADDR
|
1239 |
|
|
arm_read_fp (void)
|
1240 |
|
|
{
|
1241 |
|
|
if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
|
1242 |
|
|
return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
|
1243 |
|
|
else
|
1244 |
|
|
return read_register (ARM_FP_REGNUM); /* R11 if ARM */
|
1245 |
|
|
}
|
1246 |
|
|
|
1247 |
|
|
/* Store into a struct frame_saved_regs the addresses of the saved
|
1248 |
|
|
registers of frame described by FRAME_INFO. This includes special
|
1249 |
|
|
registers such as PC and FP saved in special ways in the stack
|
1250 |
|
|
frame. SP is even more special: the address we return for it IS
|
1251 |
|
|
the sp for the next frame. */
|
1252 |
|
|
|
1253 |
|
|
static void
|
1254 |
|
|
arm_frame_init_saved_regs (struct frame_info *fip)
|
1255 |
|
|
{
|
1256 |
|
|
|
1257 |
|
|
if (fip->saved_regs)
|
1258 |
|
|
return;
|
1259 |
|
|
|
1260 |
|
|
arm_init_extra_frame_info (0, fip);
|
1261 |
|
|
}
|
1262 |
|
|
|
1263 |
|
|
/* Set the return address for a generic dummy frame. ARM uses the
|
1264 |
|
|
entry point. */
|
1265 |
|
|
|
1266 |
|
|
static CORE_ADDR
|
1267 |
|
|
arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
|
1268 |
|
|
{
|
1269 |
|
|
write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ());
|
1270 |
|
|
return sp;
|
1271 |
|
|
}
|
1272 |
|
|
|
1273 |
|
|
/* Push an empty stack frame, to record the current PC, etc. */
|
1274 |
|
|
|
1275 |
|
|
static void
|
1276 |
|
|
arm_push_dummy_frame (void)
|
1277 |
|
|
{
|
1278 |
|
|
CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
|
1279 |
|
|
CORE_ADDR sp = old_sp;
|
1280 |
|
|
CORE_ADDR fp, prologue_start;
|
1281 |
|
|
int regnum;
|
1282 |
|
|
|
1283 |
|
|
/* Push the two dummy prologue instructions in reverse order,
|
1284 |
|
|
so that they'll be in the correct low-to-high order in memory. */
|
1285 |
|
|
/* sub fp, ip, #4 */
|
1286 |
|
|
sp = push_word (sp, 0xe24cb004);
|
1287 |
|
|
/* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
|
1288 |
|
|
prologue_start = sp = push_word (sp, 0xe92ddfff);
|
1289 |
|
|
|
1290 |
|
|
/* Push a pointer to the dummy prologue + 12, because when stm
|
1291 |
|
|
instruction stores the PC, it stores the address of the stm
|
1292 |
|
|
instruction itself plus 12. */
|
1293 |
|
|
fp = sp = push_word (sp, prologue_start + 12);
|
1294 |
|
|
|
1295 |
|
|
/* Push the processor status. */
|
1296 |
|
|
sp = push_word (sp, read_register (ARM_PS_REGNUM));
|
1297 |
|
|
|
1298 |
|
|
/* Push all 16 registers starting with r15. */
|
1299 |
|
|
for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
|
1300 |
|
|
sp = push_word (sp, read_register (regnum));
|
1301 |
|
|
|
1302 |
|
|
/* Update fp (for both Thumb and ARM) and sp. */
|
1303 |
|
|
write_register (ARM_FP_REGNUM, fp);
|
1304 |
|
|
write_register (THUMB_FP_REGNUM, fp);
|
1305 |
|
|
write_register (ARM_SP_REGNUM, sp);
|
1306 |
|
|
}
|
1307 |
|
|
|
1308 |
|
|
/* CALL_DUMMY_WORDS:
|
1309 |
|
|
This sequence of words is the instructions
|
1310 |
|
|
|
1311 |
|
|
mov lr,pc
|
1312 |
|
|
mov pc,r4
|
1313 |
|
|
illegal
|
1314 |
|
|
|
1315 |
|
|
Note this is 12 bytes. */
|
1316 |
|
|
|
1317 |
|
|
static LONGEST arm_call_dummy_words[] =
|
1318 |
|
|
{
|
1319 |
|
|
0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
|
1320 |
|
|
};
|
1321 |
|
|
|
1322 |
|
|
/* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
|
1323 |
|
|
breakpoint to the proper address in the call dummy, so that
|
1324 |
|
|
`finish' after a stop in a call dummy works.
|
1325 |
|
|
|
1326 |
|
|
FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
|
1327 |
|
|
optimal solution, but the call to arm_fix_call_dummy is immediately
|
1328 |
|
|
followed by a call to run_stack_dummy, which is the only function
|
1329 |
|
|
where call_dummy_breakpoint_offset is actually used. */
|
1330 |
|
|
|
1331 |
|
|
|
1332 |
|
|
static void
|
1333 |
|
|
arm_set_call_dummy_breakpoint_offset (void)
|
1334 |
|
|
{
|
1335 |
|
|
if (caller_is_thumb)
|
1336 |
|
|
set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4);
|
1337 |
|
|
else
|
1338 |
|
|
set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8);
|
1339 |
|
|
}
|
1340 |
|
|
|
1341 |
|
|
/* Fix up the call dummy, based on whether the processor is currently
|
1342 |
|
|
in Thumb or ARM mode, and whether the target function is Thumb or
|
1343 |
|
|
ARM. There are three different situations requiring three
|
1344 |
|
|
different dummies:
|
1345 |
|
|
|
1346 |
|
|
* ARM calling ARM: uses the call dummy in tm-arm.h, which has already
|
1347 |
|
|
been copied into the dummy parameter to this function.
|
1348 |
|
|
* ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
|
1349 |
|
|
"mov pc,r4" instruction patched to be a "bx r4" instead.
|
1350 |
|
|
* Thumb calling anything: uses the Thumb dummy defined below, which
|
1351 |
|
|
works for calling both ARM and Thumb functions.
|
1352 |
|
|
|
1353 |
|
|
All three call dummies expect to receive the target function
|
1354 |
|
|
address in R4, with the low bit set if it's a Thumb function. */
|
1355 |
|
|
|
1356 |
|
|
static void
|
1357 |
|
|
arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
|
1358 |
|
|
struct value **args, struct type *type, int gcc_p)
|
1359 |
|
|
{
|
1360 |
|
|
static short thumb_dummy[4] =
|
1361 |
|
|
{
|
1362 |
|
|
0xf000, 0xf801, /* bl label */
|
1363 |
|
|
0xdf18, /* swi 24 */
|
1364 |
|
|
0x4720, /* label: bx r4 */
|
1365 |
|
|
};
|
1366 |
|
|
static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
|
1367 |
|
|
|
1368 |
|
|
/* Set flag indicating whether the current PC is in a Thumb function. */
|
1369 |
|
|
caller_is_thumb = arm_pc_is_thumb (read_pc ());
|
1370 |
|
|
arm_set_call_dummy_breakpoint_offset ();
|
1371 |
|
|
|
1372 |
|
|
/* If the target function is Thumb, set the low bit of the function
|
1373 |
|
|
address. And if the CPU is currently in ARM mode, patch the
|
1374 |
|
|
second instruction of call dummy to use a BX instruction to
|
1375 |
|
|
switch to Thumb mode. */
|
1376 |
|
|
target_is_thumb = arm_pc_is_thumb (fun);
|
1377 |
|
|
if (target_is_thumb)
|
1378 |
|
|
{
|
1379 |
|
|
fun |= 1;
|
1380 |
|
|
if (!caller_is_thumb)
|
1381 |
|
|
store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
|
1382 |
|
|
}
|
1383 |
|
|
|
1384 |
|
|
/* If the CPU is currently in Thumb mode, use the Thumb call dummy
|
1385 |
|
|
instead of the ARM one that's already been copied. This will
|
1386 |
|
|
work for both Thumb and ARM target functions. */
|
1387 |
|
|
if (caller_is_thumb)
|
1388 |
|
|
{
|
1389 |
|
|
int i;
|
1390 |
|
|
char *p = dummy;
|
1391 |
|
|
int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
|
1392 |
|
|
|
1393 |
|
|
for (i = 0; i < len; i++)
|
1394 |
|
|
{
|
1395 |
|
|
store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
|
1396 |
|
|
p += sizeof (thumb_dummy[0]);
|
1397 |
|
|
}
|
1398 |
|
|
}
|
1399 |
|
|
|
1400 |
|
|
/* Put the target address in r4; the call dummy will copy this to
|
1401 |
|
|
the PC. */
|
1402 |
|
|
write_register (4, fun);
|
1403 |
|
|
}
|
1404 |
|
|
|
1405 |
|
|
/* Note: ScottB
|
1406 |
|
|
|
1407 |
|
|
This function does not support passing parameters using the FPA
|
1408 |
|
|
variant of the APCS. It passes any floating point arguments in the
|
1409 |
|
|
general registers and/or on the stack. */
|
1410 |
|
|
|
1411 |
|
|
static CORE_ADDR
|
1412 |
|
|
arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
|
1413 |
|
|
int struct_return, CORE_ADDR struct_addr)
|
1414 |
|
|
{
|
1415 |
|
|
CORE_ADDR fp;
|
1416 |
|
|
int argnum;
|
1417 |
|
|
int argreg;
|
1418 |
|
|
int nstack;
|
1419 |
|
|
int simd_argreg;
|
1420 |
|
|
int second_pass;
|
1421 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
1422 |
|
|
|
1423 |
|
|
/* Walk through the list of args and determine how large a temporary
|
1424 |
|
|
stack is required. Need to take care here as structs may be
|
1425 |
|
|
passed on the stack, and we have to to push them. On the second
|
1426 |
|
|
pass, do the store. */
|
1427 |
|
|
nstack = 0;
|
1428 |
|
|
fp = sp;
|
1429 |
|
|
for (second_pass = 0; second_pass < 2; second_pass++)
|
1430 |
|
|
{
|
1431 |
|
|
/* Compute the FP using the information computed during the
|
1432 |
|
|
first pass. */
|
1433 |
|
|
if (second_pass)
|
1434 |
|
|
fp = sp - nstack;
|
1435 |
|
|
|
1436 |
|
|
simd_argreg = 0;
|
1437 |
|
|
argreg = ARM_A1_REGNUM;
|
1438 |
|
|
nstack = 0;
|
1439 |
|
|
|
1440 |
|
|
/* The struct_return pointer occupies the first parameter
|
1441 |
|
|
passing register. */
|
1442 |
|
|
if (struct_return)
|
1443 |
|
|
{
|
1444 |
|
|
if (second_pass)
|
1445 |
|
|
{
|
1446 |
|
|
if (arm_debug)
|
1447 |
|
|
fprintf_unfiltered (gdb_stdlog,
|
1448 |
|
|
"struct return in %s = 0x%s\n",
|
1449 |
|
|
REGISTER_NAME (argreg),
|
1450 |
|
|
paddr (struct_addr));
|
1451 |
|
|
write_register (argreg, struct_addr);
|
1452 |
|
|
}
|
1453 |
|
|
argreg++;
|
1454 |
|
|
}
|
1455 |
|
|
|
1456 |
|
|
for (argnum = 0; argnum < nargs; argnum++)
|
1457 |
|
|
{
|
1458 |
|
|
int len;
|
1459 |
|
|
struct type *arg_type;
|
1460 |
|
|
struct type *target_type;
|
1461 |
|
|
enum type_code typecode;
|
1462 |
|
|
char *val;
|
1463 |
|
|
|
1464 |
|
|
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
|
1465 |
|
|
len = TYPE_LENGTH (arg_type);
|
1466 |
|
|
target_type = TYPE_TARGET_TYPE (arg_type);
|
1467 |
|
|
typecode = TYPE_CODE (arg_type);
|
1468 |
|
|
val = VALUE_CONTENTS (args[argnum]);
|
1469 |
|
|
|
1470 |
|
|
/* If the argument is a pointer to a function, and it is a
|
1471 |
|
|
Thumb function, create a LOCAL copy of the value and set
|
1472 |
|
|
the THUMB bit in it. */
|
1473 |
|
|
if (second_pass
|
1474 |
|
|
&& TYPE_CODE_PTR == typecode
|
1475 |
|
|
&& target_type != NULL
|
1476 |
|
|
&& TYPE_CODE_FUNC == TYPE_CODE (target_type))
|
1477 |
|
|
{
|
1478 |
|
|
CORE_ADDR regval = extract_address (val, len);
|
1479 |
|
|
if (arm_pc_is_thumb (regval))
|
1480 |
|
|
{
|
1481 |
|
|
val = alloca (len);
|
1482 |
|
|
store_address (val, len, MAKE_THUMB_ADDR (regval));
|
1483 |
|
|
}
|
1484 |
|
|
}
|
1485 |
|
|
|
1486 |
|
|
/* Copy the argument to general registers or the stack in
|
1487 |
|
|
register-sized pieces. Large arguments are split between
|
1488 |
|
|
registers and stack. */
|
1489 |
|
|
while (len > 0)
|
1490 |
|
|
{
|
1491 |
|
|
int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
|
1492 |
|
|
|
1493 |
|
|
if (argreg <= ARM_LAST_ARG_REGNUM)
|
1494 |
|
|
{
|
1495 |
|
|
/* The argument is being passed in a general purpose
|
1496 |
|
|
register. */
|
1497 |
|
|
if (second_pass)
|
1498 |
|
|
{
|
1499 |
|
|
CORE_ADDR regval = extract_address (val,
|
1500 |
|
|
partial_len);
|
1501 |
|
|
if (arm_debug)
|
1502 |
|
|
fprintf_unfiltered (gdb_stdlog,
|
1503 |
|
|
"arg %d in %s = 0x%s\n",
|
1504 |
|
|
argnum,
|
1505 |
|
|
REGISTER_NAME (argreg),
|
1506 |
|
|
phex (regval, REGISTER_SIZE));
|
1507 |
|
|
write_register (argreg, regval);
|
1508 |
|
|
}
|
1509 |
|
|
argreg++;
|
1510 |
|
|
}
|
1511 |
|
|
else
|
1512 |
|
|
{
|
1513 |
|
|
if (second_pass)
|
1514 |
|
|
{
|
1515 |
|
|
/* Push the arguments onto the stack. */
|
1516 |
|
|
if (arm_debug)
|
1517 |
|
|
fprintf_unfiltered (gdb_stdlog,
|
1518 |
|
|
"arg %d @ 0x%s + %d\n",
|
1519 |
|
|
argnum, paddr (fp), nstack);
|
1520 |
|
|
write_memory (fp + nstack, val, REGISTER_SIZE);
|
1521 |
|
|
}
|
1522 |
|
|
nstack += REGISTER_SIZE;
|
1523 |
|
|
}
|
1524 |
|
|
|
1525 |
|
|
len -= partial_len;
|
1526 |
|
|
val += partial_len;
|
1527 |
|
|
}
|
1528 |
|
|
|
1529 |
|
|
}
|
1530 |
|
|
}
|
1531 |
|
|
|
1532 |
|
|
/* Return the botom of the argument list (pointed to by fp). */
|
1533 |
|
|
return fp;
|
1534 |
|
|
}
|
1535 |
|
|
|
1536 |
|
|
/* Pop the current frame. So long as the frame info has been
|
1537 |
|
|
initialized properly (see arm_init_extra_frame_info), this code
|
1538 |
|
|
works for dummy frames as well as regular frames. I.e, there's no
|
1539 |
|
|
need to have a special case for dummy frames. */
|
1540 |
|
|
static void
|
1541 |
|
|
arm_pop_frame (void)
|
1542 |
|
|
{
|
1543 |
|
|
int regnum;
|
1544 |
|
|
struct frame_info *frame = get_current_frame ();
|
1545 |
|
|
CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset
|
1546 |
|
|
+ frame->extra_info->framesize);
|
1547 |
|
|
|
1548 |
|
|
if (USE_GENERIC_DUMMY_FRAMES
|
1549 |
|
|
&& PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
|
1550 |
|
|
{
|
1551 |
|
|
generic_pop_dummy_frame ();
|
1552 |
|
|
flush_cached_frames ();
|
1553 |
|
|
return;
|
1554 |
|
|
}
|
1555 |
|
|
|
1556 |
|
|
for (regnum = 0; regnum < NUM_REGS; regnum++)
|
1557 |
|
|
if (frame->saved_regs[regnum] != 0)
|
1558 |
|
|
write_register (regnum,
|
1559 |
|
|
read_memory_integer (frame->saved_regs[regnum],
|
1560 |
|
|
REGISTER_RAW_SIZE (regnum)));
|
1561 |
|
|
|
1562 |
|
|
write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame));
|
1563 |
|
|
write_register (ARM_SP_REGNUM, old_SP);
|
1564 |
|
|
|
1565 |
|
|
flush_cached_frames ();
|
1566 |
|
|
}
|
1567 |
|
|
|
1568 |
|
|
static void
|
1569 |
|
|
print_fpu_flags (int flags)
|
1570 |
|
|
{
|
1571 |
|
|
if (flags & (1 << 0))
|
1572 |
|
|
fputs ("IVO ", stdout);
|
1573 |
|
|
if (flags & (1 << 1))
|
1574 |
|
|
fputs ("DVZ ", stdout);
|
1575 |
|
|
if (flags & (1 << 2))
|
1576 |
|
|
fputs ("OFL ", stdout);
|
1577 |
|
|
if (flags & (1 << 3))
|
1578 |
|
|
fputs ("UFL ", stdout);
|
1579 |
|
|
if (flags & (1 << 4))
|
1580 |
|
|
fputs ("INX ", stdout);
|
1581 |
|
|
putchar ('\n');
|
1582 |
|
|
}
|
1583 |
|
|
|
1584 |
|
|
/* Print interesting information about the floating point processor
|
1585 |
|
|
(if present) or emulator. */
|
1586 |
|
|
static void
|
1587 |
|
|
arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
|
1588 |
|
|
struct frame_info *frame, const char *args)
|
1589 |
|
|
{
|
1590 |
|
|
register unsigned long status = read_register (ARM_FPS_REGNUM);
|
1591 |
|
|
int type;
|
1592 |
|
|
|
1593 |
|
|
type = (status >> 24) & 127;
|
1594 |
|
|
printf ("%s FPU type %d\n",
|
1595 |
|
|
(status & (1 << 31)) ? "Hardware" : "Software",
|
1596 |
|
|
type);
|
1597 |
|
|
fputs ("mask: ", stdout);
|
1598 |
|
|
print_fpu_flags (status >> 16);
|
1599 |
|
|
fputs ("flags: ", stdout);
|
1600 |
|
|
print_fpu_flags (status);
|
1601 |
|
|
}
|
1602 |
|
|
|
1603 |
|
|
/* Return the GDB type object for the "standard" data type of data in
|
1604 |
|
|
register N. */
|
1605 |
|
|
|
1606 |
|
|
static struct type *
|
1607 |
|
|
arm_register_type (int regnum)
|
1608 |
|
|
{
|
1609 |
|
|
if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
|
1610 |
|
|
{
|
1611 |
|
|
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
1612 |
|
|
return builtin_type_arm_ext_big;
|
1613 |
|
|
else
|
1614 |
|
|
return builtin_type_arm_ext_littlebyte_bigword;
|
1615 |
|
|
}
|
1616 |
|
|
else
|
1617 |
|
|
return builtin_type_int32;
|
1618 |
|
|
}
|
1619 |
|
|
|
1620 |
|
|
/* Index within `registers' of the first byte of the space for
|
1621 |
|
|
register N. */
|
1622 |
|
|
|
1623 |
|
|
static int
|
1624 |
|
|
arm_register_byte (int regnum)
|
1625 |
|
|
{
|
1626 |
|
|
if (regnum < ARM_F0_REGNUM)
|
1627 |
|
|
return regnum * INT_REGISTER_RAW_SIZE;
|
1628 |
|
|
else if (regnum < ARM_PS_REGNUM)
|
1629 |
|
|
return (NUM_GREGS * INT_REGISTER_RAW_SIZE
|
1630 |
|
|
+ (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE);
|
1631 |
|
|
else
|
1632 |
|
|
return (NUM_GREGS * INT_REGISTER_RAW_SIZE
|
1633 |
|
|
+ NUM_FREGS * FP_REGISTER_RAW_SIZE
|
1634 |
|
|
+ (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
|
1635 |
|
|
}
|
1636 |
|
|
|
1637 |
|
|
/* Number of bytes of storage in the actual machine representation for
|
1638 |
|
|
register N. All registers are 4 bytes, except fp0 - fp7, which are
|
1639 |
|
|
12 bytes in length. */
|
1640 |
|
|
|
1641 |
|
|
static int
|
1642 |
|
|
arm_register_raw_size (int regnum)
|
1643 |
|
|
{
|
1644 |
|
|
if (regnum < ARM_F0_REGNUM)
|
1645 |
|
|
return INT_REGISTER_RAW_SIZE;
|
1646 |
|
|
else if (regnum < ARM_FPS_REGNUM)
|
1647 |
|
|
return FP_REGISTER_RAW_SIZE;
|
1648 |
|
|
else
|
1649 |
|
|
return STATUS_REGISTER_SIZE;
|
1650 |
|
|
}
|
1651 |
|
|
|
1652 |
|
|
/* Number of bytes of storage in a program's representation
|
1653 |
|
|
for register N. */
|
1654 |
|
|
static int
|
1655 |
|
|
arm_register_virtual_size (int regnum)
|
1656 |
|
|
{
|
1657 |
|
|
if (regnum < ARM_F0_REGNUM)
|
1658 |
|
|
return INT_REGISTER_VIRTUAL_SIZE;
|
1659 |
|
|
else if (regnum < ARM_FPS_REGNUM)
|
1660 |
|
|
return FP_REGISTER_VIRTUAL_SIZE;
|
1661 |
|
|
else
|
1662 |
|
|
return STATUS_REGISTER_SIZE;
|
1663 |
|
|
}
|
1664 |
|
|
|
1665 |
|
|
/* Map GDB internal REGNUM onto the Arm simulator register numbers. */
|
1666 |
|
|
static int
|
1667 |
|
|
arm_register_sim_regno (int regnum)
|
1668 |
|
|
{
|
1669 |
|
|
int reg = regnum;
|
1670 |
|
|
gdb_assert (reg >= 0 && reg < NUM_REGS);
|
1671 |
|
|
|
1672 |
|
|
if (reg < NUM_GREGS)
|
1673 |
|
|
return SIM_ARM_R0_REGNUM + reg;
|
1674 |
|
|
reg -= NUM_GREGS;
|
1675 |
|
|
|
1676 |
|
|
if (reg < NUM_FREGS)
|
1677 |
|
|
return SIM_ARM_FP0_REGNUM + reg;
|
1678 |
|
|
reg -= NUM_FREGS;
|
1679 |
|
|
|
1680 |
|
|
if (reg < NUM_SREGS)
|
1681 |
|
|
return SIM_ARM_FPS_REGNUM + reg;
|
1682 |
|
|
reg -= NUM_SREGS;
|
1683 |
|
|
|
1684 |
|
|
internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
|
1685 |
|
|
}
|
1686 |
|
|
|
1687 |
|
|
/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
|
1688 |
|
|
convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
|
1689 |
|
|
It is thought that this is is the floating-point register format on
|
1690 |
|
|
little-endian systems. */
|
1691 |
|
|
|
1692 |
|
|
static void
|
1693 |
|
|
convert_from_extended (void *ptr, void *dbl)
|
1694 |
|
|
{
|
1695 |
|
|
DOUBLEST d;
|
1696 |
|
|
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
1697 |
|
|
floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
|
1698 |
|
|
else
|
1699 |
|
|
floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
|
1700 |
|
|
ptr, &d);
|
1701 |
|
|
floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl);
|
1702 |
|
|
}
|
1703 |
|
|
|
1704 |
|
|
static void
|
1705 |
|
|
convert_to_extended (void *dbl, void *ptr)
|
1706 |
|
|
{
|
1707 |
|
|
DOUBLEST d;
|
1708 |
|
|
floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d);
|
1709 |
|
|
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
1710 |
|
|
floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
|
1711 |
|
|
else
|
1712 |
|
|
floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
|
1713 |
|
|
&d, dbl);
|
1714 |
|
|
}
|
1715 |
|
|
|
1716 |
|
|
static int
|
1717 |
|
|
condition_true (unsigned long cond, unsigned long status_reg)
|
1718 |
|
|
{
|
1719 |
|
|
if (cond == INST_AL || cond == INST_NV)
|
1720 |
|
|
return 1;
|
1721 |
|
|
|
1722 |
|
|
switch (cond)
|
1723 |
|
|
{
|
1724 |
|
|
case INST_EQ:
|
1725 |
|
|
return ((status_reg & FLAG_Z) != 0);
|
1726 |
|
|
case INST_NE:
|
1727 |
|
|
return ((status_reg & FLAG_Z) == 0);
|
1728 |
|
|
case INST_CS:
|
1729 |
|
|
return ((status_reg & FLAG_C) != 0);
|
1730 |
|
|
case INST_CC:
|
1731 |
|
|
return ((status_reg & FLAG_C) == 0);
|
1732 |
|
|
case INST_MI:
|
1733 |
|
|
return ((status_reg & FLAG_N) != 0);
|
1734 |
|
|
case INST_PL:
|
1735 |
|
|
return ((status_reg & FLAG_N) == 0);
|
1736 |
|
|
case INST_VS:
|
1737 |
|
|
return ((status_reg & FLAG_V) != 0);
|
1738 |
|
|
case INST_VC:
|
1739 |
|
|
return ((status_reg & FLAG_V) == 0);
|
1740 |
|
|
case INST_HI:
|
1741 |
|
|
return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
|
1742 |
|
|
case INST_LS:
|
1743 |
|
|
return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
|
1744 |
|
|
case INST_GE:
|
1745 |
|
|
return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
|
1746 |
|
|
case INST_LT:
|
1747 |
|
|
return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
|
1748 |
|
|
case INST_GT:
|
1749 |
|
|
return (((status_reg & FLAG_Z) == 0) &&
|
1750 |
|
|
(((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
|
1751 |
|
|
case INST_LE:
|
1752 |
|
|
return (((status_reg & FLAG_Z) != 0) ||
|
1753 |
|
|
(((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
|
1754 |
|
|
}
|
1755 |
|
|
return 1;
|
1756 |
|
|
}
|
1757 |
|
|
|
1758 |
|
|
/* Support routines for single stepping. Calculate the next PC value. */
|
1759 |
|
|
#define submask(x) ((1L << ((x) + 1)) - 1)
|
1760 |
|
|
#define bit(obj,st) (((obj) >> (st)) & 1)
|
1761 |
|
|
#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
|
1762 |
|
|
#define sbits(obj,st,fn) \
|
1763 |
|
|
((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
|
1764 |
|
|
#define BranchDest(addr,instr) \
|
1765 |
|
|
((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
|
1766 |
|
|
#define ARM_PC_32 1
|
1767 |
|
|
|
1768 |
|
|
static unsigned long
|
1769 |
|
|
shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
|
1770 |
|
|
unsigned long status_reg)
|
1771 |
|
|
{
|
1772 |
|
|
unsigned long res, shift;
|
1773 |
|
|
int rm = bits (inst, 0, 3);
|
1774 |
|
|
unsigned long shifttype = bits (inst, 5, 6);
|
1775 |
|
|
|
1776 |
|
|
if (bit (inst, 4))
|
1777 |
|
|
{
|
1778 |
|
|
int rs = bits (inst, 8, 11);
|
1779 |
|
|
shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
|
1780 |
|
|
}
|
1781 |
|
|
else
|
1782 |
|
|
shift = bits (inst, 7, 11);
|
1783 |
|
|
|
1784 |
|
|
res = (rm == 15
|
1785 |
|
|
? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
|
1786 |
|
|
+ (bit (inst, 4) ? 12 : 8))
|
1787 |
|
|
: read_register (rm));
|
1788 |
|
|
|
1789 |
|
|
switch (shifttype)
|
1790 |
|
|
{
|
1791 |
|
|
case 0: /* LSL */
|
1792 |
|
|
res = shift >= 32 ? 0 : res << shift;
|
1793 |
|
|
break;
|
1794 |
|
|
|
1795 |
|
|
case 1: /* LSR */
|
1796 |
|
|
res = shift >= 32 ? 0 : res >> shift;
|
1797 |
|
|
break;
|
1798 |
|
|
|
1799 |
|
|
case 2: /* ASR */
|
1800 |
|
|
if (shift >= 32)
|
1801 |
|
|
shift = 31;
|
1802 |
|
|
res = ((res & 0x80000000L)
|
1803 |
|
|
? ~((~res) >> shift) : res >> shift);
|
1804 |
|
|
break;
|
1805 |
|
|
|
1806 |
|
|
case 3: /* ROR/RRX */
|
1807 |
|
|
shift &= 31;
|
1808 |
|
|
if (shift == 0)
|
1809 |
|
|
res = (res >> 1) | (carry ? 0x80000000L : 0);
|
1810 |
|
|
else
|
1811 |
|
|
res = (res >> shift) | (res << (32 - shift));
|
1812 |
|
|
break;
|
1813 |
|
|
}
|
1814 |
|
|
|
1815 |
|
|
return res & 0xffffffff;
|
1816 |
|
|
}
|
1817 |
|
|
|
1818 |
|
|
/* Return number of 1-bits in VAL. */
|
1819 |
|
|
|
1820 |
|
|
static int
|
1821 |
|
|
bitcount (unsigned long val)
|
1822 |
|
|
{
|
1823 |
|
|
int nbits;
|
1824 |
|
|
for (nbits = 0; val != 0; nbits++)
|
1825 |
|
|
val &= val - 1; /* delete rightmost 1-bit in val */
|
1826 |
|
|
return nbits;
|
1827 |
|
|
}
|
1828 |
|
|
|
1829 |
|
|
CORE_ADDR
|
1830 |
|
|
thumb_get_next_pc (CORE_ADDR pc)
|
1831 |
|
|
{
|
1832 |
|
|
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
|
1833 |
|
|
unsigned short inst1 = read_memory_integer (pc, 2);
|
1834 |
|
|
CORE_ADDR nextpc = pc + 2; /* default is next instruction */
|
1835 |
|
|
unsigned long offset;
|
1836 |
|
|
|
1837 |
|
|
if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
|
1838 |
|
|
{
|
1839 |
|
|
CORE_ADDR sp;
|
1840 |
|
|
|
1841 |
|
|
/* Fetch the saved PC from the stack. It's stored above
|
1842 |
|
|
all of the other registers. */
|
1843 |
|
|
offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
|
1844 |
|
|
sp = read_register (ARM_SP_REGNUM);
|
1845 |
|
|
nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
|
1846 |
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
1847 |
|
|
if (nextpc == pc)
|
1848 |
|
|
error ("Infinite loop detected");
|
1849 |
|
|
}
|
1850 |
|
|
else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
|
1851 |
|
|
{
|
1852 |
|
|
unsigned long status = read_register (ARM_PS_REGNUM);
|
1853 |
|
|
unsigned long cond = bits (inst1, 8, 11);
|
1854 |
|
|
if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
|
1855 |
|
|
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
|
1856 |
|
|
}
|
1857 |
|
|
else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
|
1858 |
|
|
{
|
1859 |
|
|
nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
|
1860 |
|
|
}
|
1861 |
|
|
else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
|
1862 |
|
|
{
|
1863 |
|
|
unsigned short inst2 = read_memory_integer (pc + 2, 2);
|
1864 |
|
|
offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
|
1865 |
|
|
nextpc = pc_val + offset;
|
1866 |
|
|
}
|
1867 |
|
|
|
1868 |
|
|
return nextpc;
|
1869 |
|
|
}
|
1870 |
|
|
|
1871 |
|
|
CORE_ADDR
|
1872 |
|
|
arm_get_next_pc (CORE_ADDR pc)
|
1873 |
|
|
{
|
1874 |
|
|
unsigned long pc_val;
|
1875 |
|
|
unsigned long this_instr;
|
1876 |
|
|
unsigned long status;
|
1877 |
|
|
CORE_ADDR nextpc;
|
1878 |
|
|
|
1879 |
|
|
if (arm_pc_is_thumb (pc))
|
1880 |
|
|
return thumb_get_next_pc (pc);
|
1881 |
|
|
|
1882 |
|
|
pc_val = (unsigned long) pc;
|
1883 |
|
|
this_instr = read_memory_integer (pc, 4);
|
1884 |
|
|
status = read_register (ARM_PS_REGNUM);
|
1885 |
|
|
nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
|
1886 |
|
|
|
1887 |
|
|
if (condition_true (bits (this_instr, 28, 31), status))
|
1888 |
|
|
{
|
1889 |
|
|
switch (bits (this_instr, 24, 27))
|
1890 |
|
|
{
|
1891 |
|
|
case 0x0:
|
1892 |
|
|
case 0x1: /* data processing */
|
1893 |
|
|
case 0x2:
|
1894 |
|
|
case 0x3:
|
1895 |
|
|
{
|
1896 |
|
|
unsigned long operand1, operand2, result = 0;
|
1897 |
|
|
unsigned long rn;
|
1898 |
|
|
int c;
|
1899 |
|
|
|
1900 |
|
|
if (bits (this_instr, 12, 15) != 15)
|
1901 |
|
|
break;
|
1902 |
|
|
|
1903 |
|
|
if (bits (this_instr, 22, 25) == 0
|
1904 |
|
|
&& bits (this_instr, 4, 7) == 9) /* multiply */
|
1905 |
|
|
error ("Illegal update to pc in instruction");
|
1906 |
|
|
|
1907 |
|
|
/* Multiply into PC */
|
1908 |
|
|
c = (status & FLAG_C) ? 1 : 0;
|
1909 |
|
|
rn = bits (this_instr, 16, 19);
|
1910 |
|
|
operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
|
1911 |
|
|
|
1912 |
|
|
if (bit (this_instr, 25))
|
1913 |
|
|
{
|
1914 |
|
|
unsigned long immval = bits (this_instr, 0, 7);
|
1915 |
|
|
unsigned long rotate = 2 * bits (this_instr, 8, 11);
|
1916 |
|
|
operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
|
1917 |
|
|
& 0xffffffff;
|
1918 |
|
|
}
|
1919 |
|
|
else /* operand 2 is a shifted register */
|
1920 |
|
|
operand2 = shifted_reg_val (this_instr, c, pc_val, status);
|
1921 |
|
|
|
1922 |
|
|
switch (bits (this_instr, 21, 24))
|
1923 |
|
|
{
|
1924 |
|
|
case 0x0: /*and */
|
1925 |
|
|
result = operand1 & operand2;
|
1926 |
|
|
break;
|
1927 |
|
|
|
1928 |
|
|
case 0x1: /*eor */
|
1929 |
|
|
result = operand1 ^ operand2;
|
1930 |
|
|
break;
|
1931 |
|
|
|
1932 |
|
|
case 0x2: /*sub */
|
1933 |
|
|
result = operand1 - operand2;
|
1934 |
|
|
break;
|
1935 |
|
|
|
1936 |
|
|
case 0x3: /*rsb */
|
1937 |
|
|
result = operand2 - operand1;
|
1938 |
|
|
break;
|
1939 |
|
|
|
1940 |
|
|
case 0x4: /*add */
|
1941 |
|
|
result = operand1 + operand2;
|
1942 |
|
|
break;
|
1943 |
|
|
|
1944 |
|
|
case 0x5: /*adc */
|
1945 |
|
|
result = operand1 + operand2 + c;
|
1946 |
|
|
break;
|
1947 |
|
|
|
1948 |
|
|
case 0x6: /*sbc */
|
1949 |
|
|
result = operand1 - operand2 + c;
|
1950 |
|
|
break;
|
1951 |
|
|
|
1952 |
|
|
case 0x7: /*rsc */
|
1953 |
|
|
result = operand2 - operand1 + c;
|
1954 |
|
|
break;
|
1955 |
|
|
|
1956 |
|
|
case 0x8:
|
1957 |
|
|
case 0x9:
|
1958 |
|
|
case 0xa:
|
1959 |
|
|
case 0xb: /* tst, teq, cmp, cmn */
|
1960 |
|
|
result = (unsigned long) nextpc;
|
1961 |
|
|
break;
|
1962 |
|
|
|
1963 |
|
|
case 0xc: /*orr */
|
1964 |
|
|
result = operand1 | operand2;
|
1965 |
|
|
break;
|
1966 |
|
|
|
1967 |
|
|
case 0xd: /*mov */
|
1968 |
|
|
/* Always step into a function. */
|
1969 |
|
|
result = operand2;
|
1970 |
|
|
break;
|
1971 |
|
|
|
1972 |
|
|
case 0xe: /*bic */
|
1973 |
|
|
result = operand1 & ~operand2;
|
1974 |
|
|
break;
|
1975 |
|
|
|
1976 |
|
|
case 0xf: /*mvn */
|
1977 |
|
|
result = ~operand2;
|
1978 |
|
|
break;
|
1979 |
|
|
}
|
1980 |
|
|
nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
|
1981 |
|
|
|
1982 |
|
|
if (nextpc == pc)
|
1983 |
|
|
error ("Infinite loop detected");
|
1984 |
|
|
break;
|
1985 |
|
|
}
|
1986 |
|
|
|
1987 |
|
|
case 0x4:
|
1988 |
|
|
case 0x5: /* data transfer */
|
1989 |
|
|
case 0x6:
|
1990 |
|
|
case 0x7:
|
1991 |
|
|
if (bit (this_instr, 20))
|
1992 |
|
|
{
|
1993 |
|
|
/* load */
|
1994 |
|
|
if (bits (this_instr, 12, 15) == 15)
|
1995 |
|
|
{
|
1996 |
|
|
/* rd == pc */
|
1997 |
|
|
unsigned long rn;
|
1998 |
|
|
unsigned long base;
|
1999 |
|
|
|
2000 |
|
|
if (bit (this_instr, 22))
|
2001 |
|
|
error ("Illegal update to pc in instruction");
|
2002 |
|
|
|
2003 |
|
|
/* byte write to PC */
|
2004 |
|
|
rn = bits (this_instr, 16, 19);
|
2005 |
|
|
base = (rn == 15) ? pc_val + 8 : read_register (rn);
|
2006 |
|
|
if (bit (this_instr, 24))
|
2007 |
|
|
{
|
2008 |
|
|
/* pre-indexed */
|
2009 |
|
|
int c = (status & FLAG_C) ? 1 : 0;
|
2010 |
|
|
unsigned long offset =
|
2011 |
|
|
(bit (this_instr, 25)
|
2012 |
|
|
? shifted_reg_val (this_instr, c, pc_val, status)
|
2013 |
|
|
: bits (this_instr, 0, 11));
|
2014 |
|
|
|
2015 |
|
|
if (bit (this_instr, 23))
|
2016 |
|
|
base += offset;
|
2017 |
|
|
else
|
2018 |
|
|
base -= offset;
|
2019 |
|
|
}
|
2020 |
|
|
nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
|
2021 |
|
|
4);
|
2022 |
|
|
|
2023 |
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
2024 |
|
|
|
2025 |
|
|
if (nextpc == pc)
|
2026 |
|
|
error ("Infinite loop detected");
|
2027 |
|
|
}
|
2028 |
|
|
}
|
2029 |
|
|
break;
|
2030 |
|
|
|
2031 |
|
|
case 0x8:
|
2032 |
|
|
case 0x9: /* block transfer */
|
2033 |
|
|
if (bit (this_instr, 20))
|
2034 |
|
|
{
|
2035 |
|
|
/* LDM */
|
2036 |
|
|
if (bit (this_instr, 15))
|
2037 |
|
|
{
|
2038 |
|
|
/* loading pc */
|
2039 |
|
|
int offset = 0;
|
2040 |
|
|
|
2041 |
|
|
if (bit (this_instr, 23))
|
2042 |
|
|
{
|
2043 |
|
|
/* up */
|
2044 |
|
|
unsigned long reglist = bits (this_instr, 0, 14);
|
2045 |
|
|
offset = bitcount (reglist) * 4;
|
2046 |
|
|
if (bit (this_instr, 24)) /* pre */
|
2047 |
|
|
offset += 4;
|
2048 |
|
|
}
|
2049 |
|
|
else if (bit (this_instr, 24))
|
2050 |
|
|
offset = -4;
|
2051 |
|
|
|
2052 |
|
|
{
|
2053 |
|
|
unsigned long rn_val =
|
2054 |
|
|
read_register (bits (this_instr, 16, 19));
|
2055 |
|
|
nextpc =
|
2056 |
|
|
(CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
|
2057 |
|
|
+ offset),
|
2058 |
|
|
4);
|
2059 |
|
|
}
|
2060 |
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
2061 |
|
|
if (nextpc == pc)
|
2062 |
|
|
error ("Infinite loop detected");
|
2063 |
|
|
}
|
2064 |
|
|
}
|
2065 |
|
|
break;
|
2066 |
|
|
|
2067 |
|
|
case 0xb: /* branch & link */
|
2068 |
|
|
case 0xa: /* branch */
|
2069 |
|
|
{
|
2070 |
|
|
nextpc = BranchDest (pc, this_instr);
|
2071 |
|
|
|
2072 |
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
2073 |
|
|
if (nextpc == pc)
|
2074 |
|
|
error ("Infinite loop detected");
|
2075 |
|
|
break;
|
2076 |
|
|
}
|
2077 |
|
|
|
2078 |
|
|
case 0xc:
|
2079 |
|
|
case 0xd:
|
2080 |
|
|
case 0xe: /* coproc ops */
|
2081 |
|
|
case 0xf: /* SWI */
|
2082 |
|
|
break;
|
2083 |
|
|
|
2084 |
|
|
default:
|
2085 |
|
|
fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
|
2086 |
|
|
return (pc);
|
2087 |
|
|
}
|
2088 |
|
|
}
|
2089 |
|
|
|
2090 |
|
|
return nextpc;
|
2091 |
|
|
}
|
2092 |
|
|
|
2093 |
|
|
/* single_step() is called just before we want to resume the inferior,
|
2094 |
|
|
if we want to single-step it but there is no hardware or kernel
|
2095 |
|
|
single-step support. We find the target of the coming instruction
|
2096 |
|
|
and breakpoint it.
|
2097 |
|
|
|
2098 |
|
|
single_step() is also called just after the inferior stops. If we
|
2099 |
|
|
had set up a simulated single-step, we undo our damage. */
|
2100 |
|
|
|
2101 |
|
|
static void
|
2102 |
|
|
arm_software_single_step (enum target_signal sig, int insert_bpt)
|
2103 |
|
|
{
|
2104 |
|
|
static int next_pc; /* State between setting and unsetting. */
|
2105 |
|
|
static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
|
2106 |
|
|
|
2107 |
|
|
if (insert_bpt)
|
2108 |
|
|
{
|
2109 |
|
|
next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
|
2110 |
|
|
target_insert_breakpoint (next_pc, break_mem);
|
2111 |
|
|
}
|
2112 |
|
|
else
|
2113 |
|
|
target_remove_breakpoint (next_pc, break_mem);
|
2114 |
|
|
}
|
2115 |
|
|
|
2116 |
|
|
#include "bfd-in2.h"
|
2117 |
|
|
#include "libcoff.h"
|
2118 |
|
|
|
2119 |
|
|
static int
|
2120 |
|
|
gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
|
2121 |
|
|
{
|
2122 |
|
|
if (arm_pc_is_thumb (memaddr))
|
2123 |
|
|
{
|
2124 |
|
|
static asymbol *asym;
|
2125 |
|
|
static combined_entry_type ce;
|
2126 |
|
|
static struct coff_symbol_struct csym;
|
2127 |
|
|
static struct _bfd fake_bfd;
|
2128 |
|
|
static bfd_target fake_target;
|
2129 |
|
|
|
2130 |
|
|
if (csym.native == NULL)
|
2131 |
|
|
{
|
2132 |
|
|
/* Create a fake symbol vector containing a Thumb symbol.
|
2133 |
|
|
This is solely so that the code in print_insn_little_arm()
|
2134 |
|
|
and print_insn_big_arm() in opcodes/arm-dis.c will detect
|
2135 |
|
|
the presence of a Thumb symbol and switch to decoding
|
2136 |
|
|
Thumb instructions. */
|
2137 |
|
|
|
2138 |
|
|
fake_target.flavour = bfd_target_coff_flavour;
|
2139 |
|
|
fake_bfd.xvec = &fake_target;
|
2140 |
|
|
ce.u.syment.n_sclass = C_THUMBEXTFUNC;
|
2141 |
|
|
csym.native = &ce;
|
2142 |
|
|
csym.symbol.the_bfd = &fake_bfd;
|
2143 |
|
|
csym.symbol.name = "fake";
|
2144 |
|
|
asym = (asymbol *) & csym;
|
2145 |
|
|
}
|
2146 |
|
|
|
2147 |
|
|
memaddr = UNMAKE_THUMB_ADDR (memaddr);
|
2148 |
|
|
info->symbols = &asym;
|
2149 |
|
|
}
|
2150 |
|
|
else
|
2151 |
|
|
info->symbols = NULL;
|
2152 |
|
|
|
2153 |
|
|
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
2154 |
|
|
return print_insn_big_arm (memaddr, info);
|
2155 |
|
|
else
|
2156 |
|
|
return print_insn_little_arm (memaddr, info);
|
2157 |
|
|
}
|
2158 |
|
|
|
2159 |
|
|
/* The following define instruction sequences that will cause ARM
|
2160 |
|
|
cpu's to take an undefined instruction trap. These are used to
|
2161 |
|
|
signal a breakpoint to GDB.
|
2162 |
|
|
|
2163 |
|
|
The newer ARMv4T cpu's are capable of operating in ARM or Thumb
|
2164 |
|
|
modes. A different instruction is required for each mode. The ARM
|
2165 |
|
|
cpu's can also be big or little endian. Thus four different
|
2166 |
|
|
instructions are needed to support all cases.
|
2167 |
|
|
|
2168 |
|
|
Note: ARMv4 defines several new instructions that will take the
|
2169 |
|
|
undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
|
2170 |
|
|
not in fact add the new instructions. The new undefined
|
2171 |
|
|
instructions in ARMv4 are all instructions that had no defined
|
2172 |
|
|
behaviour in earlier chips. There is no guarantee that they will
|
2173 |
|
|
raise an exception, but may be treated as NOP's. In practice, it
|
2174 |
|
|
may only safe to rely on instructions matching:
|
2175 |
|
|
|
2176 |
|
|
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
|
2177 |
|
|
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
|
2178 |
|
|
C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
|
2179 |
|
|
|
2180 |
|
|
Even this may only true if the condition predicate is true. The
|
2181 |
|
|
following use a condition predicate of ALWAYS so it is always TRUE.
|
2182 |
|
|
|
2183 |
|
|
There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
|
2184 |
|
|
and NetBSD all use a software interrupt rather than an undefined
|
2185 |
|
|
instruction to force a trap. This can be handled by by the
|
2186 |
|
|
abi-specific code during establishment of the gdbarch vector. */
|
2187 |
|
|
|
2188 |
|
|
|
2189 |
|
|
/* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
|
2190 |
|
|
override these definitions. */
|
2191 |
|
|
#ifndef ARM_LE_BREAKPOINT
|
2192 |
|
|
#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
|
2193 |
|
|
#endif
|
2194 |
|
|
#ifndef ARM_BE_BREAKPOINT
|
2195 |
|
|
#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
|
2196 |
|
|
#endif
|
2197 |
|
|
#ifndef THUMB_LE_BREAKPOINT
|
2198 |
|
|
#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
|
2199 |
|
|
#endif
|
2200 |
|
|
#ifndef THUMB_BE_BREAKPOINT
|
2201 |
|
|
#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
|
2202 |
|
|
#endif
|
2203 |
|
|
|
2204 |
|
|
static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
|
2205 |
|
|
static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
|
2206 |
|
|
static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
|
2207 |
|
|
static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
|
2208 |
|
|
|
2209 |
|
|
/* Determine the type and size of breakpoint to insert at PCPTR. Uses
|
2210 |
|
|
the program counter value to determine whether a 16-bit or 32-bit
|
2211 |
|
|
breakpoint should be used. It returns a pointer to a string of
|
2212 |
|
|
bytes that encode a breakpoint instruction, stores the length of
|
2213 |
|
|
the string to *lenptr, and adjusts the program counter (if
|
2214 |
|
|
necessary) to point to the actual memory location where the
|
2215 |
|
|
breakpoint should be inserted. */
|
2216 |
|
|
|
2217 |
|
|
/* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
|
2218 |
|
|
breakpoints and storing their handles instread of what was in
|
2219 |
|
|
memory. It is nice that this is the same size as a handle -
|
2220 |
|
|
otherwise remote-rdp will have to change. */
|
2221 |
|
|
|
2222 |
|
|
static const unsigned char *
|
2223 |
|
|
arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
|
2224 |
|
|
{
|
2225 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
2226 |
|
|
|
2227 |
|
|
if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
|
2228 |
|
|
{
|
2229 |
|
|
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
|
2230 |
|
|
*lenptr = tdep->thumb_breakpoint_size;
|
2231 |
|
|
return tdep->thumb_breakpoint;
|
2232 |
|
|
}
|
2233 |
|
|
else
|
2234 |
|
|
{
|
2235 |
|
|
*lenptr = tdep->arm_breakpoint_size;
|
2236 |
|
|
return tdep->arm_breakpoint;
|
2237 |
|
|
}
|
2238 |
|
|
}
|
2239 |
|
|
|
2240 |
|
|
/* Extract from an array REGBUF containing the (raw) register state a
|
2241 |
|
|
function return value of type TYPE, and copy that, in virtual
|
2242 |
|
|
format, into VALBUF. */
|
2243 |
|
|
|
2244 |
|
|
static void
|
2245 |
|
|
arm_extract_return_value (struct type *type,
|
2246 |
|
|
char regbuf[REGISTER_BYTES],
|
2247 |
|
|
char *valbuf)
|
2248 |
|
|
{
|
2249 |
|
|
if (TYPE_CODE_FLT == TYPE_CODE (type))
|
2250 |
|
|
{
|
2251 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
2252 |
|
|
|
2253 |
|
|
switch (tdep->fp_model)
|
2254 |
|
|
{
|
2255 |
|
|
case ARM_FLOAT_FPA:
|
2256 |
|
|
convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)],
|
2257 |
|
|
valbuf);
|
2258 |
|
|
break;
|
2259 |
|
|
|
2260 |
|
|
case ARM_FLOAT_SOFT:
|
2261 |
|
|
case ARM_FLOAT_SOFT_VFP:
|
2262 |
|
|
memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)],
|
2263 |
|
|
TYPE_LENGTH (type));
|
2264 |
|
|
break;
|
2265 |
|
|
|
2266 |
|
|
default:
|
2267 |
|
|
internal_error
|
2268 |
|
|
(__FILE__, __LINE__,
|
2269 |
|
|
"arm_extract_return_value: Floating point model not supported");
|
2270 |
|
|
break;
|
2271 |
|
|
}
|
2272 |
|
|
}
|
2273 |
|
|
else
|
2274 |
|
|
memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)],
|
2275 |
|
|
TYPE_LENGTH (type));
|
2276 |
|
|
}
|
2277 |
|
|
|
2278 |
|
|
/* Extract from an array REGBUF containing the (raw) register state
|
2279 |
|
|
the address in which a function should return its structure value. */
|
2280 |
|
|
|
2281 |
|
|
static CORE_ADDR
|
2282 |
|
|
arm_extract_struct_value_address (char *regbuf)
|
2283 |
|
|
{
|
2284 |
|
|
return extract_address (regbuf, REGISTER_RAW_SIZE(ARM_A1_REGNUM));
|
2285 |
|
|
}
|
2286 |
|
|
|
2287 |
|
|
/* Will a function return an aggregate type in memory or in a
|
2288 |
|
|
register? Return 0 if an aggregate type can be returned in a
|
2289 |
|
|
register, 1 if it must be returned in memory. */
|
2290 |
|
|
|
2291 |
|
|
static int
|
2292 |
|
|
arm_use_struct_convention (int gcc_p, struct type *type)
|
2293 |
|
|
{
|
2294 |
|
|
int nRc;
|
2295 |
|
|
register enum type_code code;
|
2296 |
|
|
|
2297 |
|
|
/* In the ARM ABI, "integer" like aggregate types are returned in
|
2298 |
|
|
registers. For an aggregate type to be integer like, its size
|
2299 |
|
|
must be less than or equal to REGISTER_SIZE and the offset of
|
2300 |
|
|
each addressable subfield must be zero. Note that bit fields are
|
2301 |
|
|
not addressable, and all addressable subfields of unions always
|
2302 |
|
|
start at offset zero.
|
2303 |
|
|
|
2304 |
|
|
This function is based on the behaviour of GCC 2.95.1.
|
2305 |
|
|
See: gcc/arm.c: arm_return_in_memory() for details.
|
2306 |
|
|
|
2307 |
|
|
Note: All versions of GCC before GCC 2.95.2 do not set up the
|
2308 |
|
|
parameters correctly for a function returning the following
|
2309 |
|
|
structure: struct { float f;}; This should be returned in memory,
|
2310 |
|
|
not a register. Richard Earnshaw sent me a patch, but I do not
|
2311 |
|
|
know of any way to detect if a function like the above has been
|
2312 |
|
|
compiled with the correct calling convention. */
|
2313 |
|
|
|
2314 |
|
|
/* All aggregate types that won't fit in a register must be returned
|
2315 |
|
|
in memory. */
|
2316 |
|
|
if (TYPE_LENGTH (type) > REGISTER_SIZE)
|
2317 |
|
|
{
|
2318 |
|
|
return 1;
|
2319 |
|
|
}
|
2320 |
|
|
|
2321 |
|
|
/* The only aggregate types that can be returned in a register are
|
2322 |
|
|
structs and unions. Arrays must be returned in memory. */
|
2323 |
|
|
code = TYPE_CODE (type);
|
2324 |
|
|
if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
|
2325 |
|
|
{
|
2326 |
|
|
return 1;
|
2327 |
|
|
}
|
2328 |
|
|
|
2329 |
|
|
/* Assume all other aggregate types can be returned in a register.
|
2330 |
|
|
Run a check for structures, unions and arrays. */
|
2331 |
|
|
nRc = 0;
|
2332 |
|
|
|
2333 |
|
|
if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
|
2334 |
|
|
{
|
2335 |
|
|
int i;
|
2336 |
|
|
/* Need to check if this struct/union is "integer" like. For
|
2337 |
|
|
this to be true, its size must be less than or equal to
|
2338 |
|
|
REGISTER_SIZE and the offset of each addressable subfield
|
2339 |
|
|
must be zero. Note that bit fields are not addressable, and
|
2340 |
|
|
unions always start at offset zero. If any of the subfields
|
2341 |
|
|
is a floating point type, the struct/union cannot be an
|
2342 |
|
|
integer type. */
|
2343 |
|
|
|
2344 |
|
|
/* For each field in the object, check:
|
2345 |
|
|
1) Is it FP? --> yes, nRc = 1;
|
2346 |
|
|
2) Is it addressable (bitpos != 0) and
|
2347 |
|
|
not packed (bitsize == 0)?
|
2348 |
|
|
--> yes, nRc = 1
|
2349 |
|
|
*/
|
2350 |
|
|
|
2351 |
|
|
for (i = 0; i < TYPE_NFIELDS (type); i++)
|
2352 |
|
|
{
|
2353 |
|
|
enum type_code field_type_code;
|
2354 |
|
|
field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
|
2355 |
|
|
|
2356 |
|
|
/* Is it a floating point type field? */
|
2357 |
|
|
if (field_type_code == TYPE_CODE_FLT)
|
2358 |
|
|
{
|
2359 |
|
|
nRc = 1;
|
2360 |
|
|
break;
|
2361 |
|
|
}
|
2362 |
|
|
|
2363 |
|
|
/* If bitpos != 0, then we have to care about it. */
|
2364 |
|
|
if (TYPE_FIELD_BITPOS (type, i) != 0)
|
2365 |
|
|
{
|
2366 |
|
|
/* Bitfields are not addressable. If the field bitsize is
|
2367 |
|
|
zero, then the field is not packed. Hence it cannot be
|
2368 |
|
|
a bitfield or any other packed type. */
|
2369 |
|
|
if (TYPE_FIELD_BITSIZE (type, i) == 0)
|
2370 |
|
|
{
|
2371 |
|
|
nRc = 1;
|
2372 |
|
|
break;
|
2373 |
|
|
}
|
2374 |
|
|
}
|
2375 |
|
|
}
|
2376 |
|
|
}
|
2377 |
|
|
|
2378 |
|
|
return nRc;
|
2379 |
|
|
}
|
2380 |
|
|
|
2381 |
|
|
/* Write into appropriate registers a function return value of type
|
2382 |
|
|
TYPE, given in virtual format. */
|
2383 |
|
|
|
2384 |
|
|
static void
|
2385 |
|
|
arm_store_return_value (struct type *type, char *valbuf)
|
2386 |
|
|
{
|
2387 |
|
|
if (TYPE_CODE (type) == TYPE_CODE_FLT)
|
2388 |
|
|
{
|
2389 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
2390 |
|
|
char buf[ARM_MAX_REGISTER_RAW_SIZE];
|
2391 |
|
|
|
2392 |
|
|
switch (tdep->fp_model)
|
2393 |
|
|
{
|
2394 |
|
|
case ARM_FLOAT_FPA:
|
2395 |
|
|
|
2396 |
|
|
convert_to_extended (valbuf, buf);
|
2397 |
|
|
write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf,
|
2398 |
|
|
FP_REGISTER_RAW_SIZE);
|
2399 |
|
|
break;
|
2400 |
|
|
|
2401 |
|
|
case ARM_FLOAT_SOFT:
|
2402 |
|
|
case ARM_FLOAT_SOFT_VFP:
|
2403 |
|
|
write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type));
|
2404 |
|
|
break;
|
2405 |
|
|
|
2406 |
|
|
default:
|
2407 |
|
|
internal_error
|
2408 |
|
|
(__FILE__, __LINE__,
|
2409 |
|
|
"arm_store_return_value: Floating point model not supported");
|
2410 |
|
|
break;
|
2411 |
|
|
}
|
2412 |
|
|
}
|
2413 |
|
|
else
|
2414 |
|
|
write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type));
|
2415 |
|
|
}
|
2416 |
|
|
|
2417 |
|
|
/* Store the address of the place in which to copy the structure the
|
2418 |
|
|
subroutine will return. This is called from call_function. */
|
2419 |
|
|
|
2420 |
|
|
static void
|
2421 |
|
|
arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
|
2422 |
|
|
{
|
2423 |
|
|
write_register (ARM_A1_REGNUM, addr);
|
2424 |
|
|
}
|
2425 |
|
|
|
2426 |
|
|
static int
|
2427 |
|
|
arm_get_longjmp_target (CORE_ADDR *pc)
|
2428 |
|
|
{
|
2429 |
|
|
CORE_ADDR jb_addr;
|
2430 |
|
|
char buf[INT_REGISTER_RAW_SIZE];
|
2431 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
2432 |
|
|
|
2433 |
|
|
jb_addr = read_register (ARM_A1_REGNUM);
|
2434 |
|
|
|
2435 |
|
|
if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
|
2436 |
|
|
INT_REGISTER_RAW_SIZE))
|
2437 |
|
|
return 0;
|
2438 |
|
|
|
2439 |
|
|
*pc = extract_address (buf, INT_REGISTER_RAW_SIZE);
|
2440 |
|
|
return 1;
|
2441 |
|
|
}
|
2442 |
|
|
|
2443 |
|
|
/* Return non-zero if the PC is inside a thumb call thunk. */
|
2444 |
|
|
|
2445 |
|
|
int
|
2446 |
|
|
arm_in_call_stub (CORE_ADDR pc, char *name)
|
2447 |
|
|
{
|
2448 |
|
|
CORE_ADDR start_addr;
|
2449 |
|
|
|
2450 |
|
|
/* Find the starting address of the function containing the PC. If
|
2451 |
|
|
the caller didn't give us a name, look it up at the same time. */
|
2452 |
|
|
if (0 == find_pc_partial_function (pc, name ? NULL : &name,
|
2453 |
|
|
&start_addr, NULL))
|
2454 |
|
|
return 0;
|
2455 |
|
|
|
2456 |
|
|
return strncmp (name, "_call_via_r", 11) == 0;
|
2457 |
|
|
}
|
2458 |
|
|
|
2459 |
|
|
/* If PC is in a Thumb call or return stub, return the address of the
|
2460 |
|
|
target PC, which is in a register. The thunk functions are called
|
2461 |
|
|
_called_via_xx, where x is the register name. The possible names
|
2462 |
|
|
are r0-r9, sl, fp, ip, sp, and lr. */
|
2463 |
|
|
|
2464 |
|
|
CORE_ADDR
|
2465 |
|
|
arm_skip_stub (CORE_ADDR pc)
|
2466 |
|
|
{
|
2467 |
|
|
char *name;
|
2468 |
|
|
CORE_ADDR start_addr;
|
2469 |
|
|
|
2470 |
|
|
/* Find the starting address and name of the function containing the PC. */
|
2471 |
|
|
if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
|
2472 |
|
|
return 0;
|
2473 |
|
|
|
2474 |
|
|
/* Call thunks always start with "_call_via_". */
|
2475 |
|
|
if (strncmp (name, "_call_via_", 10) == 0)
|
2476 |
|
|
{
|
2477 |
|
|
/* Use the name suffix to determine which register contains the
|
2478 |
|
|
target PC. */
|
2479 |
|
|
static char *table[15] =
|
2480 |
|
|
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
2481 |
|
|
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
|
2482 |
|
|
};
|
2483 |
|
|
int regno;
|
2484 |
|
|
|
2485 |
|
|
for (regno = 0; regno <= 14; regno++)
|
2486 |
|
|
if (strcmp (&name[10], table[regno]) == 0)
|
2487 |
|
|
return read_register (regno);
|
2488 |
|
|
}
|
2489 |
|
|
|
2490 |
|
|
return 0; /* not a stub */
|
2491 |
|
|
}
|
2492 |
|
|
|
2493 |
|
|
/* If the user changes the register disassembly flavor used for info
|
2494 |
|
|
register and other commands, we have to also switch the flavor used
|
2495 |
|
|
in opcodes for disassembly output. This function is run in the set
|
2496 |
|
|
disassembly_flavor command, and does that. */
|
2497 |
|
|
|
2498 |
|
|
static void
|
2499 |
|
|
set_disassembly_flavor_sfunc (char *args, int from_tty,
|
2500 |
|
|
struct cmd_list_element *c)
|
2501 |
|
|
{
|
2502 |
|
|
set_disassembly_flavor ();
|
2503 |
|
|
}
|
2504 |
|
|
|
2505 |
|
|
/* Return the ARM register name corresponding to register I. */
|
2506 |
|
|
static const char *
|
2507 |
|
|
arm_register_name (int i)
|
2508 |
|
|
{
|
2509 |
|
|
return arm_register_names[i];
|
2510 |
|
|
}
|
2511 |
|
|
|
2512 |
|
|
static void
|
2513 |
|
|
set_disassembly_flavor (void)
|
2514 |
|
|
{
|
2515 |
|
|
const char *setname, *setdesc, **regnames;
|
2516 |
|
|
int numregs, j;
|
2517 |
|
|
|
2518 |
|
|
/* Find the flavor that the user wants in the opcodes table. */
|
2519 |
|
|
int current = 0;
|
2520 |
|
|
numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
|
2521 |
|
|
while ((disassembly_flavor != setname)
|
2522 |
|
|
&& (current < num_flavor_options))
|
2523 |
|
|
get_arm_regnames (++current, &setname, &setdesc, ®names);
|
2524 |
|
|
current_option = current;
|
2525 |
|
|
|
2526 |
|
|
/* Fill our copy. */
|
2527 |
|
|
for (j = 0; j < numregs; j++)
|
2528 |
|
|
arm_register_names[j] = (char *) regnames[j];
|
2529 |
|
|
|
2530 |
|
|
/* Adjust case. */
|
2531 |
|
|
if (isupper (*regnames[ARM_PC_REGNUM]))
|
2532 |
|
|
{
|
2533 |
|
|
arm_register_names[ARM_FPS_REGNUM] = "FPS";
|
2534 |
|
|
arm_register_names[ARM_PS_REGNUM] = "CPSR";
|
2535 |
|
|
}
|
2536 |
|
|
else
|
2537 |
|
|
{
|
2538 |
|
|
arm_register_names[ARM_FPS_REGNUM] = "fps";
|
2539 |
|
|
arm_register_names[ARM_PS_REGNUM] = "cpsr";
|
2540 |
|
|
}
|
2541 |
|
|
|
2542 |
|
|
/* Synchronize the disassembler. */
|
2543 |
|
|
set_arm_regname_option (current);
|
2544 |
|
|
}
|
2545 |
|
|
|
2546 |
|
|
/* arm_othernames implements the "othernames" command. This is kind
|
2547 |
|
|
of hacky, and I prefer the set-show disassembly-flavor which is
|
2548 |
|
|
also used for the x86 gdb. I will keep this around, however, in
|
2549 |
|
|
case anyone is actually using it. */
|
2550 |
|
|
|
2551 |
|
|
static void
|
2552 |
|
|
arm_othernames (char *names, int n)
|
2553 |
|
|
{
|
2554 |
|
|
/* Circle through the various flavors. */
|
2555 |
|
|
current_option = (current_option + 1) % num_flavor_options;
|
2556 |
|
|
|
2557 |
|
|
disassembly_flavor = valid_flavors[current_option];
|
2558 |
|
|
set_disassembly_flavor ();
|
2559 |
|
|
}
|
2560 |
|
|
|
2561 |
|
|
/* Fetch, and possibly build, an appropriate link_map_offsets structure
|
2562 |
|
|
for ARM linux targets using the struct offsets defined in <link.h>.
|
2563 |
|
|
Note, however, that link.h is not actually referred to in this file.
|
2564 |
|
|
Instead, the relevant structs offsets were obtained from examining
|
2565 |
|
|
link.h. (We can't refer to link.h from this file because the host
|
2566 |
|
|
system won't necessarily have it, or if it does, the structs which
|
2567 |
|
|
it defines will refer to the host system, not the target). */
|
2568 |
|
|
|
2569 |
|
|
struct link_map_offsets *
|
2570 |
|
|
arm_linux_svr4_fetch_link_map_offsets (void)
|
2571 |
|
|
{
|
2572 |
|
|
static struct link_map_offsets lmo;
|
2573 |
|
|
static struct link_map_offsets *lmp = 0;
|
2574 |
|
|
|
2575 |
|
|
if (lmp == 0)
|
2576 |
|
|
{
|
2577 |
|
|
lmp = &lmo;
|
2578 |
|
|
|
2579 |
|
|
lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
|
2580 |
|
|
need. */
|
2581 |
|
|
|
2582 |
|
|
lmo.r_map_offset = 4;
|
2583 |
|
|
lmo.r_map_size = 4;
|
2584 |
|
|
|
2585 |
|
|
lmo.link_map_size = 20; /* Actual size is 552, but this is all we
|
2586 |
|
|
need. */
|
2587 |
|
|
|
2588 |
|
|
lmo.l_addr_offset = 0;
|
2589 |
|
|
lmo.l_addr_size = 4;
|
2590 |
|
|
|
2591 |
|
|
lmo.l_name_offset = 4;
|
2592 |
|
|
lmo.l_name_size = 4;
|
2593 |
|
|
|
2594 |
|
|
lmo.l_next_offset = 12;
|
2595 |
|
|
lmo.l_next_size = 4;
|
2596 |
|
|
|
2597 |
|
|
lmo.l_prev_offset = 16;
|
2598 |
|
|
lmo.l_prev_size = 4;
|
2599 |
|
|
}
|
2600 |
|
|
|
2601 |
|
|
return lmp;
|
2602 |
|
|
}
|
2603 |
|
|
|
2604 |
|
|
/* Test whether the coff symbol specific value corresponds to a Thumb
|
2605 |
|
|
function. */
|
2606 |
|
|
|
2607 |
|
|
static int
|
2608 |
|
|
coff_sym_is_thumb (int val)
|
2609 |
|
|
{
|
2610 |
|
|
return (val == C_THUMBEXT ||
|
2611 |
|
|
val == C_THUMBSTAT ||
|
2612 |
|
|
val == C_THUMBEXTFUNC ||
|
2613 |
|
|
val == C_THUMBSTATFUNC ||
|
2614 |
|
|
val == C_THUMBLABEL);
|
2615 |
|
|
}
|
2616 |
|
|
|
2617 |
|
|
/* arm_coff_make_msymbol_special()
|
2618 |
|
|
arm_elf_make_msymbol_special()
|
2619 |
|
|
|
2620 |
|
|
These functions test whether the COFF or ELF symbol corresponds to
|
2621 |
|
|
an address in thumb code, and set a "special" bit in a minimal
|
2622 |
|
|
symbol to indicate that it does. */
|
2623 |
|
|
|
2624 |
|
|
static void
|
2625 |
|
|
arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
|
2626 |
|
|
{
|
2627 |
|
|
/* Thumb symbols are of type STT_LOPROC, (synonymous with
|
2628 |
|
|
STT_ARM_TFUNC). */
|
2629 |
|
|
if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
|
2630 |
|
|
== STT_LOPROC)
|
2631 |
|
|
MSYMBOL_SET_SPECIAL (msym);
|
2632 |
|
|
}
|
2633 |
|
|
|
2634 |
|
|
static void
|
2635 |
|
|
arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
|
2636 |
|
|
{
|
2637 |
|
|
if (coff_sym_is_thumb (val))
|
2638 |
|
|
MSYMBOL_SET_SPECIAL (msym);
|
2639 |
|
|
}
|
2640 |
|
|
|
2641 |
|
|
|
2642 |
|
|
static enum gdb_osabi
|
2643 |
|
|
arm_elf_osabi_sniffer (bfd *abfd)
|
2644 |
|
|
{
|
2645 |
|
|
unsigned int elfosabi, eflags;
|
2646 |
|
|
enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
|
2647 |
|
|
|
2648 |
|
|
elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
|
2649 |
|
|
|
2650 |
|
|
switch (elfosabi)
|
2651 |
|
|
{
|
2652 |
|
|
case ELFOSABI_NONE:
|
2653 |
|
|
/* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
|
2654 |
|
|
file are conforming to the base specification for that machine
|
2655 |
|
|
(there are no OS-specific extensions). In order to determine the
|
2656 |
|
|
real OS in use we must look for OS notes that have been added. */
|
2657 |
|
|
bfd_map_over_sections (abfd,
|
2658 |
|
|
generic_elf_osabi_sniff_abi_tag_sections,
|
2659 |
|
|
&osabi);
|
2660 |
|
|
if (osabi == GDB_OSABI_UNKNOWN)
|
2661 |
|
|
{
|
2662 |
|
|
/* Existing ARM tools don't set this field, so look at the EI_FLAGS
|
2663 |
|
|
field for more information. */
|
2664 |
|
|
eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
|
2665 |
|
|
switch (eflags)
|
2666 |
|
|
{
|
2667 |
|
|
case EF_ARM_EABI_VER1:
|
2668 |
|
|
osabi = GDB_OSABI_ARM_EABI_V1;
|
2669 |
|
|
break;
|
2670 |
|
|
|
2671 |
|
|
case EF_ARM_EABI_VER2:
|
2672 |
|
|
osabi = GDB_OSABI_ARM_EABI_V2;
|
2673 |
|
|
break;
|
2674 |
|
|
|
2675 |
|
|
case EF_ARM_EABI_UNKNOWN:
|
2676 |
|
|
/* Assume GNU tools. */
|
2677 |
|
|
osabi = GDB_OSABI_ARM_APCS;
|
2678 |
|
|
break;
|
2679 |
|
|
|
2680 |
|
|
default:
|
2681 |
|
|
internal_error (__FILE__, __LINE__,
|
2682 |
|
|
"arm_elf_osabi_sniffer: Unknown ARM EABI "
|
2683 |
|
|
"version 0x%x", eflags);
|
2684 |
|
|
}
|
2685 |
|
|
}
|
2686 |
|
|
break;
|
2687 |
|
|
|
2688 |
|
|
case ELFOSABI_ARM:
|
2689 |
|
|
/* GNU tools use this value. Check note sections in this case,
|
2690 |
|
|
as well. */
|
2691 |
|
|
bfd_map_over_sections (abfd,
|
2692 |
|
|
generic_elf_osabi_sniff_abi_tag_sections,
|
2693 |
|
|
&osabi);
|
2694 |
|
|
if (osabi == GDB_OSABI_UNKNOWN)
|
2695 |
|
|
{
|
2696 |
|
|
/* Assume APCS ABI. */
|
2697 |
|
|
osabi = GDB_OSABI_ARM_APCS;
|
2698 |
|
|
}
|
2699 |
|
|
break;
|
2700 |
|
|
|
2701 |
|
|
case ELFOSABI_FREEBSD:
|
2702 |
|
|
osabi = GDB_OSABI_FREEBSD_ELF;
|
2703 |
|
|
break;
|
2704 |
|
|
|
2705 |
|
|
case ELFOSABI_NETBSD:
|
2706 |
|
|
osabi = GDB_OSABI_NETBSD_ELF;
|
2707 |
|
|
break;
|
2708 |
|
|
|
2709 |
|
|
case ELFOSABI_LINUX:
|
2710 |
|
|
osabi = GDB_OSABI_LINUX;
|
2711 |
|
|
break;
|
2712 |
|
|
}
|
2713 |
|
|
|
2714 |
|
|
return osabi;
|
2715 |
|
|
}
|
2716 |
|
|
|
2717 |
|
|
|
2718 |
|
|
/* Initialize the current architecture based on INFO. If possible,
|
2719 |
|
|
re-use an architecture from ARCHES, which is a list of
|
2720 |
|
|
architectures already created during this debugging session.
|
2721 |
|
|
|
2722 |
|
|
Called e.g. at program startup, when reading a core file, and when
|
2723 |
|
|
reading a binary file. */
|
2724 |
|
|
|
2725 |
|
|
static struct gdbarch *
|
2726 |
|
|
arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
2727 |
|
|
{
|
2728 |
|
|
struct gdbarch_tdep *tdep;
|
2729 |
|
|
struct gdbarch *gdbarch;
|
2730 |
|
|
enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
|
2731 |
|
|
|
2732 |
|
|
/* Try to deterimine the ABI of the object we are loading. */
|
2733 |
|
|
|
2734 |
|
|
if (info.abfd != NULL)
|
2735 |
|
|
{
|
2736 |
|
|
osabi = gdbarch_lookup_osabi (info.abfd);
|
2737 |
|
|
if (osabi == GDB_OSABI_UNKNOWN)
|
2738 |
|
|
{
|
2739 |
|
|
switch (bfd_get_flavour (info.abfd))
|
2740 |
|
|
{
|
2741 |
|
|
case bfd_target_aout_flavour:
|
2742 |
|
|
/* Assume it's an old APCS-style ABI. */
|
2743 |
|
|
osabi = GDB_OSABI_ARM_APCS;
|
2744 |
|
|
break;
|
2745 |
|
|
|
2746 |
|
|
case bfd_target_coff_flavour:
|
2747 |
|
|
/* Assume it's an old APCS-style ABI. */
|
2748 |
|
|
/* XXX WinCE? */
|
2749 |
|
|
osabi = GDB_OSABI_ARM_APCS;
|
2750 |
|
|
break;
|
2751 |
|
|
|
2752 |
|
|
default:
|
2753 |
|
|
/* Leave it as "unknown". */
|
2754 |
|
|
}
|
2755 |
|
|
}
|
2756 |
|
|
}
|
2757 |
|
|
|
2758 |
|
|
/* Find a candidate among extant architectures. */
|
2759 |
|
|
for (arches = gdbarch_list_lookup_by_info (arches, &info);
|
2760 |
|
|
arches != NULL;
|
2761 |
|
|
arches = gdbarch_list_lookup_by_info (arches->next, &info))
|
2762 |
|
|
{
|
2763 |
|
|
/* Make sure the ABI selection matches. */
|
2764 |
|
|
tdep = gdbarch_tdep (arches->gdbarch);
|
2765 |
|
|
if (tdep && tdep->osabi == osabi)
|
2766 |
|
|
return arches->gdbarch;
|
2767 |
|
|
}
|
2768 |
|
|
|
2769 |
|
|
tdep = xmalloc (sizeof (struct gdbarch_tdep));
|
2770 |
|
|
gdbarch = gdbarch_alloc (&info, tdep);
|
2771 |
|
|
|
2772 |
|
|
tdep->osabi = osabi;
|
2773 |
|
|
|
2774 |
|
|
/* This is the way it has always defaulted. */
|
2775 |
|
|
tdep->fp_model = ARM_FLOAT_FPA;
|
2776 |
|
|
|
2777 |
|
|
/* Breakpoints. */
|
2778 |
|
|
switch (info.byte_order)
|
2779 |
|
|
{
|
2780 |
|
|
case BFD_ENDIAN_BIG:
|
2781 |
|
|
tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
|
2782 |
|
|
tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
|
2783 |
|
|
tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
|
2784 |
|
|
tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
|
2785 |
|
|
|
2786 |
|
|
break;
|
2787 |
|
|
|
2788 |
|
|
case BFD_ENDIAN_LITTLE:
|
2789 |
|
|
tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
|
2790 |
|
|
tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
|
2791 |
|
|
tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
|
2792 |
|
|
tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
|
2793 |
|
|
|
2794 |
|
|
break;
|
2795 |
|
|
|
2796 |
|
|
default:
|
2797 |
|
|
internal_error (__FILE__, __LINE__,
|
2798 |
|
|
"arm_gdbarch_init: bad byte order for float format");
|
2799 |
|
|
}
|
2800 |
|
|
|
2801 |
|
|
/* On ARM targets char defaults to unsigned. */
|
2802 |
|
|
set_gdbarch_char_signed (gdbarch, 0);
|
2803 |
|
|
|
2804 |
|
|
/* This should be low enough for everything. */
|
2805 |
|
|
tdep->lowest_pc = 0x20;
|
2806 |
|
|
tdep->jb_pc = -1; /* Longjump support not enabled by default. */
|
2807 |
|
|
|
2808 |
|
|
#if OLD_STYLE_ARM_DUMMY_FRAMES
|
2809 |
|
|
/* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
|
2810 |
|
|
specific (non-generic) dummy frame code. Might be useful if
|
2811 |
|
|
there appears to be a problem with the generic dummy frame
|
2812 |
|
|
mechanism that replaced it. */
|
2813 |
|
|
set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
|
2814 |
|
|
|
2815 |
|
|
/* Call dummy code. */
|
2816 |
|
|
set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
|
2817 |
|
|
set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
|
2818 |
|
|
/* We have to give this a value now, even though we will re-set it
|
2819 |
|
|
during each call to arm_fix_call_dummy. */
|
2820 |
|
|
set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8);
|
2821 |
|
|
set_gdbarch_call_dummy_p (gdbarch, 1);
|
2822 |
|
|
set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
|
2823 |
|
|
|
2824 |
|
|
set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
|
2825 |
|
|
set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words));
|
2826 |
|
|
set_gdbarch_call_dummy_start_offset (gdbarch, 0);
|
2827 |
|
|
set_gdbarch_call_dummy_length (gdbarch, 0);
|
2828 |
|
|
|
2829 |
|
|
set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy);
|
2830 |
|
|
|
2831 |
|
|
set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack);
|
2832 |
|
|
#else
|
2833 |
|
|
set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
|
2834 |
|
|
set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
|
2835 |
|
|
|
2836 |
|
|
set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
|
2837 |
|
|
set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
|
2838 |
|
|
|
2839 |
|
|
set_gdbarch_call_dummy_p (gdbarch, 1);
|
2840 |
|
|
set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
|
2841 |
|
|
|
2842 |
|
|
set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
|
2843 |
|
|
set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
|
2844 |
|
|
set_gdbarch_call_dummy_start_offset (gdbarch, 0);
|
2845 |
|
|
set_gdbarch_call_dummy_length (gdbarch, 0);
|
2846 |
|
|
|
2847 |
|
|
set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
|
2848 |
|
|
set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
|
2849 |
|
|
|
2850 |
|
|
set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
|
2851 |
|
|
set_gdbarch_push_return_address (gdbarch, arm_push_return_address);
|
2852 |
|
|
#endif
|
2853 |
|
|
|
2854 |
|
|
set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
|
2855 |
|
|
set_gdbarch_push_arguments (gdbarch, arm_push_arguments);
|
2856 |
|
|
set_gdbarch_coerce_float_to_double (gdbarch,
|
2857 |
|
|
standard_coerce_float_to_double);
|
2858 |
|
|
|
2859 |
|
|
/* Frame handling. */
|
2860 |
|
|
set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid);
|
2861 |
|
|
set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
|
2862 |
|
|
set_gdbarch_read_fp (gdbarch, arm_read_fp);
|
2863 |
|
|
set_gdbarch_frame_chain (gdbarch, arm_frame_chain);
|
2864 |
|
|
set_gdbarch_frameless_function_invocation
|
2865 |
|
|
(gdbarch, arm_frameless_function_invocation);
|
2866 |
|
|
set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc);
|
2867 |
|
|
set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
|
2868 |
|
|
set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
|
2869 |
|
|
set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
|
2870 |
|
|
set_gdbarch_frame_args_skip (gdbarch, 0);
|
2871 |
|
|
set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
|
2872 |
|
|
#if OLD_STYLE_ARM_DUMMY_FRAMES
|
2873 |
|
|
/* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
|
2874 |
|
|
specific (non-generic) dummy frame code. Might be useful if
|
2875 |
|
|
there appears to be a problem with the generic dummy frame
|
2876 |
|
|
mechanism that replaced it. */
|
2877 |
|
|
set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame);
|
2878 |
|
|
#else
|
2879 |
|
|
set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
|
2880 |
|
|
#endif
|
2881 |
|
|
set_gdbarch_pop_frame (gdbarch, arm_pop_frame);
|
2882 |
|
|
|
2883 |
|
|
/* Address manipulation. */
|
2884 |
|
|
set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
|
2885 |
|
|
set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
|
2886 |
|
|
|
2887 |
|
|
/* Offset from address of function to start of its code. */
|
2888 |
|
|
set_gdbarch_function_start_offset (gdbarch, 0);
|
2889 |
|
|
|
2890 |
|
|
/* Advance PC across function entry code. */
|
2891 |
|
|
set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
|
2892 |
|
|
|
2893 |
|
|
/* Get the PC when a frame might not be available. */
|
2894 |
|
|
set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
|
2895 |
|
|
|
2896 |
|
|
/* The stack grows downward. */
|
2897 |
|
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
2898 |
|
|
|
2899 |
|
|
/* Breakpoint manipulation. */
|
2900 |
|
|
set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
|
2901 |
|
|
set_gdbarch_decr_pc_after_break (gdbarch, 0);
|
2902 |
|
|
|
2903 |
|
|
/* Information about registers, etc. */
|
2904 |
|
|
set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
|
2905 |
|
|
set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
|
2906 |
|
|
set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
|
2907 |
|
|
set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
|
2908 |
|
|
set_gdbarch_register_byte (gdbarch, arm_register_byte);
|
2909 |
|
|
set_gdbarch_register_bytes (gdbarch,
|
2910 |
|
|
(NUM_GREGS * INT_REGISTER_RAW_SIZE
|
2911 |
|
|
+ NUM_FREGS * FP_REGISTER_RAW_SIZE
|
2912 |
|
|
+ NUM_SREGS * STATUS_REGISTER_SIZE));
|
2913 |
|
|
set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
|
2914 |
|
|
set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
|
2915 |
|
|
set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
|
2916 |
|
|
set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
|
2917 |
|
|
set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
|
2918 |
|
|
set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
|
2919 |
|
|
|
2920 |
|
|
/* Internal <-> external register number maps. */
|
2921 |
|
|
set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
|
2922 |
|
|
|
2923 |
|
|
/* Integer registers are 4 bytes. */
|
2924 |
|
|
set_gdbarch_register_size (gdbarch, 4);
|
2925 |
|
|
set_gdbarch_register_name (gdbarch, arm_register_name);
|
2926 |
|
|
|
2927 |
|
|
/* Returning results. */
|
2928 |
|
|
set_gdbarch_deprecated_extract_return_value (gdbarch, arm_extract_return_value);
|
2929 |
|
|
set_gdbarch_deprecated_store_return_value (gdbarch, arm_store_return_value);
|
2930 |
|
|
set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return);
|
2931 |
|
|
set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
|
2932 |
|
|
set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
|
2933 |
|
|
arm_extract_struct_value_address);
|
2934 |
|
|
|
2935 |
|
|
/* Single stepping. */
|
2936 |
|
|
/* XXX For an RDI target we should ask the target if it can single-step. */
|
2937 |
|
|
set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
|
2938 |
|
|
|
2939 |
|
|
/* Minsymbol frobbing. */
|
2940 |
|
|
set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
|
2941 |
|
|
set_gdbarch_coff_make_msymbol_special (gdbarch,
|
2942 |
|
|
arm_coff_make_msymbol_special);
|
2943 |
|
|
|
2944 |
|
|
/* Hook in the ABI-specific overrides, if they have been registered. */
|
2945 |
|
|
gdbarch_init_osabi (info, gdbarch, osabi);
|
2946 |
|
|
|
2947 |
|
|
/* Now we have tuned the configuration, set a few final things,
|
2948 |
|
|
based on what the OS ABI has told us. */
|
2949 |
|
|
|
2950 |
|
|
if (tdep->jb_pc >= 0)
|
2951 |
|
|
set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
|
2952 |
|
|
|
2953 |
|
|
/* Floating point sizes and format. */
|
2954 |
|
|
switch (info.byte_order)
|
2955 |
|
|
{
|
2956 |
|
|
case BFD_ENDIAN_BIG:
|
2957 |
|
|
set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
|
2958 |
|
|
set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
|
2959 |
|
|
set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
|
2960 |
|
|
|
2961 |
|
|
break;
|
2962 |
|
|
|
2963 |
|
|
case BFD_ENDIAN_LITTLE:
|
2964 |
|
|
set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
|
2965 |
|
|
if (tdep->fp_model == ARM_FLOAT_VFP
|
2966 |
|
|
|| tdep->fp_model == ARM_FLOAT_SOFT_VFP)
|
2967 |
|
|
{
|
2968 |
|
|
set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
|
2969 |
|
|
set_gdbarch_long_double_format (gdbarch,
|
2970 |
|
|
&floatformat_ieee_double_little);
|
2971 |
|
|
}
|
2972 |
|
|
else
|
2973 |
|
|
{
|
2974 |
|
|
set_gdbarch_double_format
|
2975 |
|
|
(gdbarch, &floatformat_ieee_double_littlebyte_bigword);
|
2976 |
|
|
set_gdbarch_long_double_format
|
2977 |
|
|
(gdbarch, &floatformat_ieee_double_littlebyte_bigword);
|
2978 |
|
|
}
|
2979 |
|
|
break;
|
2980 |
|
|
|
2981 |
|
|
default:
|
2982 |
|
|
internal_error (__FILE__, __LINE__,
|
2983 |
|
|
"arm_gdbarch_init: bad byte order for float format");
|
2984 |
|
|
}
|
2985 |
|
|
|
2986 |
|
|
/* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
|
2987 |
|
|
references the old architecture vector, not the one we are
|
2988 |
|
|
building here. */
|
2989 |
|
|
if (prologue_cache.saved_regs != NULL)
|
2990 |
|
|
xfree (prologue_cache.saved_regs);
|
2991 |
|
|
|
2992 |
|
|
/* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
|
2993 |
|
|
references the old architecture vector, not the one we are
|
2994 |
|
|
building here. */
|
2995 |
|
|
prologue_cache.saved_regs = (CORE_ADDR *)
|
2996 |
|
|
xcalloc (1, (sizeof (CORE_ADDR)
|
2997 |
|
|
* (gdbarch_num_regs (gdbarch)
|
2998 |
|
|
+ gdbarch_num_pseudo_regs (gdbarch))));
|
2999 |
|
|
|
3000 |
|
|
return gdbarch;
|
3001 |
|
|
}
|
3002 |
|
|
|
3003 |
|
|
static void
|
3004 |
|
|
arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
|
3005 |
|
|
{
|
3006 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
|
3007 |
|
|
|
3008 |
|
|
if (tdep == NULL)
|
3009 |
|
|
return;
|
3010 |
|
|
|
3011 |
|
|
fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n",
|
3012 |
|
|
gdbarch_osabi_name (tdep->osabi));
|
3013 |
|
|
|
3014 |
|
|
fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
|
3015 |
|
|
(unsigned long) tdep->lowest_pc);
|
3016 |
|
|
}
|
3017 |
|
|
|
3018 |
|
|
static void
|
3019 |
|
|
arm_init_abi_eabi_v1 (struct gdbarch_info info,
|
3020 |
|
|
struct gdbarch *gdbarch)
|
3021 |
|
|
{
|
3022 |
|
|
/* Place-holder. */
|
3023 |
|
|
}
|
3024 |
|
|
|
3025 |
|
|
static void
|
3026 |
|
|
arm_init_abi_eabi_v2 (struct gdbarch_info info,
|
3027 |
|
|
struct gdbarch *gdbarch)
|
3028 |
|
|
{
|
3029 |
|
|
/* Place-holder. */
|
3030 |
|
|
}
|
3031 |
|
|
|
3032 |
|
|
static void
|
3033 |
|
|
arm_init_abi_apcs (struct gdbarch_info info,
|
3034 |
|
|
struct gdbarch *gdbarch)
|
3035 |
|
|
{
|
3036 |
|
|
/* Place-holder. */
|
3037 |
|
|
}
|
3038 |
|
|
|
3039 |
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void
|
3040 |
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_initialize_arm_tdep (void)
|
3041 |
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{
|
3042 |
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struct ui_file *stb;
|
3043 |
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long length;
|
3044 |
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struct cmd_list_element *new_cmd;
|
3045 |
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const char *setname;
|
3046 |
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const char *setdesc;
|
3047 |
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const char **regnames;
|
3048 |
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int numregs, i, j;
|
3049 |
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static char *helptext;
|
3050 |
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|
3051 |
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if (GDB_MULTI_ARCH)
|
3052 |
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gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
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3053 |
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|
3054 |
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/* Register an ELF OS ABI sniffer for ARM binaries. */
|
3055 |
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gdbarch_register_osabi_sniffer (bfd_arch_arm,
|
3056 |
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bfd_target_elf_flavour,
|
3057 |
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arm_elf_osabi_sniffer);
|
3058 |
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|
3059 |
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/* Register some ABI variants for embedded systems. */
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3060 |
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gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V1,
|
3061 |
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arm_init_abi_eabi_v1);
|
3062 |
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gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V2,
|
3063 |
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arm_init_abi_eabi_v2);
|
3064 |
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gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_APCS,
|
3065 |
|
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arm_init_abi_apcs);
|
3066 |
|
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|
3067 |
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tm_print_insn = gdb_print_insn_arm;
|
3068 |
|
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|
3069 |
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/* Get the number of possible sets of register names defined in opcodes. */
|
3070 |
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num_flavor_options = get_arm_regname_num_options ();
|
3071 |
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|
3072 |
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/* Sync the opcode insn printer with our register viewer. */
|
3073 |
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parse_arm_disassembler_option ("reg-names-std");
|
3074 |
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|
3075 |
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/* Begin creating the help text. */
|
3076 |
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stb = mem_fileopen ();
|
3077 |
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fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
|
3078 |
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The valid values are:\n");
|
3079 |
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|
3080 |
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/* Initialize the array that will be passed to add_set_enum_cmd(). */
|
3081 |
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valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
|
3082 |
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for (i = 0; i < num_flavor_options; i++)
|
3083 |
|
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{
|
3084 |
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numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
|
3085 |
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valid_flavors[i] = setname;
|
3086 |
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fprintf_unfiltered (stb, "%s - %s\n", setname,
|
3087 |
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setdesc);
|
3088 |
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/* Copy the default names (if found) and synchronize disassembler. */
|
3089 |
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if (!strcmp (setname, "std"))
|
3090 |
|
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{
|
3091 |
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disassembly_flavor = setname;
|
3092 |
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current_option = i;
|
3093 |
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for (j = 0; j < numregs; j++)
|
3094 |
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arm_register_names[j] = (char *) regnames[j];
|
3095 |
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set_arm_regname_option (i);
|
3096 |
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}
|
3097 |
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}
|
3098 |
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/* Mark the end of valid options. */
|
3099 |
|
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valid_flavors[num_flavor_options] = NULL;
|
3100 |
|
|
|
3101 |
|
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/* Finish the creation of the help text. */
|
3102 |
|
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fprintf_unfiltered (stb, "The default is \"std\".");
|
3103 |
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helptext = ui_file_xstrdup (stb, &length);
|
3104 |
|
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ui_file_delete (stb);
|
3105 |
|
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|
3106 |
|
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/* Add the disassembly-flavor command. */
|
3107 |
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new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
|
3108 |
|
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valid_flavors,
|
3109 |
|
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&disassembly_flavor,
|
3110 |
|
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helptext,
|
3111 |
|
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&setlist);
|
3112 |
|
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set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc);
|
3113 |
|
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add_show_from_set (new_cmd, &showlist);
|
3114 |
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|
3115 |
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/* ??? Maybe this should be a boolean. */
|
3116 |
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add_show_from_set (add_set_cmd ("apcs32", no_class,
|
3117 |
|
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var_zinteger, (char *) &arm_apcs_32,
|
3118 |
|
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"Set usage of ARM 32-bit mode.\n", &setlist),
|
3119 |
|
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&showlist);
|
3120 |
|
|
|
3121 |
|
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/* Add the deprecated "othernames" command. */
|
3122 |
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|
3123 |
|
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add_com ("othernames", class_obscure, arm_othernames,
|
3124 |
|
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"Switch to the next set of register names.");
|
3125 |
|
|
|
3126 |
|
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/* Fill in the prologue_cache fields. */
|
3127 |
|
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prologue_cache.saved_regs = NULL;
|
3128 |
|
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prologue_cache.extra_info = (struct frame_extra_info *)
|
3129 |
|
|
xcalloc (1, sizeof (struct frame_extra_info));
|
3130 |
|
|
|
3131 |
|
|
/* Debugging flag. */
|
3132 |
|
|
add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger,
|
3133 |
|
|
&arm_debug, "Set arm debugging.\n\
|
3134 |
|
|
When non-zero, arm specific debugging is enabled.", &setdebuglist),
|
3135 |
|
|
&showdebuglist);
|
3136 |
|
|
}
|