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[/] [or1k/] [trunk/] [gdb-5.3/] [gdb/] [arm-tdep.h] - Blame information for rev 1765

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1 1181 sfurman
/* Common target dependent code for GDB on ARM systems.
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   Copyright 2002 Free Software Foundation, Inc.
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   This file is part of GDB.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 2 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place - Suite 330,
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   Boston, MA 02111-1307, USA.  */
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#include "osabi.h"
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/* Register numbers of various important registers.  Note that some of
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   these values are "real" register numbers, and correspond to the
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   general registers of the machine, and some are "phony" register
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   numbers which are too large to be actual register numbers as far as
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   the user is concerned but do serve to get the desired values when
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   passed to read_register.  */
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enum gdb_regnum {
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  ARM_A1_REGNUM = 0,             /* first integer-like argument */
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  ARM_A4_REGNUM = 3,            /* last integer-like argument */
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  ARM_AP_REGNUM = 11,
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  ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
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  ARM_LR_REGNUM = 14,           /* address to return to from a function call */
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  ARM_PC_REGNUM = 15,           /* Contains program counter */
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  ARM_F0_REGNUM = 16,           /* first floating point register */
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  ARM_F3_REGNUM = 19,           /* last floating point argument register */
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  ARM_F7_REGNUM = 23,           /* last floating point register */
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  ARM_FPS_REGNUM = 24,          /* floating point status register */
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  ARM_PS_REGNUM = 25,           /* Contains processor status */
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  ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
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  THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
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  ARM_NUM_ARG_REGS = 4,
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  ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
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  ARM_NUM_FP_ARG_REGS = 4,
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  ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
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};
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/* Used in target-specific code when we need to know the size of the
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   largest type of register we need to handle.  */
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#define ARM_MAX_REGISTER_RAW_SIZE       12
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#define ARM_MAX_REGISTER_VIRTUAL_SIZE   8
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/* Size of integer registers.  */
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#define INT_REGISTER_RAW_SIZE           4
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#define INT_REGISTER_VIRTUAL_SIZE       4
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/* Say how long FP registers are.  Used for documentation purposes and
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   code readability in this header.  IEEE extended doubles are 80
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   bits.  DWORD aligned they use 96 bits.  */
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#define FP_REGISTER_RAW_SIZE    12
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/* GCC doesn't support long doubles (extended IEEE values).  The FP
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   register virtual size is therefore 64 bits.  Used for documentation
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   purposes and code readability in this header.  */
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#define FP_REGISTER_VIRTUAL_SIZE        8
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/* Status registers are the same size as general purpose registers.
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   Used for documentation purposes and code readability in this
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   header.  */
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#define STATUS_REGISTER_SIZE    4
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/* Number of machine registers.  The only define actually required
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   is NUM_REGS.  The other definitions are used for documentation
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   purposes and code readability.  */
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/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
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   (and called PS for processor status) so the status bits can be cleared
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   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
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   in PS.  */
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#define NUM_FREGS       8       /* Number of floating point registers.  */
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#define NUM_SREGS       2       /* Number of status registers.  */
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#define NUM_GREGS       16      /* Number of general purpose registers.  */
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/* Instruction condition field values.  */
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#define INST_EQ         0x0
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#define INST_NE         0x1
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#define INST_CS         0x2
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#define INST_CC         0x3
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#define INST_MI         0x4
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#define INST_PL         0x5
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#define INST_VS         0x6
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#define INST_VC         0x7
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#define INST_HI         0x8
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#define INST_LS         0x9
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#define INST_GE         0xa
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#define INST_LT         0xb
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#define INST_GT         0xc
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#define INST_LE         0xd
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#define INST_AL         0xe
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#define INST_NV         0xf
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#define FLAG_N          0x80000000
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#define FLAG_Z          0x40000000
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#define FLAG_C          0x20000000
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#define FLAG_V          0x10000000
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/* Type of floating-point code in use by inferior.  There are really 3 models
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   that are traditionally supported (plus the endianness issue), but gcc can
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   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
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   functions are passed in floating-point registers.
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   In addition to the traditional models, VFP adds two more.  */
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enum arm_float_model
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{
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  ARM_FLOAT_SOFT,
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  ARM_FLOAT_FPA,
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  ARM_FLOAT_SOFT_VFP,
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  ARM_FLOAT_VFP
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};
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/* Target-dependent structure in gdbarch.  */
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struct gdbarch_tdep
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{
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  enum gdb_osabi osabi;         /* OS/ABI of inferior.  */
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  enum arm_float_model fp_model; /* Floating point calling conventions.  */
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  CORE_ADDR lowest_pc;          /* Lowest address at which instructions
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                                   will appear.  */
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  const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
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  int arm_breakpoint_size;      /* And its size.  */
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  const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn.  */
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  int thumb_breakpoint_size;    /* And its size.  */
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  int jb_pc;                    /* Offset to PC value in jump buffer.
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                                   If this is negative, longjmp support
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                                   will be disabled.  */
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  size_t jb_elt_size;           /* And the size of each entry in the buf.  */
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};
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#ifndef LOWEST_PC
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#define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
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#endif
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/* Prototypes for internal interfaces needed by more than one MD file.  */
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int arm_pc_is_thumb_dummy (CORE_ADDR);
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int arm_pc_is_thumb (CORE_ADDR);
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CORE_ADDR thumb_get_next_pc (CORE_ADDR);
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CORE_ADDR arm_get_next_pc (CORE_ADDR);

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