OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.3/] [gdb/] [rdi-share/] [angel_bytesex.c] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1181 sfurman
/*
2
 * Copyright (C) 1995 Advanced RISC Machines Limited. All rights reserved.
3
 *
4
 * This software may be freely used, copied, modified, and distributed
5
 * provided that the above copyright notice is preserved in all copies of the
6
 * software.
7
 */
8
 
9
/*
10
 * angel_bytesex.c - Code to support byte-sex independence
11
 * Copyright: (C) 1991, Advanced RISC Machines Ltd., Cambridge, England.
12
 */
13
 
14
/*
15 1183 sfurman
 * RCS $Revision: 1.2 $
16
 * Checkin $Date: 2003-08-15 01:06:10 $
17 1181 sfurman
 */
18
 
19
#include "angel_bytesex.h"
20
 
21
static int reversing_bytes = 0;
22
 
23
void bytesex_reverse(yes_or_no)
24
int yes_or_no;
25
{ reversing_bytes = yes_or_no;
26
}
27
 
28
int bytesex_reversing()
29
{
30
  return reversing_bytes;
31
}
32
 
33
int32 bytesex_hostval(v)
34
int32 v;
35
{ /* Return v with the same endian-ness as the host */
36
  /* This mess generates better ARM code than the more obvious mess */
37
  /* and may eventually peephole to optimal code...                 */
38
  if (reversing_bytes)
39
  { unsigned32 t;
40
    /* t = v ^ (v ror 16) */
41
    t = v ^ ((v << 16) | (((unsigned32)v) >> 16));
42
    t &= ~0xff0000;
43
    /* v = v ror 8 */
44
    v = (v << 24) | (((unsigned32)v) >> 8);
45
    v = v ^ (t >> 8);
46
  }
47
  return v;
48
}
49
 
50
int32 bytesex_hostval_16(v)
51
int32 v;
52
{
53
  if (reversing_bytes) {
54
    v = ((v >> 8) & 0xff) | ((v << 8) & 0xff00);
55
  }
56
  return v;
57
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.