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[/] [or1k/] [trunk/] [gdb-5.3/] [include/] [opcode/] [m68k.h] - Blame information for rev 1765

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1 1181 sfurman
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
2
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001
3
   Free Software Foundation, Inc.
4
 
5
This file is part of GDB, GAS, and the GNU binutils.
6
 
7
GDB, GAS, and the GNU binutils are free software; you can redistribute
8
them and/or modify them under the terms of the GNU General Public
9
License as published by the Free Software Foundation; either version
10
1, or (at your option) any later version.
11
 
12
GDB, GAS, and the GNU binutils are distributed in the hope that they
13
will be useful, but WITHOUT ANY WARRANTY; without even the implied
14
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15
the GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this file; see the file COPYING.  If not, write to the Free
19
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA.  */
21
 
22
/* These are used as bit flags for the arch field in the m68k_opcode
23
   structure.  */
24
#define _m68k_undef  0
25
#define m68000  0x001
26
#define m68008  m68000 /* synonym for -m68000.  otherwise unused. */
27
#define m68010  0x002
28
#define m68020  0x004
29
#define m68030  0x008
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#define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
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                           gas will deal with the few differences.  */
32
#define m68040  0x010
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/* there is no 68050 */
34
#define m68060  0x020
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#define m68881  0x040
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#define m68882  m68881 /* synonym for -m68881.  otherwise unused. */
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#define m68851  0x080
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#define cpu32   0x100   /* e.g., 68332 */
39
#define mcf5200 0x200
40
#define mcf5206e 0x400
41
#define mcf5307 0x800
42
#define mcf5407 0x1000
43
 
44
 /* handy aliases */
45
#define m68040up  (m68040 | m68060)
46
#define m68030up  (m68030 | m68040up)
47
#define m68020up  (m68020 | m68030up)
48
#define m68010up  (m68010 | cpu32 | m68020up)
49
#define m68000up  (m68000 | m68010up)
50
#define mcf       (mcf5200 | mcf5206e | mcf5307 | mcf5407)
51
#define mcf5307up (mcf5307 | mcf5407)
52
 
53
#define mfloat  (m68881 | m68882 | m68040 | m68060)
54
#define mmmu    (m68851 | m68030 | m68040 | m68060)
55
 
56
/* The structure used to hold information for an opcode.  */
57
 
58
struct m68k_opcode
59
{
60
  /* The opcode name.  */
61
  const char *name;
62
  /* The opcode itself.  */
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  unsigned long opcode;
64
  /* The mask used by the disassembler.  */
65
  unsigned long match;
66
  /* The arguments.  */
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  const char *args;
68
  /* The architectures which support this opcode.  */
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  unsigned int arch;
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};
71
 
72
/* The structure used to hold information for an opcode alias.  */
73
 
74
struct m68k_opcode_alias
75
{
76
  /* The alias name.  */
77
  const char *alias;
78
  /* The instruction for which this is an alias.  */
79
  const char *primary;
80
};
81
 
82
/* We store four bytes of opcode for all opcodes because that is the
83
   most any of them need.  The actual length of an instruction is
84
   always at least 2 bytes, and is as much longer as necessary to hold
85
   the operands it has.
86
 
87
   The match field is a mask saying which bits must match particular
88
   opcode in order for an instruction to be an instance of that
89
   opcode.
90
 
91
   The args field is a string containing two characters for each
92
   operand of the instruction.  The first specifies the kind of
93
   operand; the second, the place it is stored.  */
94
 
95
/* Kinds of operands:
96
   Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
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98
   D  data register only.  Stored as 3 bits.
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   A  address register only.  Stored as 3 bits.
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   a  address register indirect only.  Stored as 3 bits.
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   R  either kind of register.  Stored as 4 bits.
102
   r  either kind of register indirect only.  Stored as 4 bits.
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      At the moment, used only for cas2 instruction.
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   F  floating point coprocessor register only.   Stored as 3 bits.
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   O  an offset (or width): immediate data 0-31 or data register.
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      Stored as 6 bits in special format for BF... insns.
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   +  autoincrement only.  Stored as 3 bits (number of the address register).
108
   -  autodecrement only.  Stored as 3 bits (number of the address register).
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   Q  quick immediate data.  Stored as 3 bits.
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      This matches an immediate operand only when value is in range 1 .. 8.
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   M  moveq immediate data.  Stored as 8 bits.
112
      This matches an immediate operand only when value is in range -128..127
113
   T  trap vector immediate data.  Stored as 4 bits.
114
 
115
   k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
116
      a three bit register offset, depending on the field type.
117
 
118
   #  immediate data.  Stored in special places (b, w or l)
119
      which say how many bits to store.
120
   ^  immediate data for floating point instructions.   Special places
121
      are offset by 2 bytes from '#'...
122
   B  pc-relative address, converted to an offset
123
      that is treated as immediate data.
124
   d  displacement and register.  Stores the register as 3 bits
125
      and stores the displacement in the entire second word.
126
 
127
   C  the CCR.  No need to store it; this is just for filtering validity.
128
   S  the SR.  No need to store, just as with CCR.
129
   U  the USP.  No need to store, just as with CCR.
130
   E  the ACC.  No need to store, just as with CCR.
131
   G  the MACSR.  No need to store, just as with CCR.
132
   H  the MASK.  No need to store, just as with CCR.
133
 
134
   I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
135
      extracted from the 'd' field of word one, which means that an extended
136
      coprocessor opcode can be skipped using the 'i' place, if needed.
137
 
138
   s  System Control register for the floating point coprocessor.
139
 
140
   J  Misc register for movec instruction, stored in 'j' format.
141
        Possible values:
142
        0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
143
        0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
144
        0x002   CACR    Cache Control Register          [60, 40, 30, 20]
145
        0x003   TC      MMU Translation Control         [60, 40]
146
        0x004   ITT0    Instruction Transparent
147
                                Translation reg 0       [60, 40]
148
        0x005   ITT1    Instruction Transparent
149
                                Translation reg 1       [60, 40]
150
        0x006   DTT0    Data Transparent
151
                                Translation reg 0       [60, 40]
152
        0x007   DTT1    Data Transparent
153
                                Translation reg 1       [60, 40]
154
        0x008   BUSCR   Bus Control Register            [60]
155
        0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
156
        0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10]
157
        0x802   CAAR    Cache Address Register          [        30, 20]
158
        0x803   MSP     Master Stack Pointer            [    40, 30, 20]
159
        0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
160
        0x805   MMUSR   MMU Status reg                  [    40]
161
        0x806   URP     User Root Pointer               [60, 40]
162
        0x807   SRP     Supervisor Root Pointer         [60, 40]
163
        0x808   PCR     Processor Configuration reg     [60]
164
        0xC00   ROMBAR  ROM Base Address Register       [520X]
165
        0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
166
        0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
167
        0xC0F   MBAR0   RAM Base Address Register 0     [520X]
168
 
169
    L  Register list of the type d0-d7/a0-a7 etc.
170
       (New!  Improved!  Can also hold fp0-fp7, as well!)
171
       The assembler tries to see if the registers match the insn by
172
       looking at where the insn wants them stored.
173
 
174
    l  Register list like L, but with all the bits reversed.
175
       Used for going the other way. . .
176
 
177
    c  cache identifier which may be "nc" for no cache, "ic"
178
       for instruction cache, "dc" for data cache, or "bc"
179
       for both caches.  Used in cinv and cpush.  Always
180
       stored in position "d".
181
 
182
    u  Any register, with ``upper'' or ``lower'' specification.  Used
183
       in the mac instructions with size word.
184
 
185
 The remainder are all stored as 6 bits using an address mode and a
186
 register number; they differ in which addressing modes they match.
187
 
188
   *  all                                       (modes 0-6,7.0-4)
189
   ~  alterable memory                          (modes 2-6,7.0,7.1)
190
                                                (not 0,1,7.2-4)
191
   %  alterable                                 (modes 0-6,7.0,7.1)
192
                                                (not 7.2-4)
193
   ;  data                                      (modes 0,2-6,7.0-4)
194
                                                (not 1)
195
   @  data, but not immediate                   (modes 0,2-6,7.0-3)
196
                                                (not 1,7.4)
197
   !  control                                   (modes 2,5,6,7.0-3)
198
                                                (not 0,1,3,4,7.4)
199
   &  alterable control                         (modes 2,5,6,7.0,7.1)
200
                                                (not 0,1,7.2-4)
201
   $  alterable data                            (modes 0,2-6,7.0,7.1)
202
                                                (not 1,7.2-4)
203
   ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
204
                                                (not 1,3,4,7.2-4)
205
   /  control, or data register                 (modes 0,2,5,6,7.0-3)
206
                                                (not 1,3,4,7.4)
207
   >  *save operands                            (modes 2,4,5,6,7.0,7.1)
208
                                                (not 0,1,3,7.2-4)
209
   <  *restore operands                         (modes 2,3,5,6,7.0-3)
210
                                                (not 0,1,4,7.4)
211
 
212
   coldfire move operands:
213
   m                                            (modes 0-4)
214
   n                                            (modes 5,7.2)
215
   o                                            (modes 6,7.0,7.1,7.3,7.4)
216
   p                                            (modes 0-5)
217
 
218
   coldfire bset/bclr/btst/mulsl/mulul operands:
219
   q                                            (modes 0,2-5)
220
   v                                            (modes 0,2-5,7.0,7.1)
221
*/
222
 
223
/* For the 68851: */
224
/*
225
   I didn't use much imagination in choosing the
226
   following codes, so many of them aren't very
227
   mnemonic. -rab
228
 
229
 
230
        Possible values:
231
        000     TC      Translation Control Register (68030, 68851)
232
 
233
   1  16 bit pmmu register
234
        111     AC      Access Control (68851)
235
 
236
   2  8 bit pmmu register
237
        100     CAL     Current Access Level (68851)
238
        101     VAL     Validate Access Level (68851)
239
        110     SCC     Stack Change Control (68851)
240
 
241
   3  68030-only pmmu registers (32 bit)
242
        010     TT0     Transparent Translation reg 0
243
                        (aka Access Control reg 0 -- AC0 -- on 68ec030)
244
        011     TT1     Transparent Translation reg 1
245
                        (aka Access Control reg 1 -- AC1 -- on 68ec030)
246
 
247
   W  wide pmmu registers
248
        Possible values:
249
        001     DRP     Dma Root Pointer (68851)
250
        010     SRP     Supervisor Root Pointer (68030, 68851)
251
        011     CRP     Cpu Root Pointer (68030, 68851)
252
 
253
   f    function code register (68030, 68851)
254
 
255
        1       DFC
256
 
257
   V    VAL register only (68851)
258
 
259
   X    BADx, BACx (16 bit)
260
        100     BAD     Breakpoint Acknowledge Data (68851)
261
        101     BAC     Breakpoint Acknowledge Control (68851)
262
 
263
   Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
264
   Z    PCSR (68851)
265
 
266
   |    memory          (modes 2-6, 7.*)
267
 
268
   t  address test level (68030 only)
269
      Stored as 3 bits, range 0-7.
270
      Also used for breakpoint instruction now.
271
 
272
*/
273
 
274
/* Places to put an operand, for non-general operands:
275
   Characters used: BbCcDdghijkLlMmNnostWw123456789
276
 
277
   s  source, low bits of first word.
278
   d  dest, shifted 9 in first word
279
   1  second word, shifted 12
280
   2  second word, shifted 6
281
   3  second word, shifted 0
282
   4  third word, shifted 12
283
   5  third word, shifted 6
284
   6  third word, shifted 0
285
   7  second word, shifted 7
286
   8  second word, shifted 10
287
   9  second word, shifted 5
288
   D  store in both place 1 and place 3; for divul and divsl.
289
   B  first word, low byte, for branch displacements
290
   W  second word (entire), for branch displacements
291
   L  second and third words (entire), for branch displacements
292
      (also overloaded for move16)
293
   b  second word, low byte
294
   w  second word (entire) [variable word/long branch offset for dbra]
295
   W  second word (entire) (must be signed 16 bit value)
296
   l  second and third word (entire)
297
   g  variable branch offset for bra and similar instructions.
298
      The place to store depends on the magnitude of offset.
299
   t  store in both place 7 and place 8; for floating point operations
300
   c  branch offset for cpBcc operations.
301
      The place to store is word two if bit six of word one is zero,
302
      and words two and three if bit six of word one is one.
303
   i  Increment by two, to skip over coprocessor extended operands.   Only
304
      works with the 'I' format.
305
   k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
306
      Also used for dynamic fmovem instruction.
307
   C  floating point coprocessor constant - 7 bits.  Also used for static
308
      K-factors...
309
   j  Movec register #, stored in 12 low bits of second word.
310
   m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
311
      and remaining 3 bits of register shifted 9 bits in first word.
312
      Indicate upper/lower in 1 bit shifted 7 bits in second word.
313
      Use with `R' or `u' format.
314
   n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
315
      with MSB shifted 6 bits in first word and remaining 3 bits of
316
      register shifted 9 bits in first word.  No upper/lower
317
      indication is done.)  Use with `R' or `u' format.
318
   o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
319
      Indicate upper/lower in 1 bit shifted 7 bits in second word.
320
      Use with `R' or `u' format.
321
   M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
322
      upper/lower in 1 bit shifted 6 bits in second word.  Use with
323
      `R' or `u' format.
324
   N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
325
      upper/lower in 1 bit shifted 6 bits in second word.  Use with
326
      `R' or `u' format.
327
   h  shift indicator (scale factor), 1 bit shifted 10 in second word
328
 
329
 Places to put operand, for general operands:
330
   d  destination, shifted 6 bits in first word
331
   b  source, at low bit of first word, and immediate uses one byte
332
   w  source, at low bit of first word, and immediate uses two bytes
333
   l  source, at low bit of first word, and immediate uses four bytes
334
   s  source, at low bit of first word.
335
      Used sometimes in contexts where immediate is not allowed anyway.
336
   f  single precision float, low bit of 1st word, immediate uses 4 bytes
337
   F  double precision float, low bit of 1st word, immediate uses 8 bytes
338
   x  extended precision float, low bit of 1st word, immediate uses 12 bytes
339
   p  packed float, low bit of 1st word, immediate uses 12 bytes
340
*/
341
 
342
extern const struct m68k_opcode m68k_opcodes[];
343
extern const struct m68k_opcode_alias m68k_opcode_aliases[];
344
 
345
extern const int m68k_numopcodes, m68k_numaliases;
346
 
347
/* end of m68k-opcode.h */

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