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/* Table of opcodes for the Texas Instruments TMS320C[34]X family.

   Copyright (c) 2002 Free Software Foundation.

   Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/* FIXME:  Only allow floating point registers for floating point

   instructions.  Use another field in the instruction table?

   This field could also flag which instructions are valid for

   which architectures...

   e.g., OP_FP | OP_C40  or OP_C40_FP  */

#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32)

#define IS_CPU_C4X(v) ((v) ==  0 || (v) == 40 || (v) == 44)

/* Define some bitfield extraction/insertion macros.  */

#define EXTR(inst, m, l)          ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) 

#define EXTRU(inst, m, l)         EXTR ((unsigned long)(inst), (m), (l))

#define EXTRS(inst, m, l)         EXTR ((long)(inst), (m), (l))

#define INSERTU(inst, val, m, l)  (inst |= ((val) << (l))) 

#define INSERTS(inst, val, m, l)  INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)

/* Define register numbers.  */

typedef enum

  {

    REG_R0, REG_R1, REG_R2, REG_R3,

    REG_R4, REG_R5, REG_R6, REG_R7,

    REG_AR0, REG_AR1, REG_AR2, REG_AR3,

    REG_AR4, REG_AR5, REG_AR6, REG_AR7,

    REG_DP, REG_IR0, REG_IR1, REG_BK,

    REG_SP, REG_ST, REG_DIE, REG_IIE,

    REG_IIF, REG_RS, REG_RE, REG_RC,

    REG_R8, REG_R9, REG_R10, REG_R11,

    REG_IVTP, REG_TVTP

  }

c4x_reg_t;

/* Note that the actual register numbers for IVTP is 0 and TVTP is 1.  */

#define REG_IE REG_DIE          /* C3x only */

#define REG_IF REG_IIE          /* C3x only */

#define REG_IOF REG_IIF         /* C3x only */

#define C3X_REG_MAX REG_RC

#define C4X_REG_MAX REG_TVTP

/* Register table size including C4x expansion regs.  */

#define REG_TABLE_SIZE (C4X_REG_MAX + 1)

struct c4x_register

{

  char *        name;

  unsigned long regno;

};

typedef struct c4x_register c4x_register_t;

/* We could store register synonyms here.  */

static const c4x_register_t c3x_registers[] =

{

  {"f0",  REG_R0},

  {"r0",  REG_R0},

  {"f1",  REG_R1},

  {"r1",  REG_R1},

  {"f2",  REG_R2},

  {"r2",  REG_R2},

  {"f3",  REG_R3},

  {"r3",  REG_R3},

  {"f4",  REG_R4},

  {"r4",  REG_R4},

  {"f5",  REG_R5},

  {"r5",  REG_R5},

  {"f6",  REG_R6},

  {"r6",  REG_R6},

  {"f7",  REG_R7},

  {"r7",  REG_R7},

  {"ar0", REG_AR0},

  {"ar1", REG_AR1},

  {"ar2", REG_AR2},

  {"ar3", REG_AR3},

  {"ar4", REG_AR4},

  {"ar5", REG_AR5},

  {"ar6", REG_AR6},

  {"ar7", REG_AR7},

  {"dp",  REG_DP},

  {"ir0", REG_IR0},

  {"ir1", REG_IR1},

  {"bk",  REG_BK},

  {"sp",  REG_SP},

  {"st",  REG_ST},

  {"ie",  REG_IE},

  {"if",  REG_IF},

  {"iof", REG_IOF},

  {"rs",  REG_RS},

  {"re",  REG_RE},

  {"rc",  REG_RC},

  {"", 0}

};

const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1);

/* Define C4x registers in addition to C3x registers.  */

static const c4x_register_t c4x_registers[] =

{

  {"die", REG_DIE},             /* Clobbers C3x REG_IE */

  {"iie", REG_IIE},             /* Clobbers C3x REG_IF */

  {"iif", REG_IIF},             /* Clobbers C3x REG_IOF */

  {"f8",  REG_R8},

  {"r8",  REG_R8},

  {"f9",  REG_R9},

  {"r9",  REG_R9},

  {"f10", REG_R10},

  {"r10", REG_R10},

  {"f11", REG_R11},

  {"r11", REG_R11},

  {"ivtp", REG_IVTP},

  {"tvtp", REG_TVTP},

  {"", 0}

};

const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);

/* Instruction template.  */

struct c4x_inst

{

  char *        name;

  unsigned long opcode;

  unsigned long opmask;

  char *        args;

};

typedef struct c4x_inst c4x_inst_t;

/* B  condition             16--20

   C  condition             23--27

   ,  required arg follows

   ;  optional arg follows

   General addressing modes

   *  indirect               0--15

   #  direct (for ldp only)  0--15

   @  direct                 0--15

   F  short float immediate  0--15

   Q  register               0--15

   R  register              16--20

   S  short int immediate    0--15

   D  src and dst same reg

   Three operand addressing modes

   E  register               0--7

   G  register               8--15

   I  indirect(short)        0--7

   J  indirect(short)        8--15

   R  register              16--20

   W  short int (C4x)        0--7

   C  indirect(short) (C4x)  0--7

   O  indirect(short) (C4x)  8--15

   Parallel instruction addressing modes

   E  register               0--7

   G  register               8--15

   I  indirect(short)        0--7

   J  indirect(short)        8--15

   K  register              19--21

   L  register              22--24

   M  register (R2,R3)      22--22

   N  register (R0,R1)      23--23

   Misc. addressing modes

   A  address register      22--24

   B  unsigned integer       0--23  (absolute on C3x, relative on C4x)

   P  displacement (PC Rel)  0--15

   U  unsigned integer       0--15

   V  vector                 0--4   (C4x 0--8)

   T  integer (C4x stik)    16--20

   Y  address reg (C4x)     16--20

   X  expansion reg (C4x)    0--4

   Z  expansion reg (C4x)   16--20.  */

#define C4X_OPERANDS_MAX 7      /* Max number of operands for an inst.  */

#define C4X_NAME_MAX 16         /* Max number of chars in parallel name.  */

/* General (two) operand group.  */

#define G_F_r "F,R"

#define G_I_r "S,R"

#define G_L_r "U,R"

#define G_Q_r "*,R"

#define G_T_r "@,R"

#define G_r_r "Q;R"

/* Three operand group (Type 1 with missing third operand).  */

#define T_rr_ "E,G"

#define T_rS_ "E,J"

#define T_Sr_ "I,G"

#define T_SS_ "I,J"

/* Three operand group (Type 2 with missing third operand).  */

#define T_Jr_ "W,G"             /* C4x only */

#define T_rJ_ "G,W"             /* C4x only (commutative insns only) */

#define T_Rr_ "C,G"             /* C4x only */

#define T_rR_ "G,C"             /* C4x only (commutative insns only) */

#define T_JR_ "W,O"             /* C4x only */

#define T_RJ_ "O,W"             /* C4x only (commutative insns only) */

#define T_RR_ "C,O"             /* C4x only */

/* Three operand group (Type 1).  */

#define T_rrr "E,G;R"

#define T_Srr "E,J,R"

#define T_rSr "I,G;R"

#define T_SSr "I,J,R"

/* Three operand group (Type 2).  */

#define T_Jrr "W,G;R"           /* C4x only */

#define T_rJr "G,W,R"           /* C4x only (commutative insns only) */

#define T_Rrr "C,G;R"           /* C4x only */

#define T_rRr "G,C,R"           /* C4x only (commutative insns only) */

#define T_JRr "W,O,R"           /* C4x only */

#define T_RJr "O,W,R"           /* C4x only (commutative insns only) */

#define T_RRr "C,O,R"           /* C4x only */

/* Parallel group (store || op).  */

#define Q_rS_rSr "H,J|K,I,L"

#define Q_rS_Sr  "H,J|I,L"

#define Q_rS_Srr "H,J|I,K;L"

/* Parallel group (op || store).  */

#define P_rSr_rS "K,I,L|H,J"

#define P_Srr_rS "I,K;L|H,J"

#define P_rS_rS  "L,I|H,J"

/* Parallel group (load || load).  */

#define P_Sr_Sr "I,L|J,K"

#define Q_Sr_Sr "J,K|I,L"

/* Parallel group (store || store).  */

#define P_Sr_rS "I,L|H,J"

#define Q_rS_rS "H,J|L,I"

/* Parallel group (multiply || add/sub).  */

#define P_SSr_rrr "I,J,N|H,K;M" /* 00 (User manual transposes I,J) */

#define P_Srr_rSr "J,K;N|H,I,M" /* 01 */

#define P_rSr_rSr "K,J,N|H,I,M" /* 01 */

#define P_rrr_SSr "H,K;N|I,J,M" /* 10 (User manual transposes H,K) */

#define P_Srr_Srr "J,K;N|I,H;M" /* 11 */

#define P_rSr_Srr "K,J,N|I,H;M" /* 11 */

#define Q_rrr_SSr "H,K;M|I,J,N" /* 00 (User manual transposes I,J) */

#define Q_rSr_Srr "H,I,M|J,K;N" /* 01 */

#define Q_rSr_rSr "H,I,M|K,J,N" /* 01 */

#define Q_SSr_rrr "I,J,M|H,K;N" /* 10 (User manual transposes H,K) */

#define Q_Srr_Srr "I,H;M|J,K;N" /* 11 */

#define Q_Srr_rSr "I,H;M|K,J,N" /* 11 */

/* Define c3x opcodes for assembler and disassembler.  */

static const c4x_inst_t c3x_insts[] =

{

  /* Put synonyms after the desired forms in table so that they get

     overwritten in the lookup table.  The disassembler will thus

     print the `proper' mnemonics.  Note that the disassembler

     only decodes the 11 MSBs, so instructions like ldp @0x500 will

     be printed as ldiu 5, dp.  Note that with parallel instructions,

     the second part is executed before the first part, unless

     the sti1||sti2 form is used.  We also allow sti2||sti1

     which is equivalent to the default sti||sti form.

     Put most common forms first to speed up assembler.

     FIXME:  Add all the other parallel/load forms, like absf1_stf2

     Perhaps I should have used a few macros...especially with

     all the bloat after adding the C4x opcodes...too late now!  */

    /* Parallel instructions.  */

  { "absf_stf",     0xc8000000, 0xfe000000, P_Sr_rS },

  { "absi_sti",     0xca000000, 0xfe000000, P_Sr_rS },

  { "addf_mpyf",    0x80000000, 0xff000000, Q_rrr_SSr },

  { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_Srr },

  { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_rSr },

  { "addf_mpyf",    0x82000000, 0xff000000, Q_SSr_rrr },

  { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_Srr },

  { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_rSr },

  { "addf3_mpyf3",  0x80000000, 0xff000000, Q_rrr_SSr },

  { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_Srr },

  { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_rSr },

  { "addf3_mpyf3",  0x82000000, 0xff000000, Q_SSr_rrr },

  { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_Srr },

  { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_rSr },

  { "addf_stf",     0xcc000000, 0xfe000000, P_Srr_rS },

  { "addf_stf",     0xcc000000, 0xfe000000, P_rSr_rS },

  { "addf3_stf",    0xcc000000, 0xfe000000, P_Srr_rS },

  { "addf3_stf",    0xcc000000, 0xfe000000, P_rSr_rS },

  { "addi_mpyi",    0x88000000, 0xff000000, Q_rrr_SSr },

  { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_Srr },

  { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_rSr },

  { "addi_mpyi",    0x8a000000, 0xff000000, Q_SSr_rrr },

  { "addi_mpyi",    0x8b000000, 0xff000000, Q_Srr_Srr },

  { "addi3_mpyi3",  0x88000000, 0xff000000, Q_rrr_SSr },

  { "addi3_mpyi3",  0x89000000, 0xff000000, Q_rSr_Srr },

  { "addi3_mpyi3",  0x8a000000, 0xff000000, Q_SSr_rrr },

  { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_Srr },

  { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_rSr },

  { "addi_sti",     0xce000000, 0xfe000000, P_Srr_rS },

  { "addi_sti",     0xce000000, 0xfe000000, P_rSr_rS },

  { "addi3_sti",    0xce000000, 0xfe000000, P_Srr_rS },

  { "addi3_sti",    0xce000000, 0xfe000000, P_rSr_rS },

  { "and_sti",      0xd0000000, 0xfe000000, P_Srr_rS },

  { "and_sti",      0xd0000000, 0xfe000000, P_rSr_rS },

  { "and3_sti",     0xd0000000, 0xfe000000, P_Srr_rS },

  { "and3_sti",     0xd0000000, 0xfe000000, P_rSr_rS },

  { "ash_sti",      0xd2000000, 0xfe000000, P_rSr_rS },

  { "ash3_sti",     0xd2000000, 0xfe000000, P_rSr_rS },

  { "fix_sti",      0xd4000000, 0xfe000000, P_Sr_rS },

  { "float_stf",    0xd6000000, 0xfe000000, P_Sr_rS },

  { "ldf_ldf",      0xc4000000, 0xfe000000, P_Sr_Sr },

  { "ldf1_ldf2",    0xc4000000, 0xfe000000, Q_Sr_Sr }, /* synonym */

  { "ldf2_ldf1",    0xc4000000, 0xfe000000, P_Sr_Sr }, /* synonym */

  { "ldf_stf",      0xd8000000, 0xfe000000, P_Sr_rS },

  { "ldi_ldi",      0xc6000000, 0xfe000000, P_Sr_Sr },

  { "ldi1_ldi2",    0xc6000000, 0xfe000000, Q_Sr_Sr }, /* synonym  */

  { "ldi2_ldi1",    0xc6000000, 0xfe000000, P_Sr_Sr }, /* synonym  */

  { "ldi_sti",      0xda000000, 0xfe000000, P_Sr_rS },

  { "lsh_sti",      0xdc000000, 0xfe000000, P_rSr_rS },

  { "lsh3_sti",     0xdc000000, 0xfe000000, P_rSr_rS },

  { "mpyf_addf",    0x80000000, 0xff000000, P_SSr_rrr },

  { "mpyf_addf",    0x81000000, 0xff000000, P_Srr_rSr },

  { "mpyf_addf",    0x81000000, 0xff000000, P_rSr_rSr },

  { "mpyf_addf",    0x82000000, 0xff000000, P_rrr_SSr },

  { "mpyf_addf",    0x83000000, 0xff000000, P_Srr_Srr },

  { "mpyf_addf",    0x83000000, 0xff000000, P_rSr_Srr },

  { "mpyf3_addf3",  0x80000000, 0xff000000, P_SSr_rrr },

  { "mpyf3_addf3",  0x81000000, 0xff000000, P_Srr_rSr },

  { "mpyf3_addf3",  0x81000000, 0xff000000, P_rSr_rSr },

  { "mpyf3_addf3",  0x82000000, 0xff000000, P_rrr_SSr },

  { "mpyf3_addf3",  0x83000000, 0xff000000, P_Srr_Srr },

  { "mpyf3_addf3",  0x83000000, 0xff000000, P_rSr_Srr },

  { "mpyf_stf",     0xde000000, 0xfe000000, P_Srr_rS },

  { "mpyf_stf",     0xde000000, 0xfe000000, P_rSr_rS },

  { "mpyf3_stf",    0xde000000, 0xfe000000, P_Srr_rS },

  { "mpyf3_stf",    0xde000000, 0xfe000000, P_rSr_rS },

  { "mpyf_subf",    0x84000000, 0xff000000, P_SSr_rrr },

  { "mpyf_subf",    0x85000000, 0xff000000, P_Srr_rSr },

  { "mpyf_subf",    0x85000000, 0xff000000, P_rSr_rSr },

  { "mpyf_subf",    0x86000000, 0xff000000, P_rrr_SSr },

  { "mpyf_subf",    0x87000000, 0xff000000, P_Srr_Srr },

  { "mpyf_subf",    0x87000000, 0xff000000, P_rSr_Srr },

  { "mpyf3_subf3",  0x84000000, 0xff000000, P_SSr_rrr },

  { "mpyf3_subf3",  0x85000000, 0xff000000, P_Srr_rSr },

  { "mpyf3_subf3",  0x85000000, 0xff000000, P_rSr_rSr },

  { "mpyf3_subf3",  0x86000000, 0xff000000, P_rrr_SSr },

  { "mpyf3_subf3",  0x87000000, 0xff000000, P_Srr_Srr },

  { "mpyf3_subf3",  0x87000000, 0xff000000, P_rSr_Srr },

  { "mpyi_addi",    0x88000000, 0xff000000, P_SSr_rrr },

  { "mpyi_addi",    0x89000000, 0xff000000, P_Srr_rSr },

  { "mpyi_addi",    0x89000000, 0xff000000, P_rSr_rSr },

  { "mpyi_addi",    0x8a000000, 0xff000000, P_rrr_SSr },

  { "mpyi_addi",    0x8b000000, 0xff000000, P_Srr_Srr },

  { "mpyi_addi",    0x8b000000, 0xff000000, P_rSr_Srr },

  { "mpyi3_addi3",  0x88000000, 0xff000000, P_SSr_rrr },

  { "mpyi3_addi3",  0x89000000, 0xff000000, P_Srr_rSr },

  { "mpyi3_addi3",  0x89000000, 0xff000000, P_rSr_rSr },

  { "mpyi3_addi3",  0x8a000000, 0xff000000, P_rrr_SSr },

  { "mpyi3_addi3",  0x8b000000, 0xff000000, P_Srr_Srr },

  { "mpyi3_addi3",  0x8b000000, 0xff000000, P_rSr_Srr },

  { "mpyi_sti",     0xe0000000, 0xfe000000, P_Srr_rS },

  { "mpyi_sti",     0xe0000000, 0xfe000000, P_rSr_rS },

  { "mpyi3_sti",    0xe0000000, 0xfe000000, P_Srr_rS },

  { "mpyi3_sti",    0xe0000000, 0xfe000000, P_rSr_rS },

  { "mpyi_subi",    0x8c000000, 0xff000000, P_SSr_rrr },

  { "mpyi_subi",    0x8d000000, 0xff000000, P_Srr_rSr },

  { "mpyi_subi",    0x8d000000, 0xff000000, P_rSr_rSr },

  { "mpyi_subi",    0x8e000000, 0xff000000, P_rrr_SSr },

  { "mpyi_subi",    0x8f000000, 0xff000000, P_Srr_Srr },

  { "mpyi_subi",    0x8f000000, 0xff000000, P_rSr_Srr },

  { "mpyi3_subi3",  0x8c000000, 0xff000000, P_SSr_rrr },

  { "mpyi3_subi3",  0x8d000000, 0xff000000, P_Srr_rSr },

  { "mpyi3_subi3",  0x8d000000, 0xff000000, P_rSr_rSr },

  { "mpyi3_subi3",  0x8e000000, 0xff000000, P_rrr_SSr },

  { "mpyi3_subi3",  0x8f000000, 0xff000000, P_Srr_Srr },

  { "mpyi3_subi3",  0x8f000000, 0xff000000, P_rSr_Srr },

  { "negf_stf",     0xe2000000, 0xfe000000, P_Sr_rS },

  { "negi_sti",     0xe4000000, 0xfe000000, P_Sr_rS },

  { "not_sti",      0xe6000000, 0xfe000000, P_Sr_rS },

  { "or3_sti",      0xe8000000, 0xfe000000, P_Srr_rS },

  { "or3_sti",      0xe8000000, 0xfe000000, P_rSr_rS },

  { "stf_absf",     0xc8000000, 0xfe000000, Q_rS_Sr },

  { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_Srr },

  { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_rSr },

  { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_Srr },

  { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_rSr },

  { "stf_float",    0xd6000000, 0xfe000000, Q_rS_Sr },

  { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_Srr },

  { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_rSr },

  { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_Srr },

  { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_rSr },

  { "stf_negf",     0xe2000000, 0xfe000000, Q_rS_Sr },

  { "stf_stf",      0xc0000000, 0xfe000000, P_rS_rS },

  { "stf1_stf2",    0xc0000000, 0xfe000000, Q_rS_rS }, /* synonym */

  { "stf2_stf1",    0xc0000000, 0xfe000000, P_rS_rS }, /* synonym */

  { "stf_subf",     0xea000000, 0xfe000000, Q_rS_rSr },

  { "stf_subf3",    0xea000000, 0xfe000000, Q_rS_rSr },

  { "sti_absi",     0xca000000, 0xfe000000, Q_rS_Sr },

  { "sti_addi",     0xce000000, 0xfe000000, Q_rS_Srr },

  { "sti_addi",     0xce000000, 0xfe000000, Q_rS_rSr },

  { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_Srr },

  { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_rSr },

  { "sti_and",      0xd0000000, 0xfe000000, Q_rS_Srr },

  { "sti_and",      0xd0000000, 0xfe000000, Q_rS_rSr },

  { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_Srr },

  { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_rSr },

  { "sti_ash3",     0xd2000000, 0xfe000000, Q_rS_rSr },

  { "sti_fix",      0xd4000000, 0xfe000000, Q_rS_Sr },

  { "sti_ldi",      0xda000000, 0xfe000000, Q_rS_Sr },

  { "sti_lsh",      0xdc000000, 0xfe000000, Q_rS_rSr },

  { "sti_lsh3",     0xdc000000, 0xfe000000, Q_rS_rSr },

  { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_Srr },

  { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_rSr },

  { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_Srr },

  { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_rSr },

  { "sti_negi",     0xe4000000, 0xfe000000, Q_rS_Sr },

  { "sti_not",      0xe6000000, 0xfe000000, Q_rS_Sr },

  { "sti_or",       0xe8000000, 0xfe000000, Q_rS_Srr },

  { "sti_or",       0xe8000000, 0xfe000000, Q_rS_rSr },

  { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_Srr },

  { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_rSr },

  { "sti_sti",      0xc2000000, 0xfe000000, P_rS_rS },

  { "sti1_sti2",    0xc2000000, 0xfe000000, Q_rS_rS }, /* synonym */

  { "sti2_sti1",    0xc2000000, 0xfe000000, P_rS_rS }, /* synonym */

  { "sti_subi",     0xec000000, 0xfe000000, Q_rS_rSr },

  { "sti_subi3",    0xec000000, 0xfe000000, Q_rS_rSr },

  { "sti_xor",      0xee000000, 0xfe000000, Q_rS_Srr },

  { "sti_xor",      0xee000000, 0xfe000000, Q_rS_rSr },

  { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_Srr },

  { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_rSr },

  { "subf_mpyf",    0x84000000, 0xff000000, Q_rrr_SSr },

  { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_Srr },

  { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_rSr },

  { "subf_mpyf",    0x86000000, 0xff000000, Q_SSr_rrr },

  { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_Srr },

  { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_rSr },

  { "subf3_mpyf3",  0x84000000, 0xff000000, Q_rrr_SSr },

  { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_Srr },

  { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_rSr },

  { "subf3_mpyf3",  0x86000000, 0xff000000, Q_SSr_rrr },

  { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_Srr },

  { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_rSr },

  { "subf_stf",     0xea000000, 0xfe000000, P_rSr_rS },

  { "subf3_stf",    0xea000000, 0xfe000000, P_rSr_rS },

  { "subi_mpyi",    0x8c000000, 0xff000000, Q_rrr_SSr },

  { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_Srr },

  { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_rSr },

  { "subi_mpyi",    0x8e000000, 0xff000000, Q_SSr_rrr },

  { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_Srr },

  { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_rSr },

  { "subi3_mpyi3",  0x8c000000, 0xff000000, Q_rrr_SSr },

  { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_Srr },

  { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_rSr },

  { "subi3_mpyi3",  0x8e000000, 0xff000000, Q_SSr_rrr },

  { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_Srr },

  { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_rSr },

  { "subi_sti",     0xec000000, 0xfe000000, P_rSr_rS },

  { "subi3_sti",    0xec000000, 0xfe000000, P_rSr_rS },

  { "xor_sti",      0xee000000, 0xfe000000, P_Srr_rS },

  { "xor_sti",      0xee000000, 0xfe000000, P_rSr_rS },

  { "xor3_sti",     0xee000000, 0xfe000000, P_Srr_rS },

  { "xor3_sti",     0xee000000, 0xfe000000, P_rSr_rS },

  { "absf",   0x00000000, 0xffe00000, G_r_r },

  { "absf",   0x00200000, 0xffe00000, G_T_r },

  { "absf",   0x00400000, 0xffe00000, G_Q_r },

  { "absf",   0x00600000, 0xffe00000, G_F_r },

  { "absi",   0x00800000, 0xffe00000, G_r_r },

  { "absi",   0x00a00000, 0xffe00000, G_T_r },

  { "absi",   0x00c00000, 0xffe00000, G_Q_r },

  { "absi",   0x00e00000, 0xffe00000, G_I_r },

  { "addc",   0x01000000, 0xffe00000, G_r_r },

  { "addc",   0x01200000, 0xffe00000, G_T_r },

  { "addc",   0x01400000, 0xffe00000, G_Q_r },

  { "addc",   0x01600000, 0xffe00000, G_I_r },

  { "addc",   0x20000000, 0xffe00000, T_rrr },

  { "addc",   0x20200000, 0xffe00000, T_Srr },

  { "addc",   0x20400000, 0xffe00000, T_rSr },

  { "addc",   0x20600000, 0xffe00000, T_SSr },

  { "addc",   0x30000000, 0xffe00000, T_Jrr }, /* C4x */

  { "addc",   0x30000000, 0xffe00000, T_rJr }, /* C4x */

  { "addc",   0x30200000, 0xffe00000, T_rRr }, /* C4x */

  { "addc",   0x30200000, 0xffe00000, T_Rrr }, /* C4x */

  { "addc",   0x30400000, 0xffe00000, T_JRr }, /* C4x */

  { "addc",   0x30400000, 0xffe00000, T_RJr }, /* C4x */

  { "addc",   0x30600000, 0xffe00000, T_RRr }, /* C4x */

  { "addc3",  0x20000000, 0xffe00000, T_rrr },

  { "addc3",  0x20200000, 0xffe00000, T_Srr },

  { "addc3",  0x20400000, 0xffe00000, T_rSr },

  { "addc3",  0x20600000, 0xffe00000, T_SSr },

  { "addc3",  0x30000000, 0xffe00000, T_Jrr }, /* C4x */

  { "addc3",  0x30000000, 0xffe00000, T_rJr }, /* C4x */

  { "addc3",  0x30200000, 0xffe00000, T_rRr }, /* C4x */

  { "addc3",  0x30200000, 0xffe00000, T_Rrr }, /* C4x */

  { "addc3",  0x30400000, 0xffe00000, T_JRr }, /* C4x */

  { "addc3",  0x30400000, 0xffe00000, T_RJr }, /* C4x */

  { "addc3",  0x30600000, 0xffe00000, T_RRr }, /* C4x */

  { "addf",   0x01800000, 0xffe00000, G_r_r },

  { "addf",   0x01a00000, 0xffe00000, G_T_r },

  { "addf",   0x01c00000, 0xffe00000, G_Q_r },

  { "addf",   0x01e00000, 0xffe00000, G_F_r },

  { "addf",   0x20800000, 0xffe00000, T_rrr },

  { "addf",   0x20a00000, 0xffe00000, T_Srr },

  { "addf",   0x20c00000, 0xffe00000, T_rSr },

  { "addf",   0x20e00000, 0xffe00000, T_SSr },

  { "addf",   0x30800000, 0xffe00000, T_Jrr }, /* C4x */

  { "addf",   0x30800000, 0xffe00000, T_rJr }, /* C4x */

  { "addf",   0x30a00000, 0xffe00000, T_rRr }, /* C4x */

  { "addf",   0x30a00000, 0xffe00000, T_Rrr }, /* C4x */

  { "addf",   0x30c00000, 0xffe00000, T_JRr }, /* C4x */

  { "addf",   0x30c00000, 0xffe00000, T_RJr }, /* C4x */

  { "addf",   0x30e00000, 0xffe00000, T_RRr }, /* C4x */

  { "addf3",  0x20800000, 0xffe00000, T_rrr },

  { "addf3",  0x20a00000, 0xffe00000, T_Srr },

  { "addf3",  0x20c00000, 0xffe00000, T_rSr },

  { "addf3",  0x20e00000, 0xffe00000, T_SSr },

  { "addf3",  0x30800000, 0xffe00000, T_Jrr }, /* C4x */

  { "addf3",  0x30800000, 0xffe00000, T_rJr }, /* C4x */

  { "addf3",  0x30a00000, 0xffe00000, T_rRr }, /* C4x */

  { "addf3",  0x30a00000, 0xffe00000, T_Rrr }, /* C4x */

  { "addf3",  0x30c00000, 0xffe00000, T_JRr }, /* C4x */

  { "addf3",  0x30c00000, 0xffe00000, T_RJr }, /* C4x */

  { "addf3",  0x30e00000, 0xffe00000, T_RRr }, /* C4x */

  { "addi",   0x02000000, 0xffe00000, G_r_r },

  { "addi",   0x02200000, 0xffe00000, G_T_r },

  { "addi",   0x02400000, 0xffe00000, G_Q_r },