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[/] [or1k/] [trunk/] [gdb-5.3/] [opcodes/] [d30v-opc.c] - Blame information for rev 1773

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1 1181 sfurman 
/* d30v-opc.c -- D30V opcode list
2 
   Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 
   Written by Martin Hunt, Cygnus Support
4 
 
5 
This file is part of GDB, GAS, and the GNU binutils.
6 
 
7 
GDB, GAS, and the GNU binutils are free software; you can redistribute
8 
them and/or modify them under the terms of the GNU General Public
9 
License as published by the Free Software Foundation; either version
10 
2, or (at your option) any later version.
11 
 
12 
GDB, GAS, and the GNU binutils are distributed in the hope that they
13 
will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15 
the GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this file; see the file COPYING.  If not, write to the Free
19 
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
20 
 
21 
#include <stdio.h>
22 
#include "sysdep.h"
23 
#include "opcode/d30v.h"
24 
 
25 
/* This table is sorted. */
26 
/* If you add anything, it MUST be in alphabetical order */
27 
/* The first field is the name the assembler uses when looking */
28 
/* up orcodes.  The second field is the name the disassembler will use. */
29 
/* This allows the assembler to assemble references to r63 (for example) */
30 
/* or "sp".  The disassembler will always use the preferred form (sp) */
31 
const struct pd_reg pre_defined_registers[] =
32 
{
33 
  { "a0", NULL, OPERAND_ACC+0 },
34 
  { "a1", NULL, OPERAND_ACC+1 },
35 
  { "bpc", NULL, OPERAND_CONTROL+3 },
36 
  { "bpsw", NULL, OPERAND_CONTROL+1 },
37 
  { "c", "c", OPERAND_FLAG+7 },
38 
  { "cr0", "psw", OPERAND_CONTROL },
39 
  { "cr1", "bpsw", OPERAND_CONTROL+1 },
40 
  { "cr10", "mod_s", OPERAND_CONTROL+10 },
41 
  { "cr11", "mod_e", OPERAND_CONTROL+11 },
42 
  { "cr12", NULL, OPERAND_CONTROL+12 },
43 
  { "cr13", NULL, OPERAND_CONTROL+13 },
44 
  { "cr14", "iba", OPERAND_CONTROL+14 },
45 
  { "cr15", "eit_vb", OPERAND_CONTROL+15 },
46 
  { "cr16", "int_s", OPERAND_CONTROL+16 },
47 
  { "cr17", "int_m", OPERAND_CONTROL+17 },
48 
  { "cr18", NULL, OPERAND_CONTROL+18 },
49 
  { "cr19", NULL, OPERAND_CONTROL+19 },
50 
  { "cr2", "pc", OPERAND_CONTROL+2 },
51 
  { "cr20", NULL, OPERAND_CONTROL+20 },
52 
  { "cr21", NULL, OPERAND_CONTROL+21 },
53 
  { "cr22", NULL, OPERAND_CONTROL+22 },
54 
  { "cr23", NULL, OPERAND_CONTROL+23 },
55 
  { "cr24", NULL, OPERAND_CONTROL+24 },
56 
  { "cr25", NULL, OPERAND_CONTROL+25 },
57 
  { "cr26", NULL, OPERAND_CONTROL+26 },
58 
  { "cr27", NULL, OPERAND_CONTROL+27 },
59 
  { "cr28", NULL, OPERAND_CONTROL+28 },
60 
  { "cr29", NULL, OPERAND_CONTROL+29 },
61 
  { "cr3", "bpc", OPERAND_CONTROL+3 },
62 
  { "cr30", NULL, OPERAND_CONTROL+30 },
63 
  { "cr31", NULL, OPERAND_CONTROL+31 },
64 
  { "cr32", NULL, OPERAND_CONTROL+32 },
65 
  { "cr33", NULL, OPERAND_CONTROL+33 },
66 
  { "cr34", NULL, OPERAND_CONTROL+34 },
67 
  { "cr35", NULL, OPERAND_CONTROL+35 },
68 
  { "cr36", NULL, OPERAND_CONTROL+36 },
69 
  { "cr37", NULL, OPERAND_CONTROL+37 },
70 
  { "cr38", NULL, OPERAND_CONTROL+38 },
71 
  { "cr39", NULL, OPERAND_CONTROL+39 },
72 
  { "cr4", "dpsw", OPERAND_CONTROL+4 },
73 
  { "cr40", NULL, OPERAND_CONTROL+40 },
74 
  { "cr41", NULL, OPERAND_CONTROL+41 },
75 
  { "cr42", NULL, OPERAND_CONTROL+42 },
76 
  { "cr43", NULL, OPERAND_CONTROL+43 },
77 
  { "cr44", NULL, OPERAND_CONTROL+44 },
78 
  { "cr45", NULL, OPERAND_CONTROL+45 },
79 
  { "cr46", NULL, OPERAND_CONTROL+46 },
80 
  { "cr47", NULL, OPERAND_CONTROL+47 },
81 
  { "cr48", NULL, OPERAND_CONTROL+48 },
82 
  { "cr49", NULL, OPERAND_CONTROL+49 },
83 
  { "cr5","dpc", OPERAND_CONTROL+5 },
84 
  { "cr50", NULL, OPERAND_CONTROL+50 },
85 
  { "cr51", NULL, OPERAND_CONTROL+51 },
86 
  { "cr52", NULL, OPERAND_CONTROL+52 },
87 
  { "cr53", NULL, OPERAND_CONTROL+53 },
88 
  { "cr54", NULL, OPERAND_CONTROL+54 },
89 
  { "cr55", NULL, OPERAND_CONTROL+55 },
90 
  { "cr56", NULL, OPERAND_CONTROL+56 },
91 
  { "cr57", NULL, OPERAND_CONTROL+57 },
92 
  { "cr58", NULL, OPERAND_CONTROL+58 },
93 
  { "cr59", NULL, OPERAND_CONTROL+59 },
94 
  { "cr6", NULL, OPERAND_CONTROL+6 },
95 
  { "cr60", NULL, OPERAND_CONTROL+60 },
96 
  { "cr61", NULL, OPERAND_CONTROL+61 },
97 
  { "cr62", NULL, OPERAND_CONTROL+62 },
98 
  { "cr63", NULL, OPERAND_CONTROL+63 },
99 
  { "cr7", "rpt_c", OPERAND_CONTROL+7 },
100 
  { "cr8", "rpt_s", OPERAND_CONTROL+8 },
101 
  { "cr9", "rpt_e", OPERAND_CONTROL+9 },
102 
  { "dpc", NULL, OPERAND_CONTROL+5 },
103 
  { "dpsw", NULL, OPERAND_CONTROL+4 },
104 
  { "eit_vb", NULL, OPERAND_CONTROL+15 },
105 
  { "f0", NULL, OPERAND_FLAG+0 },
106 
  { "f1", NULL, OPERAND_FLAG+1 },
107 
  { "f2", NULL, OPERAND_FLAG+2 },
108 
  { "f3", NULL, OPERAND_FLAG+3 },
109 
  { "f4", "s", OPERAND_FLAG+4 },
110 
  { "f5", "v", OPERAND_FLAG+5 },
111 
  { "f6", "va", OPERAND_FLAG+6 },
112 
  { "f7", "c", OPERAND_FLAG+7 },
113 
  { "iba", NULL, OPERAND_CONTROL+14 },
114 
  { "int_m", NULL, OPERAND_CONTROL+17 },
115 
  { "int_s", NULL, OPERAND_CONTROL+16 },
116 
  { "link", "r62", 62 },
117 
  { "mod_e", NULL, OPERAND_CONTROL+11 },
118 
  { "mod_s", NULL, OPERAND_CONTROL+10 },
119 
  { "pc", NULL, OPERAND_CONTROL+2 },
120 
  { "psw", NULL, OPERAND_CONTROL },
121 
  { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
122 
  { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
123 
  { "r0", NULL, 0 },
124 
  { "r1", NULL, 1 },
125 
  { "r10", NULL, 10 },
126 
  { "r11", NULL, 11 },
127 
  { "r12", NULL, 12 },
128 
  { "r13", NULL, 13 },
129 
  { "r14", NULL, 14 },
130 
  { "r15", NULL, 15 },
131 
  { "r16", NULL, 16 },
132 
  { "r17", NULL, 17 },
133 
  { "r18", NULL, 18 },
134 
  { "r19", NULL, 19 },
135 
  { "r2", NULL, 2 },
136 
  { "r20", NULL, 20 },
137 
  { "r21", NULL, 21 },
138 
  { "r22", NULL, 22 },
139 
  { "r23", NULL, 23 },
140 
  { "r24", NULL, 24 },
141 
  { "r25", NULL, 25 },
142 
  { "r26", NULL, 26 },
143 
  { "r27", NULL, 27 },
144 
  { "r28", NULL, 28 },
145 
  { "r29", NULL, 29 },
146 
  { "r3", NULL, 3 },
147 
  { "r30", NULL, 30 },
148 
  { "r31", NULL, 31 },
149 
  { "r32", NULL, 32 },
150 
  { "r33", NULL, 33 },
151 
  { "r34", NULL, 34 },
152 
  { "r35", NULL, 35 },
153 
  { "r36", NULL, 36 },
154 
  { "r37", NULL, 37 },
155 
  { "r38", NULL, 38 },
156 
  { "r39", NULL, 39 },
157 
  { "r4", NULL, 4 },
158 
  { "r40", NULL, 40 },
159 
  { "r41", NULL, 41 },
160 
  { "r42", NULL, 42 },
161 
  { "r43", NULL, 43 },
162 
  { "r44", NULL, 44 },
163 
  { "r45", NULL, 45 },
164 
  { "r46", NULL, 46 },
165 
  { "r47", NULL, 47 },
166 
  { "r48", NULL, 48 },
167 
  { "r49", NULL, 49 },
168 
  { "r5", NULL, 5 },
169 
  { "r50", NULL, 50 },
170 
  { "r51", NULL, 51 },
171 
  { "r52", NULL, 52 },
172 
  { "r53", NULL, 53 },
173 
  { "r54", NULL, 54 },
174 
  { "r55", NULL, 55 },
175 
  { "r56", NULL, 56 },
176 
  { "r57", NULL, 57 },
177 
  { "r58", NULL, 58 },
178 
  { "r59", NULL, 59 },
179 
  { "r6", NULL, 6 },
180 
  { "r60", NULL, 60 },
181 
  { "r61", NULL, 61 },
182 
  { "r62", "link", 62 },
183 
  { "r63", "sp", 63 },
184 
  { "r7", NULL, 7 },
185 
  { "r8", NULL, 8 },
186 
  { "r9", NULL, 9 },
187 
  { "rpt_c", NULL, OPERAND_CONTROL+7 },
188 
  { "rpt_e", NULL, OPERAND_CONTROL+9 },
189 
  { "rpt_s", NULL, OPERAND_CONTROL+8 },
190 
  { "s", NULL, OPERAND_FLAG+4 },
191 
  { "sp", NULL, 63 },
192 
  { "v", NULL, OPERAND_FLAG+5 },
193 
  { "va", NULL, OPERAND_FLAG+6 },
194 
};
195 
 
196 
int
197 
reg_name_cnt()
198 
{
199 
  return (sizeof(pre_defined_registers) / sizeof(struct pd_reg));
200 
}
201 
 
202 
/* OPCODE TABLE */
203 
/* The format of this table is defined in opcode/d30v.h */
204 
const struct d30v_opcode d30v_opcode_table[] = {
205 
  { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
206 
  { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
207 
  { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
208 
  { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
209 
  { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
210 
  { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
211 
  { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
212 
  { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
213 
  { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
214 
  { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
215 
  { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
216 
  { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
217 
  { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
218 
  { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
219 
  { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
220 
  { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
221 
  { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
222 
  { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
223 
  { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
224 
  { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
225 
  { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
226 
  { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
227 
  { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
228 
  { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
229 
  { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
230 
  { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
231 
  { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
232 
  { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
233 
  { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
234 
  { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
235 
  { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
236 
  { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
237 
  { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
238 
  { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
239 
  { "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
240 
  { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
241 
  { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
242 
  { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
243 
  { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
244 
  { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
245 
  { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
246 
  { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
247 
  { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
248 
  { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
249 
  { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
250 
  { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
251 
  { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
252 
  { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
253 
  { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
254 
  { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
255 
  { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
256 
  { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
257 
  { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
258 
  { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
259 
  { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
260 
  { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
261 
  { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
262 
  { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
263 
  { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
264 
  { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
265 
  { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
266 
  { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
267 
  { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
268 
  { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
269 
  { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
270 
  { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
271 
  { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
272 
  { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
273 
  { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
274 
  { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
275 
  { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
276 
  { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
277 
  { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
278 
  { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
279 
  { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
280 
  { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
281 
  { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 },
282 
  { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
283 
  { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
284 
  { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
285 
  { "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 },
286 
  { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
287 
  { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
288 
  { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
289 
  { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
290 
  { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
291 
  { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
292 
  { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
293 
  { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
294 
  { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
295 
  { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
296 
  { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
297 
  { "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
298 
  { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
299 
  { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
300 
  { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
301 
  { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
302 
  { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
303 
  { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
304 
  { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
305 
  { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
306 
  { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
307 
  { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
308 
  { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },
309 
  { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
310 
  { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
311 
  { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
312 
  { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
313 
  { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
314 
  { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
315 
  { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
316 
  { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
317 
  { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
318 
  { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
319 
  { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
320 
  { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
321 
  { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
322 
  { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
323 
  { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
324 
  { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
325 
  { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
326 
  { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
327 
  { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
328 
  { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
329 
  { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
330 
  { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
331 
  { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 },
332 
  { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
333 
  { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
334 
  { NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
335 
};
336 
 
337 
 
338 
/* now define the operand types */
339 
/* format is length, bits, position, flags */
340 
const struct d30v_operand d30v_operand_table[] =
341 
{
342 
#define UNUSED  (0)
343 
  { 0, 0, 0, 0 },
344 
#define Ra      (UNUSED + 1)
345 
  { 6, 6, 0, OPERAND_REG|OPERAND_DEST },
346 
#define Ra2     (Ra + 1)
347 
  { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG },
348 
#define Ra3     (Ra2 + 1)
349 
  { 6, 6, 0, OPERAND_REG },
350 
#define Rb      (Ra3 + 1)
351 
  { 6, 6, 6, OPERAND_REG },
352 
#define Rb2     (Rb + 1)
353 
  { 6, 6, 6, OPERAND_REG|OPERAND_DEST },
354 
#define Rc      (Rb2 + 1)
355 
  { 6, 6, 12, OPERAND_REG },
356 
#define Aa      (Rc + 1)
357 
  { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
358 
#define Ab      (Aa + 1)
359 
  { 6, 1, 6, OPERAND_ACC|OPERAND_REG },
360 
#define IMM5    (Ab + 1)
361 
  { 6, 5, 12, OPERAND_NUM },
362 
#define IMM5U (IMM5 + 1)
363 
  { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
364 
#define IMM5S3        (IMM5U + 1)
365 
  { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
366 
#define IMM6  (IMM5S3 + 1)
367 
  { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
368 
#define IMM6U (IMM6 + 1)
369 
  { 6, 6, 0, OPERAND_NUM },
370 
#define IMM6U2        (IMM6U + 1)
371 
  { 6, 6, 12, OPERAND_NUM },
372 
#define REL6S3        (IMM6U2 + 1)
373 
  { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL },
374 
#define REL12S3       (REL6S3 + 1)
375 
  { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
376 
#define IMM12S3       (REL12S3 + 1)
377 
  { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
378 
#define REL18S3       (IMM12S3 + 1)
379 
  { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
380 
#define IMM18S3       (REL18S3 + 1)
381 
  { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
382 
#define REL32 (IMM18S3 + 1)
383 
  { 32, 32, 0, OPERAND_NUM|OPERAND_PCREL },
384 
#define IMM32 (REL32 + 1)
385 
  { 32, 32, 0, OPERAND_NUM },
386 
#define Fa      (IMM32 + 1)
387 
  { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
388 
#define Fb      (Fa + 1)
389 
  { 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
390 
#define Fc      (Fb + 1)
391 
  { 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
392 
#define ATSIGN  (Fc + 1)
393 
  { 0, 0, 0, OPERAND_ATSIGN},
394 
#define ATPAR   (ATSIGN + 1)    /* "@(" */
395 
  { 0, 0, 0, OPERAND_ATPAR},
396 
#define PLUS    (ATPAR + 1)     /* postincrement */
397 
  { 0, 0, 0, OPERAND_PLUS},
398 
#define MINUS   (PLUS + 1)      /* postdecrement */
399 
  { 0, 0, 0, OPERAND_MINUS},
400 
#define ATMINUS (MINUS + 1)     /* predecrement */
401 
  { 0, 0, 0, OPERAND_ATMINUS},
402 
#define Ca      (ATMINUS + 1)   /* control register */
403 
  { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
404 
#define Cb      (Ca + 1)        /* control register */
405 
  { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL},
406 
#define CC      (Cb + 1)        /* condition code (CMPcc and CMPUcc) */
407 
  { 3, 3, -3, OPERAND_NAME},
408 
#define Fa2     (CC + 1)        /* flag register (CMPcc and CMPUcc) */
409 
  { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST},
410 
#define Fake    (Fa2 + 1)       /* place holder for "id" field in mvfsys and mvtsys */
411 
  { 6, 2, 12, OPERAND_SPECIAL},
412 
};
413 
 
414 
/* now we need to define the instruction formats */
415 
const struct d30v_format d30v_format_table[] =
416 
{
417 
  { 0, 0, { 0 } },
418 
  { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
419 
  { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } },  /* Ra,@(Rb+,Rc) */
420 
  { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } },      /* Ra,@(Rb,imm6) */
421 
  { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
422 
  { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } },       /* Ra,@(Rb,Rc) */
423 
  { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
424 
  { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } },    /* Ra,@(Rb,imm6) */
425 
  { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
426 
  { SHORT_A, 0, { Ra, Rb, Rc } },                /* Ra,Rb,Rc */
427 
  { SHORT_A, 2, { Ra, Rb, IMM6 } },             /* Ra,Rb,imm6 */
428 
  { SHORT_B1, 0, { Rc } },                       /* Rc */
429 
  { SHORT_B2, 2, { IMM18S3 } },                 /* imm18 */
430 
  { SHORT_B2r, 2, { REL18S3 } },                /* rel18 */
431 
  { SHORT_B3, 0, { Ra3, Rc } },                  /* Ra,Rc */
432 
  { SHORT_B3, 2, { Ra3, IMM12S3 } },            /* Ra,imm12 */
433 
  { SHORT_B3r, 0, { Ra3, Rc } },         /* Ra,Rc */
434 
  { SHORT_B3r, 2, { Ra3, REL12S3 } },           /* Ra,rel12 */
435 
  { SHORT_B3b, 1, { Ra3, Rc } },                /* Ra,Rc */
436 
  { SHORT_B3b, 3, { Ra3, IMM12S3 } },           /* Ra,imm12 */
437 
  { SHORT_B3br, 1, { Ra3, Rc } },               /* Ra,Rc */
438 
  { SHORT_B3br, 3, { Ra3, REL12S3 } },          /* Ra,rel12 */
439 
  { SHORT_D1r, 0, { Ra, Rc } },                  /* Ra,Rc */
440 
  { SHORT_D1r, 2, { Ra, REL12S3 } },            /* Ra,rel12s3 */
441 
  { SHORT_D2, 0, { REL6S3, Rc } },               /* rel6s3,Rc */
442 
  { SHORT_D2, 2, { REL6S3, IMM12S3 } },         /* rel6s3,imm12s3 */
443 
  { SHORT_D2r, 0, { REL6S3, Rc } },              /* rel6s3,Rc */
444 
  { SHORT_D2r, 2, { REL6S3, REL12S3 } },        /* rel6s3,rel12s3 */
445 
  { SHORT_D2Br, 0, { IMM6U, Rc } },              /* imm6u,Rc */
446 
  { SHORT_D2Br, 2, { IMM6U, REL12S3 } },        /* imm6u,rel12s3 */
447 
  { SHORT_U, 0, { Ra, Rb } },                    /* Ra,Rb */
448 
  { SHORT_F, 0, { Fa, Fb, Fc } },                /* Fa,Fb,Fc  (orfg, xorfg) */
449 
  { SHORT_F, 2, { Fa, Fb, IMM6 } },             /* Fa,Fb,imm6 */
450 
  { SHORT_AF, 0, { Fa, Rb, Rc } },               /* Fa,Rb,Rc */
451 
  { SHORT_AF, 2, { Fa, Rb, IMM6 } },            /* Fa,Rb,imm6 */
452 
  { SHORT_T, 2, { IMM5 } },                     /* imm5s3   (trap) */
453 
  { SHORT_A5, 0, { Ra, Rb, Rc } },               /* Ra,Rb,Rc */
454 
  { SHORT_A5, 2, { Ra, Rb, IMM5 } },            /* Ra,Rb,imm5    (sat*) */
455 
  { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} },          /* CC  Fa2,Rb,Rc */
456 
  { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} },       /* CC  Fa2,Rb,imm6 */
457 
  { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC  Fa2,Rb,Rc */
458 
  { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} },    /* CC  Fa2,Rb,imm6 */
459 
  { SHORT_A1, 1, { Ra, Rb, Rc } },              /* Ra,Rb,Rc for MAC where a=1 */
460 
  { SHORT_A1, 3, { Ra, Rb, IMM6 } },            /* Ra,Rb,imm6 for MAC where a=1 */
461 
  { SHORT_AA, 0, { Aa, Rb, Rc } },               /* Aa,Rb,Rc */
462 
  { SHORT_AA, 2, { Aa, Rb, IMM6 } },            /* Aa,Rb,imm6 */
463 
  { SHORT_RA, 0, { Ra, Ab, Rc } },               /* Ra,Ab,Rc */
464 
  { SHORT_RA, 2, { Ra, Ab, IMM6U2 } },          /* Ra,Ab,imm6u */
465 
  { SHORT_MODINC, 1, { Rb2, IMM5 } },           /* Rb2,imm5 (modinc) */
466 
  { SHORT_MODDEC, 3, { Rb2, IMM5 } },           /* Rb2,imm5 (moddec) */
467 
  { SHORT_C1, 0, { Ra, Cb, Fake } },             /* Ra,Cb (mvfsys) */
468 
  { SHORT_C2, 0, { Ca, Rb, Fake } },             /* Ca,Rb (mvtsys) */
469 
  { SHORT_UF, 0, { Fa, Fb } },                   /* Fa,Fb  (notfg) */
470 
  { SHORT_A2, 0, { Ra2, Rb, Rc } },              /* Ra2,Rb,Rc */
471 
  { SHORT_A2, 2, { Ra2, Rb, IMM6 } },           /* Ra2,Rb,imm6 */
472 
  { SHORT_NONE, 0, { 0 } },                       /* no operands (nop, reit) */
473 
  { SHORT_AR, 0, { Aa, Rb, Rc } },               /* Aa,Rb,Rc */
474 
  { LONG, 2, { Ra, Rb, IMM32 } },               /* Ra,Rb,imm32 */
475 
  { LONG_U, 2, { IMM32 } },                     /* imm32 */
476 
  { LONG_Ur, 2, { REL32 } },                    /* rel32 */
477 
  { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} },       /* CC  Fa2,Rb,imm32 */
478 
  { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } },      /* Ra,@(Rb,imm32) */
479 
  { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } },    /* Ra,@(Rb,imm32) */
480 
  { LONG_2, 2, { Ra3, IMM32 } },                /* Ra,imm32 */
481 
  { LONG_2r, 2, { Ra3, REL32 } },               /* Ra,rel32 */
482 
  { LONG_2b, 3, { Ra3, IMM32 } },               /* Ra,imm32 */
483 
  { LONG_2br, 3, { Ra3, REL32 } },              /* Ra,rel32 */
484 
  { LONG_D, 2, { REL6S3, IMM32 } },             /* rel6s3,imm32 */
485 
  { LONG_Dr, 2, { REL6S3, REL32 } },            /* rel6s3,rel32 */
486 
  { LONG_Dbr, 2, { IMM6U, REL32 } },            /* imm6,rel32 */
487 
  { 0, 0, { 0 } },
488 
};
489 
 
490 
const char *d30v_ecc_names[] =
491 
{
492 
  "al",
493 
  "tx",
494 
  "fx",
495 
  "xt",
496 
  "xf",
497 
  "tt",
498 
  "tf",
499 
  "res"
500 
};
501 
 
502 
const char *d30v_cc_names[] =
503 
{
504 
  "eq",
505 
  "ne",
506 
  "gt",
507 
  "ge",
508 
  "lt",
509 
  "le",
510 
  "ps",
511 
  "ng",
512 
  NULL
513 
};

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