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[/] [or1k/] [trunk/] [gdb-5.3/] [opcodes/] [m32r-desc.c] - Blame information for rev 1777

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1 1181 sfurman 
/* CPU data for m32r.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <stdio.h>
27 
#include <stdarg.h>
28 
#include "ansidecl.h"
29 
#include "bfd.h"
30 
#include "symcat.h"
31 
#include "m32r-desc.h"
32 
#include "m32r-opc.h"
33 
#include "opintl.h"
34 
#include "libiberty.h"
35 
 
36 
/* Attributes.  */
37 
 
38 
static const CGEN_ATTR_ENTRY bool_attr[] =
39 
{
40 
  { "#f", 0 },
41 
  { "#t", 1 },
42 
  { 0, 0 }
43 
};
44 
 
45 
static const CGEN_ATTR_ENTRY MACH_attr[] =
46 
{
47 
  { "base", MACH_BASE },
48 
  { "m32r", MACH_M32R },
49 
  { "m32rx", MACH_M32RX },
50 
  { "max", MACH_MAX },
51 
  { 0, 0 }
52 
};
53 
 
54 
static const CGEN_ATTR_ENTRY ISA_attr[] =
55 
{
56 
  { "m32r", ISA_M32R },
57 
  { "max", ISA_MAX },
58 
  { 0, 0 }
59 
};
60 
 
61 
static const CGEN_ATTR_ENTRY PIPE_attr[] =
62 
{
63 
  { "NONE", PIPE_NONE },
64 
  { "O", PIPE_O },
65 
  { "S", PIPE_S },
66 
  { "OS", PIPE_OS },
67 
  { 0, 0 }
68 
};
69 
 
70 
const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
71 
{
72 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
73 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
74 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
75 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
76 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
77 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
78 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
79 
  { "RELOC", &bool_attr[0], &bool_attr[0] },
80 
  { 0, 0, 0 }
81 
};
82 
 
83 
const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
84 
{
85 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
86 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
88 
  { "PC", &bool_attr[0], &bool_attr[0] },
89 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
90 
  { 0, 0, 0 }
91 
};
92 
 
93 
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
94 
{
95 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
96 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
97 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
98 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
99 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
100 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
101 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
102 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
103 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
104 
  { "RELOC", &bool_attr[0], &bool_attr[0] },
105 
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
106 
  { 0, 0, 0 }
107 
};
108 
 
109 
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
110 
{
111 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
112 
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
113 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
114 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
115 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
116 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
117 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
118 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
119 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
120 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
121 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
122 
  { "PBB", &bool_attr[0], &bool_attr[0] },
123 
  { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
124 
  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
125 
  { 0, 0, 0 }
126 
};
127 
 
128 
/* Instruction set variants.  */
129 
 
130 
static const CGEN_ISA m32r_cgen_isa_table[] = {
131 
  { "m32r", 32, 32, 16, 32 },
132 
  { 0, 0, 0, 0, 0 }
133 
};
134 
 
135 
/* Machine variants.  */
136 
 
137 
static const CGEN_MACH m32r_cgen_mach_table[] = {
138 
  { "m32r", "m32r", MACH_M32R, 0 },
139 
  { "m32rx", "m32rx", MACH_M32RX, 0 },
140 
  { 0, 0, 0, 0 }
141 
};
142 
 
143 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
144 
{
145 
  { "fp", 13, {0, {0}}, 0, 0 },
146 
  { "lr", 14, {0, {0}}, 0, 0 },
147 
  { "sp", 15, {0, {0}}, 0, 0 },
148 
  { "r0", 0, {0, {0}}, 0, 0 },
149 
  { "r1", 1, {0, {0}}, 0, 0 },
150 
  { "r2", 2, {0, {0}}, 0, 0 },
151 
  { "r3", 3, {0, {0}}, 0, 0 },
152 
  { "r4", 4, {0, {0}}, 0, 0 },
153 
  { "r5", 5, {0, {0}}, 0, 0 },
154 
  { "r6", 6, {0, {0}}, 0, 0 },
155 
  { "r7", 7, {0, {0}}, 0, 0 },
156 
  { "r8", 8, {0, {0}}, 0, 0 },
157 
  { "r9", 9, {0, {0}}, 0, 0 },
158 
  { "r10", 10, {0, {0}}, 0, 0 },
159 
  { "r11", 11, {0, {0}}, 0, 0 },
160 
  { "r12", 12, {0, {0}}, 0, 0 },
161 
  { "r13", 13, {0, {0}}, 0, 0 },
162 
  { "r14", 14, {0, {0}}, 0, 0 },
163 
  { "r15", 15, {0, {0}}, 0, 0 }
164 
};
165 
 
166 
CGEN_KEYWORD m32r_cgen_opval_gr_names =
167 
{
168 
  & m32r_cgen_opval_gr_names_entries[0],
169 
  19,
170 
  0, 0, 0, 0, ""
171 
};
172 
 
173 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
174 
{
175 
  { "psw", 0, {0, {0}}, 0, 0 },
176 
  { "cbr", 1, {0, {0}}, 0, 0 },
177 
  { "spi", 2, {0, {0}}, 0, 0 },
178 
  { "spu", 3, {0, {0}}, 0, 0 },
179 
  { "bpc", 6, {0, {0}}, 0, 0 },
180 
  { "bbpsw", 8, {0, {0}}, 0, 0 },
181 
  { "bbpc", 14, {0, {0}}, 0, 0 },
182 
  { "cr0", 0, {0, {0}}, 0, 0 },
183 
  { "cr1", 1, {0, {0}}, 0, 0 },
184 
  { "cr2", 2, {0, {0}}, 0, 0 },
185 
  { "cr3", 3, {0, {0}}, 0, 0 },
186 
  { "cr4", 4, {0, {0}}, 0, 0 },
187 
  { "cr5", 5, {0, {0}}, 0, 0 },
188 
  { "cr6", 6, {0, {0}}, 0, 0 },
189 
  { "cr7", 7, {0, {0}}, 0, 0 },
190 
  { "cr8", 8, {0, {0}}, 0, 0 },
191 
  { "cr9", 9, {0, {0}}, 0, 0 },
192 
  { "cr10", 10, {0, {0}}, 0, 0 },
193 
  { "cr11", 11, {0, {0}}, 0, 0 },
194 
  { "cr12", 12, {0, {0}}, 0, 0 },
195 
  { "cr13", 13, {0, {0}}, 0, 0 },
196 
  { "cr14", 14, {0, {0}}, 0, 0 },
197 
  { "cr15", 15, {0, {0}}, 0, 0 }
198 
};
199 
 
200 
CGEN_KEYWORD m32r_cgen_opval_cr_names =
201 
{
202 
  & m32r_cgen_opval_cr_names_entries[0],
203 
  23,
204 
  0, 0, 0, 0, ""
205 
};
206 
 
207 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
208 
{
209 
  { "a0", 0, {0, {0}}, 0, 0 },
210 
  { "a1", 1, {0, {0}}, 0, 0 }
211 
};
212 
 
213 
CGEN_KEYWORD m32r_cgen_opval_h_accums =
214 
{
215 
  & m32r_cgen_opval_h_accums_entries[0],
216 
  2,
217 
  0, 0, 0, 0, ""
218 
};
219 
 
220 
 
221 
/* The hardware table.  */
222 
 
223 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
224 
#define A(a) (1 << CGEN_HW_##a)
225 
#else
226 
#define A(a) (1 << CGEN_HW_/**/a)
227 
#endif
228 
 
229 
const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
230 
{
231 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
234 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
235 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
236 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
237 
  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
238 
  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
239 
  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
240 
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
241 
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
242 
  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
243 
  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
244 
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
245 
  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
246 
  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
247 
  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
248 
  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
249 
  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
250 
};
251 
 
252 
#undef A
253 
 
254 
 
255 
/* The instruction field table.  */
256 
 
257 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
258 
#define A(a) (1 << CGEN_IFLD_##a)
259 
#else
260 
#define A(a) (1 << CGEN_IFLD_/**/a)
261 
#endif
262 
 
263 
const CGEN_IFLD m32r_cgen_ifld_table[] =
264 
{
265 
  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
266 
  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
267 
  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
268 
  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
269 
  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
270 
  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
271 
  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
272 
  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
273 
  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
274 
  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
275 
  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
276 
  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
277 
  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
278 
  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
279 
  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
280 
  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
281 
  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
282 
  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
283 
  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
284 
  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
285 
  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
286 
  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
287 
  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
288 
  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
289 
  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
290 
  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
291 
  { 0, 0, 0, 0, 0, 0, {0, {0}} }
292 
};
293 
 
294 
#undef A
295 
 
296 
 
297 
 
298 
/* multi ifield declarations */
299 
 
300 
 
301 
 
302 
/* multi ifield definitions */
303 
 
304 
 
305 
/* The operand table.  */
306 
 
307 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
308 
#define A(a) (1 << CGEN_OPERAND_##a)
309 
#else
310 
#define A(a) (1 << CGEN_OPERAND_/**/a)
311 
#endif
312 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
313 
#define OPERAND(op) M32R_OPERAND_##op
314 
#else
315 
#define OPERAND(op) M32R_OPERAND_/**/op
316 
#endif
317 
 
318 
const CGEN_OPERAND m32r_cgen_operand_table[] =
319 
{
320 
/* pc: program counter */
321 
  { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
322 
    { 0, &(m32r_cgen_ifld_table[0]) },
323 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
324 
/* sr: source register */
325 
  { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
326 
    { 0, &(m32r_cgen_ifld_table[6]) },
327 
    { 0, { (1<<MACH_BASE) } }  },
328 
/* dr: destination register */
329 
  { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
330 
    { 0, &(m32r_cgen_ifld_table[5]) },
331 
    { 0, { (1<<MACH_BASE) } }  },
332 
/* src1: source register 1 */
333 
  { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
334 
    { 0, &(m32r_cgen_ifld_table[5]) },
335 
    { 0, { (1<<MACH_BASE) } }  },
336 
/* src2: source register 2 */
337 
  { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
338 
    { 0, &(m32r_cgen_ifld_table[6]) },
339 
    { 0, { (1<<MACH_BASE) } }  },
340 
/* scr: source control register */
341 
  { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
342 
    { 0, &(m32r_cgen_ifld_table[6]) },
343 
    { 0, { (1<<MACH_BASE) } }  },
344 
/* dcr: destination control register */
345 
  { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
346 
    { 0, &(m32r_cgen_ifld_table[5]) },
347 
    { 0, { (1<<MACH_BASE) } }  },
348 
/* simm8: 8 bit signed immediate */
349 
  { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
350 
    { 0, &(m32r_cgen_ifld_table[7]) },
351 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
352 
/* simm16: 16 bit signed immediate */
353 
  { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
354 
    { 0, &(m32r_cgen_ifld_table[8]) },
355 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
356 
/* uimm4: 4 bit trap number */
357 
  { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
358 
    { 0, &(m32r_cgen_ifld_table[10]) },
359 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
360 
/* uimm5: 5 bit shift count */
361 
  { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
362 
    { 0, &(m32r_cgen_ifld_table[11]) },
363 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
364 
/* uimm16: 16 bit unsigned immediate */
365 
  { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
366 
    { 0, &(m32r_cgen_ifld_table[12]) },
367 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
368 
/* imm1: 1 bit immediate */
369 
  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
370 
    { 0, &(m32r_cgen_ifld_table[25]) },
371 
    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
372 
/* accd: accumulator destination register */
373 
  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
374 
    { 0, &(m32r_cgen_ifld_table[22]) },
375 
    { 0, { (1<<MACH_M32RX) } }  },
376 
/* accs: accumulator source register */
377 
  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
378 
    { 0, &(m32r_cgen_ifld_table[21]) },
379 
    { 0, { (1<<MACH_M32RX) } }  },
380 
/* acc: accumulator reg (d) */
381 
  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
382 
    { 0, &(m32r_cgen_ifld_table[20]) },
383 
    { 0, { (1<<MACH_M32RX) } }  },
384 
/* hash: # prefix */
385 
  { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
386 
    { 0, 0 },
387 
    { 0, { (1<<MACH_BASE) } }  },
388 
/* hi16: high 16 bit immediate, sign optional */
389 
  { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
390 
    { 0, &(m32r_cgen_ifld_table[14]) },
391 
    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
392 
/* slo16: 16 bit signed immediate, for low() */
393 
  { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
394 
    { 0, &(m32r_cgen_ifld_table[8]) },
395 
    { 0, { (1<<MACH_BASE) } }  },
396 
/* ulo16: 16 bit unsigned immediate, for low() */
397 
  { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
398 
    { 0, &(m32r_cgen_ifld_table[12]) },
399 
    { 0, { (1<<MACH_BASE) } }  },
400 
/* uimm24: 24 bit address */
401 
  { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
402 
    { 0, &(m32r_cgen_ifld_table[13]) },
403 
    { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
404 
/* disp8: 8 bit displacement */
405 
  { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
406 
    { 0, &(m32r_cgen_ifld_table[15]) },
407 
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
408 
/* disp16: 16 bit displacement */
409 
  { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
410 
    { 0, &(m32r_cgen_ifld_table[16]) },
411 
    { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
412 
/* disp24: 24 bit displacement */
413 
  { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
414 
    { 0, &(m32r_cgen_ifld_table[17]) },
415 
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
416 
/* condbit: condition bit */
417 
  { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
418 
    { 0, 0 },
419 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
420 
/* accum: accumulator */
421 
  { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
422 
    { 0, 0 },
423 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
424 
  { 0, 0, 0, 0, 0, {0, {0}} }
425 
};
426 
 
427 
#undef A
428 
 
429 
 
430 
/* The instruction table.  */
431 
 
432 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
433 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
434 
#define A(a) (1 << CGEN_INSN_##a)
435 
#else
436 
#define A(a) (1 << CGEN_INSN_/**/a)
437 
#endif
438 
 
439 
static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
440 
{
441 
  /* Special null first entry.
442 
     A `num' value of zero is thus invalid.
443 
     Also, the special `invalid' insn resides here.  */
444 
  { 0, 0, 0, 0, {0, {0}} },
445 
/* add $dr,$sr */
446 
  {
447 
    M32R_INSN_ADD, "add", "add", 16,
448 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
449 
  },
450 
/* add3 $dr,$sr,$hash$slo16 */
451 
  {
452 
    M32R_INSN_ADD3, "add3", "add3", 32,
453 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
454 
  },
455 
/* and $dr,$sr */
456 
  {
457 
    M32R_INSN_AND, "and", "and", 16,
458 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
459 
  },
460 
/* and3 $dr,$sr,$uimm16 */
461 
  {
462 
    M32R_INSN_AND3, "and3", "and3", 32,
463 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
464 
  },
465 
/* or $dr,$sr */
466 
  {
467 
    M32R_INSN_OR, "or", "or", 16,
468 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
469 
  },
470 
/* or3 $dr,$sr,$hash$ulo16 */
471 
  {
472 
    M32R_INSN_OR3, "or3", "or3", 32,
473 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
474 
  },
475 
/* xor $dr,$sr */
476 
  {
477 
    M32R_INSN_XOR, "xor", "xor", 16,
478 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
479 
  },
480 
/* xor3 $dr,$sr,$uimm16 */
481 
  {
482 
    M32R_INSN_XOR3, "xor3", "xor3", 32,
483 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
484 
  },
485 
/* addi $dr,$simm8 */
486 
  {
487 
    M32R_INSN_ADDI, "addi", "addi", 16,
488 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
489 
  },
490 
/* addv $dr,$sr */
491 
  {
492 
    M32R_INSN_ADDV, "addv", "addv", 16,
493 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
494 
  },
495 
/* addv3 $dr,$sr,$simm16 */
496 
  {
497 
    M32R_INSN_ADDV3, "addv3", "addv3", 32,
498 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
499 
  },
500 
/* addx $dr,$sr */
501 
  {
502 
    M32R_INSN_ADDX, "addx", "addx", 16,
503 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
504 
  },
505 
/* bc.s $disp8 */
506 
  {
507 
    M32R_INSN_BC8, "bc8", "bc.s", 16,
508 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
509 
  },
510 
/* bc.l $disp24 */
511 
  {
512 
    M32R_INSN_BC24, "bc24", "bc.l", 32,
513 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
514 
  },
515 
/* beq $src1,$src2,$disp16 */
516 
  {
517 
    M32R_INSN_BEQ, "beq", "beq", 32,
518 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
519 
  },
520 
/* beqz $src2,$disp16 */
521 
  {
522 
    M32R_INSN_BEQZ, "beqz", "beqz", 32,
523 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
524 
  },
525 
/* bgez $src2,$disp16 */
526 
  {
527 
    M32R_INSN_BGEZ, "bgez", "bgez", 32,
528 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
529 
  },
530 
/* bgtz $src2,$disp16 */
531 
  {
532 
    M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
533 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
534 
  },
535 
/* blez $src2,$disp16 */
536 
  {
537 
    M32R_INSN_BLEZ, "blez", "blez", 32,
538 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
539 
  },
540 
/* bltz $src2,$disp16 */
541 
  {
542 
    M32R_INSN_BLTZ, "bltz", "bltz", 32,
543 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
544 
  },
545 
/* bnez $src2,$disp16 */
546 
  {
547 
    M32R_INSN_BNEZ, "bnez", "bnez", 32,
548 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
549 
  },
550 
/* bl.s $disp8 */
551 
  {
552 
    M32R_INSN_BL8, "bl8", "bl.s", 16,
553 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
554 
  },
555 
/* bl.l $disp24 */
556 
  {
557 
    M32R_INSN_BL24, "bl24", "bl.l", 32,
558 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
559 
  },
560 
/* bcl.s $disp8 */
561 
  {
562 
    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
563 
    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
564 
  },
565 
/* bcl.l $disp24 */
566 
  {
567 
    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
568 
    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
569 
  },
570 
/* bnc.s $disp8 */
571 
  {
572 
    M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
573 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
574 
  },
575 
/* bnc.l $disp24 */
576 
  {
577 
    M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
578 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
579 
  },
580 
/* bne $src1,$src2,$disp16 */
581 
  {
582 
    M32R_INSN_BNE, "bne", "bne", 32,
583 
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
584 
  },
585 
/* bra.s $disp8 */
586 
  {
587 
    M32R_INSN_BRA8, "bra8", "bra.s", 16,
588 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
589 
  },
590 
/* bra.l $disp24 */
591 
  {
592 
    M32R_INSN_BRA24, "bra24", "bra.l", 32,
593 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
594 
  },
595 
/* bncl.s $disp8 */
596 
  {
597 
    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
598 
    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
599 
  },
600 
/* bncl.l $disp24 */
601 
  {
602 
    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
603 
    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
604 
  },
605 
/* cmp $src1,$src2 */
606 
  {
607 
    M32R_INSN_CMP, "cmp", "cmp", 16,
608 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
609 
  },
610 
/* cmpi $src2,$simm16 */
611 
  {
612 
    M32R_INSN_CMPI, "cmpi", "cmpi", 32,
613 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
614 
  },
615 
/* cmpu $src1,$src2 */
616 
  {
617 
    M32R_INSN_CMPU, "cmpu", "cmpu", 16,
618 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
619 
  },
620 
/* cmpui $src2,$simm16 */
621 
  {
622 
    M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
623 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
624 
  },
625 
/* cmpeq $src1,$src2 */
626 
  {
627 
    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
628 
    { 0, { (1<<MACH_M32RX), PIPE_OS } }
629 
  },
630 
/* cmpz $src2 */
631 
  {
632 
    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
633 
    { 0, { (1<<MACH_M32RX), PIPE_OS } }
634 
  },
635 
/* div $dr,$sr */
636 
  {
637 
    M32R_INSN_DIV, "div", "div", 32,
638 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
639 
  },
640 
/* divu $dr,$sr */
641 
  {
642 
    M32R_INSN_DIVU, "divu", "divu", 32,
643 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
644 
  },
645 
/* rem $dr,$sr */
646 
  {
647 
    M32R_INSN_REM, "rem", "rem", 32,
648 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
649 
  },
650 
/* remu $dr,$sr */
651 
  {
652 
    M32R_INSN_REMU, "remu", "remu", 32,
653 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
654 
  },
655 
/* divh $dr,$sr */
656 
  {
657 
    M32R_INSN_DIVH, "divh", "divh", 32,
658 
    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
659 
  },
660 
/* jc $sr */
661 
  {
662 
    M32R_INSN_JC, "jc", "jc", 16,
663 
    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
664 
  },
665 
/* jnc $sr */
666 
  {
667 
    M32R_INSN_JNC, "jnc", "jnc", 16,
668 
    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
669 
  },
670 
/* jl $sr */
671 
  {
672 
    M32R_INSN_JL, "jl", "jl", 16,
673 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
674 
  },
675 
/* jmp $sr */
676 
  {
677 
    M32R_INSN_JMP, "jmp", "jmp", 16,
678 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
679 
  },
680 
/* ld $dr,@$sr */
681 
  {
682 
    M32R_INSN_LD, "ld", "ld", 16,
683 
    { 0, { (1<<MACH_BASE), PIPE_O } }
684 
  },
685 
/* ld $dr,@($slo16,$sr) */
686 
  {
687 
    M32R_INSN_LD_D, "ld-d", "ld", 32,
688 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
689 
  },
690 
/* ldb $dr,@$sr */
691 
  {
692 
    M32R_INSN_LDB, "ldb", "ldb", 16,
693 
    { 0, { (1<<MACH_BASE), PIPE_O } }
694 
  },
695 
/* ldb $dr,@($slo16,$sr) */
696 
  {
697 
    M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
698 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
699 
  },
700 
/* ldh $dr,@$sr */
701 
  {
702 
    M32R_INSN_LDH, "ldh", "ldh", 16,
703 
    { 0, { (1<<MACH_BASE), PIPE_O } }
704 
  },
705 
/* ldh $dr,@($slo16,$sr) */
706 
  {
707 
    M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
708 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
709 
  },
710 
/* ldub $dr,@$sr */
711 
  {
712 
    M32R_INSN_LDUB, "ldub", "ldub", 16,
713 
    { 0, { (1<<MACH_BASE), PIPE_O } }
714 
  },
715 
/* ldub $dr,@($slo16,$sr) */
716 
  {
717 
    M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
718 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
719 
  },
720 
/* lduh $dr,@$sr */
721 
  {
722 
    M32R_INSN_LDUH, "lduh", "lduh", 16,
723 
    { 0, { (1<<MACH_BASE), PIPE_O } }
724 
  },
725 
/* lduh $dr,@($slo16,$sr) */
726 
  {
727 
    M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
728 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
729 
  },
730 
/* ld $dr,@$sr+ */
731 
  {
732 
    M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
733 
    { 0, { (1<<MACH_BASE), PIPE_O } }
734 
  },
735 
/* ld24 $dr,$uimm24 */
736 
  {
737 
    M32R_INSN_LD24, "ld24", "ld24", 32,
738 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
739 
  },
740 
/* ldi8 $dr,$simm8 */
741 
  {
742 
    M32R_INSN_LDI8, "ldi8", "ldi8", 16,
743 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
744 
  },
745 
/* ldi16 $dr,$hash$slo16 */
746 
  {
747 
    M32R_INSN_LDI16, "ldi16", "ldi16", 32,
748 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
749 
  },
750 
/* lock $dr,@$sr */
751 
  {
752 
    M32R_INSN_LOCK, "lock", "lock", 16,
753 
    { 0, { (1<<MACH_BASE), PIPE_O } }
754 
  },
755 
/* machi $src1,$src2 */
756 
  {
757 
    M32R_INSN_MACHI, "machi", "machi", 16,
758 
    { 0, { (1<<MACH_M32R), PIPE_S } }
759 
  },
760 
/* machi $src1,$src2,$acc */
761 
  {
762 
    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
763 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
764 
  },
765 
/* maclo $src1,$src2 */
766 
  {
767 
    M32R_INSN_MACLO, "maclo", "maclo", 16,
768 
    { 0, { (1<<MACH_M32R), PIPE_S } }
769 
  },
770 
/* maclo $src1,$src2,$acc */
771 
  {
772 
    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
773 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
774 
  },
775 
/* macwhi $src1,$src2 */
776 
  {
777 
    M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
778 
    { 0, { (1<<MACH_M32R), PIPE_S } }
779 
  },
780 
/* macwhi $src1,$src2,$acc */
781 
  {
782 
    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
783 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
784 
  },
785 
/* macwlo $src1,$src2 */
786 
  {
787 
    M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
788 
    { 0, { (1<<MACH_M32R), PIPE_S } }
789 
  },
790 
/* macwlo $src1,$src2,$acc */
791 
  {
792 
    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
793 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
794 
  },
795 
/* mul $dr,$sr */
796 
  {
797 
    M32R_INSN_MUL, "mul", "mul", 16,
798 
    { 0, { (1<<MACH_BASE), PIPE_S } }
799 
  },
800 
/* mulhi $src1,$src2 */
801 
  {
802 
    M32R_INSN_MULHI, "mulhi", "mulhi", 16,
803 
    { 0, { (1<<MACH_M32R), PIPE_S } }
804 
  },
805 
/* mulhi $src1,$src2,$acc */
806 
  {
807 
    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
808 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
809 
  },
810 
/* mullo $src1,$src2 */
811 
  {
812 
    M32R_INSN_MULLO, "mullo", "mullo", 16,
813 
    { 0, { (1<<MACH_M32R), PIPE_S } }
814 
  },
815 
/* mullo $src1,$src2,$acc */
816 
  {
817 
    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
818 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
819 
  },
820 
/* mulwhi $src1,$src2 */
821 
  {
822 
    M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
823 
    { 0, { (1<<MACH_M32R), PIPE_S } }
824 
  },
825 
/* mulwhi $src1,$src2,$acc */
826 
  {
827 
    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
828 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
829 
  },
830 
/* mulwlo $src1,$src2 */
831 
  {
832 
    M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
833 
    { 0, { (1<<MACH_M32R), PIPE_S } }
834 
  },
835 
/* mulwlo $src1,$src2,$acc */
836 
  {
837 
    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
838 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
839 
  },
840 
/* mv $dr,$sr */
841 
  {
842 
    M32R_INSN_MV, "mv", "mv", 16,
843 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
844 
  },
845 
/* mvfachi $dr */
846 
  {
847 
    M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
848 
    { 0, { (1<<MACH_M32R), PIPE_S } }
849 
  },
850 
/* mvfachi $dr,$accs */
851 
  {
852 
    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
853 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
854 
  },
855 
/* mvfaclo $dr */
856 
  {
857 
    M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
858 
    { 0, { (1<<MACH_M32R), PIPE_S } }
859 
  },
860 
/* mvfaclo $dr,$accs */
861 
  {
862 
    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
863 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
864 
  },
865 
/* mvfacmi $dr */
866 
  {
867 
    M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
868 
    { 0, { (1<<MACH_M32R), PIPE_S } }
869 
  },
870 
/* mvfacmi $dr,$accs */
871 
  {
872 
    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
873 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
874 
  },
875 
/* mvfc $dr,$scr */
876 
  {
877 
    M32R_INSN_MVFC, "mvfc", "mvfc", 16,
878 
    { 0, { (1<<MACH_BASE), PIPE_O } }
879 
  },
880 
/* mvtachi $src1 */
881 
  {
882 
    M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
883 
    { 0, { (1<<MACH_M32R), PIPE_S } }
884 
  },
885 
/* mvtachi $src1,$accs */
886 
  {
887 
    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
888 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
889 
  },
890 
/* mvtaclo $src1 */
891 
  {
892 
    M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
893 
    { 0, { (1<<MACH_M32R), PIPE_S } }
894 
  },
895 
/* mvtaclo $src1,$accs */
896 
  {
897 
    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
898 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
899 
  },
900 
/* mvtc $sr,$dcr */
901 
  {
902 
    M32R_INSN_MVTC, "mvtc", "mvtc", 16,
903 
    { 0, { (1<<MACH_BASE), PIPE_O } }
904 
  },
905 
/* neg $dr,$sr */
906 
  {
907 
    M32R_INSN_NEG, "neg", "neg", 16,
908 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
909 
  },
910 
/* nop */
911 
  {
912 
    M32R_INSN_NOP, "nop", "nop", 16,
913 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
914 
  },
915 
/* not $dr,$sr */
916 
  {
917 
    M32R_INSN_NOT, "not", "not", 16,
918 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
919 
  },
920 
/* rac */
921 
  {
922 
    M32R_INSN_RAC, "rac", "rac", 16,
923 
    { 0, { (1<<MACH_M32R), PIPE_S } }
924 
  },
925 
/* rac $accd,$accs,$imm1 */
926 
  {
927 
    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
928 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
929 
  },
930 
/* rach */
931 
  {
932 
    M32R_INSN_RACH, "rach", "rach", 16,
933 
    { 0, { (1<<MACH_M32R), PIPE_S } }
934 
  },
935 
/* rach $accd,$accs,$imm1 */
936 
  {
937 
    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
938 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
939 
  },
940 
/* rte */
941 
  {
942 
    M32R_INSN_RTE, "rte", "rte", 16,
943 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
944 
  },
945 
/* seth $dr,$hash$hi16 */
946 
  {
947 
    M32R_INSN_SETH, "seth", "seth", 32,
948 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
949 
  },
950 
/* sll $dr,$sr */
951 
  {
952 
    M32R_INSN_SLL, "sll", "sll", 16,
953 
    { 0, { (1<<MACH_BASE), PIPE_O } }
954 
  },
955 
/* sll3 $dr,$sr,$simm16 */
956 
  {
957 
    M32R_INSN_SLL3, "sll3", "sll3", 32,
958 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
959 
  },
960 
/* slli $dr,$uimm5 */
961 
  {
962 
    M32R_INSN_SLLI, "slli", "slli", 16,
963 
    { 0, { (1<<MACH_BASE), PIPE_O } }
964 
  },
965 
/* sra $dr,$sr */
966 
  {
967 
    M32R_INSN_SRA, "sra", "sra", 16,
968 
    { 0, { (1<<MACH_BASE), PIPE_O } }
969 
  },
970 
/* sra3 $dr,$sr,$simm16 */
971 
  {
972 
    M32R_INSN_SRA3, "sra3", "sra3", 32,
973 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
974 
  },
975 
/* srai $dr,$uimm5 */
976 
  {
977 
    M32R_INSN_SRAI, "srai", "srai", 16,
978 
    { 0, { (1<<MACH_BASE), PIPE_O } }
979 
  },
980 
/* srl $dr,$sr */
981 
  {
982 
    M32R_INSN_SRL, "srl", "srl", 16,
983 
    { 0, { (1<<MACH_BASE), PIPE_O } }
984 
  },
985 
/* srl3 $dr,$sr,$simm16 */
986 
  {
987 
    M32R_INSN_SRL3, "srl3", "srl3", 32,
988 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
989 
  },
990 
/* srli $dr,$uimm5 */
991 
  {
992 
    M32R_INSN_SRLI, "srli", "srli", 16,
993 
    { 0, { (1<<MACH_BASE), PIPE_O } }
994 
  },
995 
/* st $src1,@$src2 */
996 
  {
997 
    M32R_INSN_ST, "st", "st", 16,
998 
    { 0, { (1<<MACH_BASE), PIPE_O } }
999 
  },
1000 
/* st $src1,@($slo16,$src2) */
1001 
  {
1002 
    M32R_INSN_ST_D, "st-d", "st", 32,
1003 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
1004 
  },
1005 
/* stb $src1,@$src2 */
1006 
  {
1007 
    M32R_INSN_STB, "stb", "stb", 16,
1008 
    { 0, { (1<<MACH_BASE), PIPE_O } }
1009 
  },
1010 
/* stb $src1,@($slo16,$src2) */
1011 
  {
1012 
    M32R_INSN_STB_D, "stb-d", "stb", 32,
1013 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
1014 
  },
1015 
/* sth $src1,@$src2 */
1016 
  {
1017 
    M32R_INSN_STH, "sth", "sth", 16,
1018 
    { 0, { (1<<MACH_BASE), PIPE_O } }
1019 
  },
1020 
/* sth $src1,@($slo16,$src2) */
1021 
  {
1022 
    M32R_INSN_STH_D, "sth-d", "sth", 32,
1023 
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
1024 
  },
1025 
/* st $src1,@+$src2 */
1026 
  {
1027 
    M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1028 
    { 0, { (1<<MACH_BASE), PIPE_O } }
1029 
  },
1030 
/* st $src1,@-$src2 */
1031 
  {
1032 
    M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1033 
    { 0, { (1<<MACH_BASE), PIPE_O } }
1034 
  },
1035 
/* sub $dr,$sr */
1036 
  {
1037 
    M32R_INSN_SUB, "sub", "sub", 16,
1038 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
1039 
  },
1040 
/* subv $dr,$sr */
1041 
  {
1042 
    M32R_INSN_SUBV, "subv", "subv", 16,
1043 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
1044 
  },
1045 
/* subx $dr,$sr */
1046 
  {
1047 
    M32R_INSN_SUBX, "subx", "subx", 16,
1048 
    { 0, { (1<<MACH_BASE), PIPE_OS } }
1049 
  },
1050 
/* trap $uimm4 */
1051 
  {
1052 
    M32R_INSN_TRAP, "trap", "trap", 16,
1053 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1054 
  },
1055 
/* unlock $src1,@$src2 */
1056 
  {
1057 
    M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1058 
    { 0, { (1<<MACH_BASE), PIPE_O } }
1059 
  },
1060 
/* satb $dr,$sr */
1061 
  {
1062 
    M32R_INSN_SATB, "satb", "satb", 32,
1063 
    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1064 
  },
1065 
/* sath $dr,$sr */
1066 
  {
1067 
    M32R_INSN_SATH, "sath", "sath", 32,
1068 
    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1069 
  },
1070 
/* sat $dr,$sr */
1071 
  {
1072 
    M32R_INSN_SAT, "sat", "sat", 32,
1073 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1074 
  },
1075 
/* pcmpbz $src2 */
1076 
  {
1077 
    M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1078 
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1079 
  },
1080 
/* sadd */
1081 
  {
1082 
    M32R_INSN_SADD, "sadd", "sadd", 16,
1083 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
1084 
  },
1085 
/* macwu1 $src1,$src2 */
1086 
  {
1087 
    M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1088 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
1089 
  },
1090 
/* msblo $src1,$src2 */
1091 
  {
1092 
    M32R_INSN_MSBLO, "msblo", "msblo", 16,
1093 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
1094 
  },
1095 
/* mulwu1 $src1,$src2 */
1096 
  {
1097 
    M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1098 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
1099 
  },
1100 
/* maclh1 $src1,$src2 */
1101 
  {
1102 
    M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1103 
    { 0, { (1<<MACH_M32RX), PIPE_S } }
1104 
  },
1105 
/* sc */
1106 
  {
1107 
    M32R_INSN_SC, "sc", "sc", 16,
1108 
    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1109 
  },
1110 
/* snc */
1111 
  {
1112 
    M32R_INSN_SNC, "snc", "snc", 16,
1113 
    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1114 
  },
1115 
};
1116 
 
1117 
#undef OP
1118 
#undef A
1119 
 
1120 
/* Initialize anything needed to be done once, before any cpu_open call.  */
1121 
static void init_tables PARAMS ((void));
1122 
 
1123 
static void
1124 
init_tables ()
1125 
{
1126 
}
1127 
 
1128 
static const CGEN_MACH * lookup_mach_via_bfd_name
1129 
  PARAMS ((const CGEN_MACH *, const char *));
1130 
static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1131 
static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1132 
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1133 
static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1134 
static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1135 
 
1136 
/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1137 
 
1138 
static const CGEN_MACH *
1139 
lookup_mach_via_bfd_name (table, name)
1140 
     const CGEN_MACH *table;
1141 
     const char *name;
1142 
{
1143 
  while (table->name)
1144 
    {
1145 
      if (strcmp (name, table->bfd_name) == 0)
1146 
        return table;
1147 
      ++table;
1148 
    }
1149 
  abort ();
1150 
}
1151 
 
1152 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1153 
 
1154 
static void
1155 
build_hw_table (cd)
1156 
     CGEN_CPU_TABLE *cd;
1157 
{
1158 
  int i;
1159 
  int machs = cd->machs;
1160 
  const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1161 
  /* MAX_HW is only an upper bound on the number of selected entries.
1162 
     However each entry is indexed by it's enum so there can be holes in
1163 
     the table.  */
1164 
  const CGEN_HW_ENTRY **selected =
1165 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1166 
 
1167 
  cd->hw_table.init_entries = init;
1168 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1169 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1170 
  /* ??? For now we just use machs to determine which ones we want.  */
1171 
  for (i = 0; init[i].name != NULL; ++i)
1172 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1173 
        & machs)
1174 
      selected[init[i].type] = &init[i];
1175 
  cd->hw_table.entries = selected;
1176 
  cd->hw_table.num_entries = MAX_HW;
1177 
}
1178 
 
1179 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1180 
 
1181 
static void
1182 
build_ifield_table (cd)
1183 
     CGEN_CPU_TABLE *cd;
1184 
{
1185 
  cd->ifld_table = & m32r_cgen_ifld_table[0];
1186 
}
1187 
 
1188 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1189 
 
1190 
static void
1191 
build_operand_table (cd)
1192 
     CGEN_CPU_TABLE *cd;
1193 
{
1194 
  int i;
1195 
  int machs = cd->machs;
1196 
  const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1197 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1198 
     However each entry is indexed by it's enum so there can be holes in
1199 
     the table.  */
1200 
  const CGEN_OPERAND **selected =
1201 
    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1202 
 
1203 
  cd->operand_table.init_entries = init;
1204 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1205 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1206 
  /* ??? For now we just use mach to determine which ones we want.  */
1207 
  for (i = 0; init[i].name != NULL; ++i)
1208 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1209 
        & machs)
1210 
      selected[init[i].type] = &init[i];
1211 
  cd->operand_table.entries = selected;
1212 
  cd->operand_table.num_entries = MAX_OPERANDS;
1213 
}
1214 
 
1215 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1216 
   ??? This could leave out insns not supported by the specified mach/isa,
1217 
   but that would cause errors like "foo only supported by bar" to become
1218 
   "unknown insn", so for now we include all insns and require the app to
1219 
   do the checking later.
1220 
   ??? On the other hand, parsing of such insns may require their hardware or
1221 
   operand elements to be in the table [which they mightn't be].  */
1222 
 
1223 
static void
1224 
build_insn_table (cd)
1225 
     CGEN_CPU_TABLE *cd;
1226 
{
1227 
  int i;
1228 
  const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1229 
  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1230 
 
1231 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1232 
  for (i = 0; i < MAX_INSNS; ++i)
1233 
    insns[i].base = &ib[i];
1234 
  cd->insn_table.init_entries = insns;
1235 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1236 
  cd->insn_table.num_init_entries = MAX_INSNS;
1237 
}
1238 
 
1239 
/* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1240 
 
1241 
static void
1242 
m32r_cgen_rebuild_tables (cd)
1243 
     CGEN_CPU_TABLE *cd;
1244 
{
1245 
  int i;
1246 
  unsigned int isas = cd->isas;
1247 
  unsigned int machs = cd->machs;
1248 
 
1249 
  cd->int_insn_p = CGEN_INT_INSN_P;
1250 
 
1251 
  /* Data derived from the isa spec.  */
1252 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1253 
  cd->default_insn_bitsize = UNSET;
1254 
  cd->base_insn_bitsize = UNSET;
1255 
  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1256 
  cd->max_insn_bitsize = 0;
1257 
  for (i = 0; i < MAX_ISAS; ++i)
1258 
    if (((1 << i) & isas) != 0)
1259 
      {
1260 
        const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1261 
 
1262 
        /* Default insn sizes of all selected isas must be
1263 
           equal or we set the result to 0, meaning "unknown".  */
1264 
        if (cd->default_insn_bitsize == UNSET)
1265 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1266 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1267 
          ; /* this is ok */
1268 
        else
1269 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1270 
 
1271 
        /* Base insn sizes of all selected isas must be equal
1272 
           or we set the result to 0, meaning "unknown".  */
1273 
        if (cd->base_insn_bitsize == UNSET)
1274 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1275 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1276 
          ; /* this is ok */
1277 
        else
1278 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1279 
 
1280 
        /* Set min,max insn sizes.  */
1281 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1282 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1283 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1284 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1285 
      }
1286 
 
1287 
  /* Data derived from the mach spec.  */
1288 
  for (i = 0; i < MAX_MACHS; ++i)
1289 
    if (((1 << i) & machs) != 0)
1290 
      {
1291 
        const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1292 
 
1293 
        if (mach->insn_chunk_bitsize != 0)
1294 
        {
1295 
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1296 
            {
1297 
              fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1298 
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1299 
              abort ();
1300 
            }
1301 
 
1302 
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1303 
        }
1304 
      }
1305 
 
1306 
  /* Determine which hw elements are used by MACH.  */
1307 
  build_hw_table (cd);
1308 
 
1309 
  /* Build the ifield table.  */
1310 
  build_ifield_table (cd);
1311 
 
1312 
  /* Determine which operands are used by MACH/ISA.  */
1313 
  build_operand_table (cd);
1314 
 
1315 
  /* Build the instruction table.  */
1316 
  build_insn_table (cd);
1317 
}
1318 
 
1319 
/* Initialize a cpu table and return a descriptor.
1320 
   It's much like opening a file, and must be the first function called.
1321 
   The arguments are a set of (type/value) pairs, terminated with
1322 
   CGEN_CPU_OPEN_END.
1323 
 
1324 
   Currently supported values:
1325 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1326 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1327 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1328 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1329 
   CGEN_CPU_OPEN_END:     terminates arguments
1330 
 
1331 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1332 
   precluded.
1333 
 
1334 
   ??? We only support ISO C stdargs here, not K&R.
1335 
   Laziness, plus experiment to see if anything requires K&R - eventually
1336 
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1337 
 
1338 
CGEN_CPU_DESC
1339 
m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1340 
{
1341 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1342 
  static int init_p;
1343 
  unsigned int isas = 0;  /* 0 = "unspecified" */
1344 
  unsigned int machs = 0; /* 0 = "unspecified" */
1345 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1346 
  va_list ap;
1347 
 
1348 
  if (! init_p)
1349 
    {
1350 
      init_tables ();
1351 
      init_p = 1;
1352 
    }
1353 
 
1354 
  memset (cd, 0, sizeof (*cd));
1355 
 
1356 
  va_start (ap, arg_type);
1357 
  while (arg_type != CGEN_CPU_OPEN_END)
1358 
    {
1359 
      switch (arg_type)
1360 
        {
1361 
        case CGEN_CPU_OPEN_ISAS :
1362 
          isas = va_arg (ap, unsigned int);
1363 
          break;
1364 
        case CGEN_CPU_OPEN_MACHS :
1365 
          machs = va_arg (ap, unsigned int);
1366 
          break;
1367 
        case CGEN_CPU_OPEN_BFDMACH :
1368 
          {
1369 
            const char *name = va_arg (ap, const char *);
1370 
            const CGEN_MACH *mach =
1371 
              lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1372 
 
1373 
            machs |= 1 << mach->num;
1374 
            break;
1375 
          }
1376 
        case CGEN_CPU_OPEN_ENDIAN :
1377 
          endian = va_arg (ap, enum cgen_endian);
1378 
          break;
1379 
        default :
1380 
          fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1381 
                   arg_type);
1382 
          abort (); /* ??? return NULL? */
1383 
        }
1384 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1385 
    }
1386 
  va_end (ap);
1387 
 
1388 
  /* mach unspecified means "all" */
1389 
  if (machs == 0)
1390 
    machs = (1 << MAX_MACHS) - 1;
1391 
  /* base mach is always selected */
1392 
  machs |= 1;
1393 
  /* isa unspecified means "all" */
1394 
  if (isas == 0)
1395 
    isas = (1 << MAX_ISAS) - 1;
1396 
  if (endian == CGEN_ENDIAN_UNKNOWN)
1397 
    {
1398 
      /* ??? If target has only one, could have a default.  */
1399 
      fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1400 
      abort ();
1401 
    }
1402 
 
1403 
  cd->isas = isas;
1404 
  cd->machs = machs;
1405 
  cd->endian = endian;
1406 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
1407 
     The worry here is where both data and insn endian can be independently
1408 
     chosen, in which case this function will need another argument.
1409 
     Actually, will want to allow for more arguments in the future anyway.  */
1410 
  cd->insn_endian = endian;
1411 
 
1412 
  /* Table (re)builder.  */
1413 
  cd->rebuild_tables = m32r_cgen_rebuild_tables;
1414 
  m32r_cgen_rebuild_tables (cd);
1415 
 
1416 
  /* Default to not allowing signed overflow.  */
1417 
  cd->signed_overflow_ok_p = 0;
1418 
 
1419 
  return (CGEN_CPU_DESC) cd;
1420 
}
1421 
 
1422 
/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1423 
   MACH_NAME is the bfd name of the mach.  */
1424 
 
1425 
CGEN_CPU_DESC
1426 
m32r_cgen_cpu_open_1 (mach_name, endian)
1427 
     const char *mach_name;
1428 
     enum cgen_endian endian;
1429 
{
1430 
  return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1431 
                               CGEN_CPU_OPEN_ENDIAN, endian,
1432 
                               CGEN_CPU_OPEN_END);
1433 
}
1434 
 
1435 
/* Close a cpu table.
1436 
   ??? This can live in a machine independent file, but there's currently
1437 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1438 
   place as some simulator ports use this but they don't use libopcodes.  */
1439 
 
1440 
void
1441 
m32r_cgen_cpu_close (cd)
1442 
     CGEN_CPU_DESC cd;
1443 
{
1444 
  unsigned int i;
1445 
  CGEN_INSN *insns;
1446 
 
1447 
  if (cd->macro_insn_table.init_entries)
1448 
    {
1449 
      insns = cd->macro_insn_table.init_entries;
1450 
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1451 
        {
1452 
          if (CGEN_INSN_RX ((insns)))
1453 
            regfree(CGEN_INSN_RX (insns));
1454 
        }
1455 
    }
1456 
 
1457 
  if (cd->insn_table.init_entries)
1458 
    {
1459 
      insns = cd->insn_table.init_entries;
1460 
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1461 
        {
1462 
          if (CGEN_INSN_RX (insns))
1463 
            regfree(CGEN_INSN_RX (insns));
1464 
        }
1465 
    }
1466 
 
1467 
 
1468 
 
1469 
  if (cd->macro_insn_table.init_entries)
1470 
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1471 
 
1472 
  if (cd->insn_table.init_entries)
1473 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
1474 
 
1475 
  if (cd->hw_table.entries)
1476 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1477 
 
1478 
  if (cd->operand_table.entries)
1479 
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1480 
 
1481 
  free (cd);
1482 
}
1483 
 

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