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1181 |
sfurman |
/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/ppc.h"
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/* This file provides several disassembler functions, all of which use
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the disassembler interface defined in dis-asm.h. Several functions
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
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int bigendian, int dialect));
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static int powerpc_dialect PARAMS ((struct disassemble_info *));
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/* Determine which set of machines to disassemble for. PPC403/601 or
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BookE. For convenience, also disassemble instructions supported
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by the AltiVec vector unit. */
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int
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powerpc_dialect(info)
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struct disassemble_info *info;
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{
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int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
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if (BFD_DEFAULT_TARGET_SIZE == 64)
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dialect |= PPC_OPCODE_64;
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if (info->disassembler_options
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&& (strcmp (info->disassembler_options, "booke") == 0
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|| strcmp (info->disassembler_options, "booke32") == 0
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|| strcmp (info->disassembler_options, "booke64") == 0))
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
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else
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if ((info->mach == bfd_mach_ppc_e500)
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|| (info->disassembler_options
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&& ( strcmp (info->disassembler_options, "e500") == 0
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|| strcmp (info->disassembler_options, "e500x2") == 0)))
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{
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dialect |= PPC_OPCODE_BOOKE
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| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
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| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_RFMCI;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else
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if (info->disassembler_options
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&& (strcmp (info->disassembler_options, "efs") == 0))
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{
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dialect |= PPC_OPCODE_EFS;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else
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dialect |= PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_COMMON;
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if (info->disassembler_options
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&& strcmp (info->disassembler_options, "power4") == 0)
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dialect |= PPC_OPCODE_POWER4;
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if (info->disassembler_options)
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{
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if (strstr (info->disassembler_options, "32") != NULL)
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dialect &= ~PPC_OPCODE_64;
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else if (strstr (info->disassembler_options, "64") != NULL)
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dialect |= PPC_OPCODE_64;
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}
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return dialect;
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}
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/* Print a big endian PowerPC instruction. */
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int
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print_insn_big_powerpc (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
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}
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/* Print a little endian PowerPC instruction. */
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int
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print_insn_little_powerpc (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
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}
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/* Print a POWER (RS/6000) instruction. */
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int
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print_insn_rs6000 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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}
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/* Print a PowerPC or POWER instruction. */
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static int
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print_insn_powerpc (memaddr, info, bigendian, dialect)
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bfd_vma memaddr;
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struct disassemble_info *info;
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int bigendian;
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int dialect;
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{
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bfd_byte buffer[4];
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int status;
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unsigned long insn;
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const struct powerpc_opcode *opcode;
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const struct powerpc_opcode *opcode_end;
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unsigned long op;
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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if (bigendian)
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insn = bfd_getb32 (buffer);
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else
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insn = bfd_getl32 (buffer);
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/* Get the major opcode of the instruction. */
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op = PPC_OP (insn);
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/* Find the first match in the opcode table. We could speed this up
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a bit by doing a binary search on the major opcode. */
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opcode_end = powerpc_opcodes + powerpc_num_opcodes;
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for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
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{
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unsigned long table_op;
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const unsigned char *opindex;
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const struct powerpc_operand *operand;
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int invalid;
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int need_comma;
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int need_paren;
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table_op = PPC_OP (opcode->opcode);
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if (op < table_op)
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break;
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if (op > table_op)
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continue;
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if ((insn & opcode->mask) != opcode->opcode
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|| (opcode->flags & dialect) == 0)
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continue;
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if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
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continue;
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/* Make two passes over the operands. First see if any of them
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have extraction functions, and, if they do, make sure the
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instruction is valid. */
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invalid = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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operand = powerpc_operands + *opindex;
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if (operand->extract)
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(*operand->extract) (insn, dialect, &invalid);
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}
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if (invalid)
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continue;
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/* The instruction is valid. */
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "\t");
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/* Now extract and print the operands. */
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need_comma = 0;
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need_paren = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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long value;
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operand = powerpc_operands + *opindex;
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/* Operands that are marked FAKE are simply ignored. We
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already made sure that the extract function considered
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the instruction to be valid. */
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if ((operand->flags & PPC_OPERAND_FAKE) != 0)
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continue;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, dialect, (int *) NULL);
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else
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{
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0
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&& (value & (1 << (operand->bits - 1))) != 0)
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value -= 1 << operand->bits;
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}
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/* If the operand is optional, and the value is zero, don't
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print anything. */
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& (operand->flags & PPC_OPERAND_NEXT) == 0
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&& value == 0)
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continue;
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if (need_comma)
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{
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(*info->fprintf_func) (info->stream, ",");
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need_comma = 0;
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}
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/* Print the operand as directed by the flags. */
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if ((operand->flags & PPC_OPERAND_GPR) != 0)
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(*info->fprintf_func) (info->stream, "r%ld", value);
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else if ((operand->flags & PPC_OPERAND_FPR) != 0)
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(*info->fprintf_func) (info->stream, "f%ld", value);
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else if ((operand->flags & PPC_OPERAND_VR) != 0)
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(*info->fprintf_func) (info->stream, "v%ld", value);
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else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
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(*info->print_address_func) (memaddr + value, info);
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else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
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(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
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else if ((operand->flags & PPC_OPERAND_CR) == 0
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|| (dialect & PPC_OPCODE_PPC) == 0)
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(*info->fprintf_func) (info->stream, "%ld", value);
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else
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{
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if (operand->bits == 3)
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(*info->fprintf_func) (info->stream, "cr%d", value);
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else
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{
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static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
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int cr;
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int cc;
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cr = value >> 2;
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if (cr != 0)
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(*info->fprintf_func) (info->stream, "4*cr%d", cr);
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cc = value & 3;
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if (cc != 0)
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{
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if (cr != 0)
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(*info->fprintf_func) (info->stream, "+");
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(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
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}
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}
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}
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if (need_paren)
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{
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(*info->fprintf_func) (info->stream, ")");
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need_paren = 0;
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| 279 |
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}
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| 280 |
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| 281 |
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if ((operand->flags & PPC_OPERAND_PARENS) == 0)
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need_comma = 1;
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| 283 |
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else
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| 284 |
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{
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| 285 |
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(*info->fprintf_func) (info->stream, "(");
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| 286 |
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need_paren = 1;
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| 287 |
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}
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| 288 |
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}
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| 289 |
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| 290 |
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/* We have found and printed an instruction; return. */
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| 291 |
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return 4;
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| 292 |
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}
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| 293 |
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| 294 |
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/* We could not find a match. */
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| 295 |
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(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
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| 296 |
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| 297 |
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return 4;
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| 298 |
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}
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