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/* ppc-opc.c -- PowerPC opcode list

   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002

   Free Software Foundation, Inc.

   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute

them and/or modify them under the terms of the GNU General Public

License as published by the Free Software Foundation; either version

2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they

will be useful, but WITHOUT ANY WARRANTY; without even the implied

warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

the GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this file; see the file COPYING.  If not, write to the Free

Software Foundation, 59 Temple Place - Suite 330, Boston, MA

02111-1307, USA.  */

#include <stdio.h>

#include "sysdep.h"

#include "opcode/ppc.h"

#include "opintl.h"

/* This file holds the PowerPC opcode table.  The opcode table

   includes almost all of the extended instruction mnemonics.  This

   permits the disassembler to use them, and simplifies the assembler

   logic, at the cost of increasing the table size.  The table is

   strictly constant data, so the compiler should be able to put it in

   the .text section.

   This file also holds the operand table.  All knowledge about

   inserting operands into instructions and vice-versa is kept in this

   file.  */

/* Local insertion and extraction functions.  */

static unsigned long insert_bat

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bat

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_bba

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bba

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_bd

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bd

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_bdm

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bdm

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_bdp

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bdp

  PARAMS ((unsigned long, int, int *));

static int valid_bo

  PARAMS ((long, int));

static unsigned long insert_bo

  PARAMS ((unsigned long, long, int, const char **));

static long extract_bo

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_boe

  PARAMS ((unsigned long, long, int, const char **));

static long extract_boe

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_ds

  PARAMS ((unsigned long, long, int, const char **));

static long extract_ds

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_de

  PARAMS ((unsigned long, long, int, const char **));

static long extract_de

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_des

  PARAMS ((unsigned long, long, int, const char **));

static long extract_des

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_li

  PARAMS ((unsigned long, long, int, const char **));

static long extract_li

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_mbe

  PARAMS ((unsigned long, long, int, const char **));

static long extract_mbe

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_mb6

  PARAMS ((unsigned long, long, int, const char **));

static long extract_mb6

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_nb

  PARAMS ((unsigned long, long, int, const char **));

static long extract_nb

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_nsi

  PARAMS ((unsigned long, long, int, const char **));

static long extract_nsi

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_pmrn

  PARAMS ((unsigned long, long, int, const char **));

static long extract_pmrn

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_ral

  PARAMS ((unsigned long, long, int, const char **));

static unsigned long insert_ram

  PARAMS ((unsigned long, long, int, const char **));

static unsigned long insert_ras

  PARAMS ((unsigned long, long, int, const char **));

static unsigned long insert_rbs

  PARAMS ((unsigned long, long, int, const char **));

static long extract_rbs

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_sh6

  PARAMS ((unsigned long, long, int, const char **));

static long extract_sh6

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_spr

  PARAMS ((unsigned long, long, int, const char **));

static long extract_spr

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_tbr

  PARAMS ((unsigned long, long, int, const char **));

static long extract_tbr

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_ev2

  PARAMS ((unsigned long, long, int, const char **));

static long extract_ev2

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_ev4

  PARAMS ((unsigned long, long, int, const char **));

static long extract_ev4

  PARAMS ((unsigned long, int, int *));

static unsigned long insert_ev8

  PARAMS ((unsigned long, long, int, const char **));

static long extract_ev8

  PARAMS ((unsigned long, int, int *));

/* The operands table.

   The fields are bits, shift, insert, extract, flags.

   We used to put parens around the various additions, like the one

   for BA just below.  However, that caused trouble with feeble

   compilers with a limit on depth of a parenthesized expression, like

   (reportedly) the compiler in Microsoft Developer Studio 5.  So we

   omit the parens, since the macros are never used in a context where

   the addition will be ambiguous.  */

const struct powerpc_operand powerpc_operands[] =

{

  /* The zero index is used to indicate the end of the list of

     operands.  */

#define UNUSED 0

  { 0, 0, 0, 0, 0 },

  /* The BA field in an XL form instruction.  */

#define BA UNUSED + 1

#define BA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_CR },

  /* The BA field in an XL form instruction when it must be the same

     as the BT field in the same instruction.  */

#define BAT BA + 1

  { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

  /* The BB field in an XL form instruction.  */

#define BB BAT + 1

#define BB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_CR },

  /* The BB field in an XL form instruction when it must be the same

     as the BA field in the same instruction.  */

#define BBA BB + 1

  { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

  /* The BD field in a B form instruction.  The lower two bits are

     forced to zero.  */

#define BD BBA + 1

  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when absolute addressing is

     used.  */

#define BDA BD + 1

  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDM BDA + 1

  { 16, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used

     and absolute address is used.  */

#define BDMA BDM + 1

  { 16, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDP BDMA + 1

  { 16, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used

     and absolute addressing is used.  */

#define BDPA BDP + 1

  { 16, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BF field in an X or XL form instruction.  */

#define BF BDPA + 1

  { 3, 23, 0, 0, PPC_OPERAND_CR },

  /* An optional BF field.  This is used for comparison instructions,

     in which an omitted BF field is taken as zero.  */

#define OBF BF + 1

  { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The BFA field in an X or XL form instruction.  */

#define BFA OBF + 1

  { 3, 18, 0, 0, PPC_OPERAND_CR },

  /* The BI field in a B form or XL form instruction.  */

#define BI BFA + 1

#define BI_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_CR },

  /* The BO field in a B form instruction.  Certain values are

     illegal.  */

#define BO BI + 1

#define BO_MASK (0x1f << 21)

  { 5, 21, insert_bo, extract_bo, 0 },

  /* The BO field in a B form instruction when the + or - modifier is

     used.  This is like the BO field, but it must be even.  */

#define BOE BO + 1

  { 5, 21, insert_boe, extract_boe, 0 },

  /* The BT field in an X or XL form instruction.  */

#define BT BOE + 1

  { 5, 21, 0, 0, PPC_OPERAND_CR },

  /* The condition register number portion of the BI field in a B form

     or XL form instruction.  This is used for the extended

     conditional branch mnemonics, which set the lower two bits of the

     BI field.  This field is optional.  */

#define CR BT + 1

  { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The CRB field in an X form instruction.  */

#define CRB CR + 1

  { 5, 6, 0, 0, 0 },

  /* The CRFD field in an X form instruction.  */

#define CRFD CRB + 1

  { 3, 23, 0, 0, 0 },

  /* The CRFS field in an X form instruction.  */

#define CRFS CRFD + 1

  { 3, 0, 0, 0, 0 },

  /* The CT field in an X form instruction.  */

#define CT CRFS + 1

#define RD CT

  { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },

  /* The D field in a D form instruction.  This is a displacement off

     a register, and implies that the next operand is a register in

     parentheses.  */

#define D CT + 1

  { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DE field in a DE form instruction.  This is like D, but is 12

     bits only.  */

#define DE D + 1

  { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },

  /* The DES field in a DES form instruction.  This is like DS, but is 14

     bits only (12 stored.)  */

#define DES DE + 1

  { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DS field in a DS form instruction.  This is like D, but the

     lower two bits are forced to zero.  */

#define DS DES + 1

  { 16, 0, insert_ds, extract_ds,

      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },

  /* The E field in a wrteei instruction.  */

#define E DS + 1

  { 1, 15, 0, 0, 0 },

  /* The FL1 field in a POWER SC form instruction.  */

#define FL1 E + 1

  { 4, 12, 0, 0, 0 },

  /* The FL2 field in a POWER SC form instruction.  */

#define FL2 FL1 + 1

  { 3, 2, 0, 0, 0 },

  /* The FLM field in an XFL form instruction.  */

#define FLM FL2 + 1

  { 8, 17, 0, 0, 0 },

  /* The FRA field in an X or A form instruction.  */

#define FRA FLM + 1

#define FRA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_FPR },

  /* The FRB field in an X or A form instruction.  */

#define FRB FRA + 1

#define FRB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_FPR },

  /* The FRC field in an A form instruction.  */

#define FRC FRB + 1

#define FRC_MASK (0x1f << 6)

  { 5, 6, 0, 0, PPC_OPERAND_FPR },

  /* The FRS field in an X form instruction or the FRT field in a D, X

     or A form instruction.  */

#define FRS FRC + 1

#define FRT FRS

  { 5, 21, 0, 0, PPC_OPERAND_FPR },

  /* The FXM field in an XFX instruction.  */

#define FXM FRS + 1

#define FXM_MASK (0xff << 12)

  { 8, 12, 0, 0, 0 },

  /* The L field in a D or X form instruction.  */

#define L FXM + 1

  { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },

  /* The LEV field in a POWER SC form instruction.  */

#define LEV L + 1

  { 7, 5, 0, 0, 0 },

  /* The LI field in an I form instruction.  The lower two bits are

     forced to zero.  */

#define LI LEV + 1

  { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The LI field in an I form instruction when used as an absolute

     address.  */

#define LIA LI + 1

  { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The LS field in an X (sync) form instruction.  */

#define LS LIA + 1

  { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },

  /* The MB field in an M form instruction.  */

#define MB LS + 1

#define MB_MASK (0x1f << 6)

  { 5, 6, 0, 0, 0 },

  /* The ME field in an M form instruction.  */

#define ME MB + 1

#define ME_MASK (0x1f << 1)

  { 5, 1, 0, 0, 0 },

  /* The MB and ME fields in an M form instruction expressed a single

     operand which is a bitmask indicating which bits to select.  This

     is a two operand form using PPC_OPERAND_NEXT.  See the

     description in opcode/ppc.h for what this means.  */

#define MBE ME + 1

  { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },

  { 32, 0, insert_mbe, extract_mbe, 0 },

  /* The MB or ME field in an MD or MDS form instruction.  The high

     bit is wrapped to the low end.  */

#define MB6 MBE + 2

#define ME6 MB6

#define MB6_MASK (0x3f << 5)

  { 6, 5, insert_mb6, extract_mb6, 0 },

  /* The MO field in an mbar instruction.  */

#define MO MB6 + 1

  { 5, 21, 0, 0, 0 },

  /* The NB field in an X form instruction.  The value 32 is stored as

     0.  */

#define NB MO + 1

  { 6, 11, insert_nb, extract_nb, 0 },

  /* The NSI field in a D form instruction.  This is the same as the

     SI field, only negated.  */

#define NSI NB + 1

  { 16, 0, insert_nsi, extract_nsi,

      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The PMRN field in an X form instruction.  */

#define PMRN NSI + 1

  { 16, 0, insert_pmrn, extract_pmrn, PPC_OPERAND_GPR },

  /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */

#define RA PMRN + 1

#define RA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_GPR },

  /* The RA field in a D or X form instruction which is an updating

     load, which means that the RA field may not be zero and may not

     equal the RT field.  */

#define RAL RA + 1

  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },

  /* The RA field in an lmw instruction, which has special value

     restrictions.  */

#define RAM RAL + 1

  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },

  /* The RA field in a D or X form instruction which is an updating

     store or an updating floating point load, which means that the RA

     field may not be zero.  */

#define RAS RAM + 1

  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },

  /* The RB field in an X, XO, M, or MDS form instruction.  */

#define RB RAS + 1

#define RB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_GPR },

  /* The RB field in an X form instruction when it must be the same as

     the RS field in the instruction.  This is used for extended

     mnemonics like mr.  */

#define RBS RB + 1

  { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form

     instruction or the RT field in a D, DS, X, XFX or XO form

     instruction.  */

#define RS RBS + 1

#define RT RS

#define RT_MASK (0x1f << 21)

  { 5, 21, 0, 0, PPC_OPERAND_GPR },

  /* The SH field in an X or M form instruction.  */

#define SH RS + 1

#define SH_MASK (0x1f << 11)

  { 5, 11, 0, 0, 0 },

  /* The SH field in an MD form instruction.  This is split.  */

#define SH6 SH + 1

#define SH6_MASK ((0x1f << 11) | (1 << 1))

  { 6, 1, insert_sh6, extract_sh6, 0 },

  /* The SI field in a D form instruction.  */

#define SI SH6 + 1

  { 16, 0, 0, 0, PPC_OPERAND_SIGNED },

  /* The SI field in a D form instruction when we accept a wide range

     of positive values.  */

#define SISIGNOPT SI + 1

  { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The SPR field in an XFX form instruction.  This is flipped--the

     lower 5 bits are stored in the upper 5 and vice- versa.  */

#define SPR SISIGNOPT + 1

#define SPR_MASK (0x3ff << 11)

  { 10, 11, insert_spr, extract_spr, 0 },

  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */

#define SPRBAT SPR + 1

#define SPRBAT_MASK (0x3 << 17)

  { 2, 17, 0, 0, 0 },

  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */

#define SPRG SPRBAT + 1

#define SPRG_MASK (0x3 << 16)

  { 2, 16, 0, 0, 0 },

  /* The SR field in an X form instruction.  */

#define SR SPRG + 1

  { 4, 16, 0, 0, 0 },

  /* The STRM field in an X AltiVec form instruction.  */

#define STRM SR + 1

#define STRM_MASK (0x3 << 21)

  { 2, 21, 0, 0, 0 },

  /* The SV field in a POWER SC form instruction.  */

#define SV STRM + 1

  { 14, 2, 0, 0, 0 },

  /* The TBR field in an XFX form instruction.  This is like the SPR

     field, but it is optional.  */

#define TBR SV + 1

  { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },

  /* The TO field in a D or X form instruction.  */

#define TO TBR + 1

#define TO_MASK (0x1f << 21)

  { 5, 21, 0, 0, 0 },

  /* The U field in an X form instruction.  */

#define U TO + 1

  { 4, 12, 0, 0, 0 },

  /* The UI field in a D form instruction.  */

#define UI U + 1

  { 16, 0, 0, 0, 0 },

  /* The VA field in a VA, VX or VXR form instruction. */

#define VA UI + 1

#define VA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_VR },

  /* The VB field in a VA, VX or VXR form instruction. */

#define VB VA + 1

#define VB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_VR },

  /* The VC field in a VA form instruction. */

#define VC VB + 1

#define VC_MASK (0x1f << 6)

  { 5, 6, 0, 0, PPC_OPERAND_VR },

  /* The VD or VS field in a VA, VX, VXR or X form instruction. */

#define VD VC + 1

#define VS VD

#define VD_MASK (0x1f << 21)

  { 5, 21, 0, 0, PPC_OPERAND_VR },

  /* The SIMM field in a VX form instruction. */

#define SIMM VD + 1

  { 5, 16, 0, 0, PPC_OPERAND_SIGNED},

  /* The UIMM field in a VX form instruction. */

#define UIMM SIMM + 1

  { 5, 16, 0, 0, 0 },

  /* The SHB field in a VA form instruction. */

#define SHB UIMM + 1

  { 4, 6, 0, 0, 0 },

  /* The other UIMM field in a EVX form instruction. */

#define EVUIMM SHB + 1

  { 5, 11, 0, 0, 0 },

  /* The other UIMM field in a half word EVX form instruction. */

#define EVUIMM_2 EVUIMM + 1

  { 5, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },

  /* The other UIMM field in a word EVX form instruction. */

#define EVUIMM_4 EVUIMM_2 + 1

  { 5, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },

  /* The other UIMM field in a double EVX form instruction. */

#define EVUIMM_8 EVUIMM_4 + 1

  { 8, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },

  /* The WS field.  */

#define WS EVUIMM_8 + 1

#define WS_MASK (0x7 << 11)

  { 3, 11, 0, 0, 0 },

  /* The L field in an mtmsrd instruction */

#define MTMSRD_L WS + 1

  { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },

};

/* The functions used to insert and extract complicated operands.  */

/* The BA field in an XL form instruction when it must be the same as

   the BT field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BT field into the BA field,

   and the extraction function just checks that the fields are the

   same.  */

/*ARGSUSED*/

static unsigned long

insert_bat (insn, value, dialect, errmsg)

     unsigned long insn;

     long value ATTRIBUTE_UNUSED;

     int dialect ATTRIBUTE_UNUSED;

     const char **errmsg ATTRIBUTE_UNUSED;

{

  return insn | (((insn >> 21) & 0x1f) << 16);

}

static long

extract_bat (insn, dialect, invalid)

     unsigned long insn;

     int dialect ATTRIBUTE_UNUSED;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BB field in an XL form instruction when it must be the same as

   the BA field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BA field into the BB field,

   and the extraction function just checks that the fields are the

   same.  */

/*ARGSUSED*/

static unsigned long

insert_bba (insn, value, dialect, errmsg)

     unsigned long insn;

     long value ATTRIBUTE_UNUSED;

     int dialect ATTRIBUTE_UNUSED;

     const char **errmsg ATTRIBUTE_UNUSED;

{

  return insn | (((insn >> 16) & 0x1f) << 11);

}

static long

extract_bba (insn, dialect, invalid)

     unsigned long insn;

     int dialect ATTRIBUTE_UNUSED;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BD field in a B form instruction.  The lower two bits are

   forced to zero.  */

/*ARGSUSED*/

static unsigned long

insert_bd (insn, value, dialect, errmsg)

     unsigned long insn;

     long value;

     int dialect ATTRIBUTE_UNUSED;