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1181 |
sfurman |
/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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extern ARMword isize;
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/* Condition code values. */
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#define EQ 0
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#define NE 1
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#define CS 2
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#define CC 3
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#define MI 4
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#define PL 5
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#define VS 6
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#define VC 7
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#define HI 8
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#define LS 9
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#define GE 10
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#define LT 11
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#define GT 12
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#define LE 13
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#define AL 14
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#define NV 15
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/* Shift Opcodes. */
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#define LSL 0
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#define LSR 1
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#define ASR 2
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#define ROR 3
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/* Macros to twiddle the status flags and mode. */
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#define NBIT ((unsigned)1L << 31)
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#define ZBIT (1L << 30)
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#define CBIT (1L << 29)
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#define VBIT (1L << 28)
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#define SBIT (1L << 27)
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#define IBIT (1L << 7)
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#define FBIT (1L << 6)
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#define IFBITS (3L << 6)
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#define R15IBIT (1L << 27)
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#define R15FBIT (1L << 26)
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#define R15IFBITS (3L << 26)
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#define POS(i) ( (~(i)) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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#ifdef MODET /* Thumb support. */
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/* ??? This bit is actually in the low order bit of the PC in the hardware.
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It isn't clear if the simulator needs to model that or not. */
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#define TBIT (1L << 5)
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#define TFLAG state->TFlag
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#define SETT state->TFlag = 1
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#define CLEART state->TFlag = 0
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#define ASSIGNT(res) state->TFlag = res
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#define INSN_SIZE (TFLAG ? 2 : 4)
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#else
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#define INSN_SIZE 4
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#endif
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#define NFLAG state->NFlag
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#define SETN state->NFlag = 1
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#define CLEARN state->NFlag = 0
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#define ASSIGNN(res) state->NFlag = res
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#define ZFLAG state->ZFlag
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#define SETZ state->ZFlag = 1
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#define CLEARZ state->ZFlag = 0
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#define ASSIGNZ(res) state->ZFlag = res
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#define CFLAG state->CFlag
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#define SETC state->CFlag = 1
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#define CLEARC state->CFlag = 0
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#define ASSIGNC(res) state->CFlag = res
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#define VFLAG state->VFlag
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#define SETV state->VFlag = 1
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#define CLEARV state->VFlag = 0
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#define ASSIGNV(res) state->VFlag = res
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#define SFLAG state->SFlag
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#define SETS state->SFlag = 1
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#define CLEARS state->SFlag = 0
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#define ASSIGNS(res) state->SFlag = res
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#define IFLAG (state->IFFlags >> 1)
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#define FFLAG (state->IFFlags & 1)
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#define IFFLAGS state->IFFlags
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#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
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#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
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#define PSR_FBITS (0xff000000L)
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#define PSR_SBITS (0x00ff0000L)
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#define PSR_XBITS (0x0000ff00L)
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#define PSR_CBITS (0x000000ffL)
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#if defined MODE32 || defined MODET
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#define CCBITS (0xf8000000L)
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#else
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#define CCBITS (0xf0000000L)
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#endif
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#define INTBITS (0xc0L)
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#if defined MODET && defined MODE32
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#define PCBITS (0xffffffffL)
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#else
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#define PCBITS (0xfffffffcL)
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#endif
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#define MODEBITS (0x1fL)
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#define R15INTBITS (3L << 26)
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#if defined MODET && defined MODE32
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#define R15PCBITS (0x03ffffffL)
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#else
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#define R15PCBITS (0x03fffffcL)
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#endif
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#define R15PCMODEBITS (0x03ffffffL)
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#define R15MODEBITS (0x3L)
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#ifdef MODE32
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#define PCMASK PCBITS
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#define PCWRAP(pc) (pc)
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#else
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#define PCMASK R15PCBITS
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#define PCWRAP(pc) ((pc) & R15PCBITS)
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#endif
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#define PC (state->Reg[15] & PCMASK)
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#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
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#define R15INT (state->Reg[15] & R15INTBITS)
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#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
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#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
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#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
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#define R15PC (state->Reg[15] & R15PCBITS)
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#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
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#define R15MODE (state->Reg[15] & R15MODEBITS)
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#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
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#define EINT (IFFLAGS << 6)
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#define ER15INT (IFFLAGS << 26)
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#define EMODE (state->Mode)
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#ifdef MODET
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#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
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#else
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#define CPSR (ECC | EINT | EMODE)
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#endif
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#ifdef MODE32
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#define PATCHR15
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#else
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#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
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#endif
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#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
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#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
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#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
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#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
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#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
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#define SETR15PSR(s) \
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do \
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{ \
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if (state->Mode == USER26MODE) \
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{ \
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state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \
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ASSIGNN ((state->Reg[15] & NBIT) != 0); \
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ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
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ASSIGNC ((state->Reg[15] & CBIT) != 0); \
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ASSIGNV ((state->Reg[15] & VBIT) != 0); \
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} \
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else \
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{ \
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state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \
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ARMul_R15Altered (state); \
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} \
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} \
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while (0)
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#define SETABORT(i, m, d) \
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do \
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{ \
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int SETABORT_mode = (m); \
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\
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ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
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ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
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| (i) | SETABORT_mode)); \
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state->Reg[14] = temp - (d); \
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} \
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while (0)
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#ifndef MODE32
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#define VECTORS 0x20
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#define LEGALADDR 0x03ffffff
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#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
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#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
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#endif
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#define INTERNALABORT(address) \
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do \
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{ \
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if (address < VECTORS) \
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state->Aborted = ARMul_DataAbortV; \
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else \
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state->Aborted = ARMul_AddrExceptnV; \
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} \
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while (0)
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#ifdef MODE32
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#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
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#else
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#define TAKEABORT \
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do \
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{ \
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if (state->Aborted == ARMul_AddrExceptnV) \
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ARMul_Abort (state, ARMul_AddrExceptnV); \
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else \
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ARMul_Abort (state, ARMul_DataAbortV); \
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} \
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while (0)
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#endif
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#define CPTAKEABORT \
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do \
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{ \
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if (!state->Aborted) \
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ARMul_Abort (state, ARMul_UndefinedInstrV); \
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else if (state->Aborted == ARMul_AddrExceptnV) \
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ARMul_Abort (state, ARMul_AddrExceptnV); \
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else \
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ARMul_Abort (state, ARMul_DataAbortV); \
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} \
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while (0);
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/* Different ways to start the next instruction. */
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#define SEQ 0
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#define NONSEQ 1
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#define PCINCEDSEQ 2
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#define PCINCEDNONSEQ 3
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#define PRIMEPIPE 4
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#define RESUME 8
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#define NORMALCYCLE state->NextInstr = 0
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#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
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#define BUSUSEDINCPCS \
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do \
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{ \
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if (! state->is_v4) \
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{ \
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/* A standard PC inc and an S cycle. */ \
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state->Reg[15] += isize; \
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state->NextInstr = (state->NextInstr & 0xff) | 2; \
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} \
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} \
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while (0)
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| 273 |
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#define BUSUSEDINCPCN \
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do \
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{ \
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if (state->is_v4) \
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BUSUSEDN; \
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else \
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{ \
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| 280 |
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/* A standard PC inc and an N cycle. */ \
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state->Reg[15] += isize; \
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state->NextInstr |= 3; \
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} \
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} \
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| 285 |
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while (0)
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| 286 |
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| 287 |
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#define INCPC \
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| 288 |
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do \
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{ \
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| 290 |
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/* A standard PC inc. */ \
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state->Reg[15] += isize; \
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state->NextInstr |= 2; \
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} \
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while (0)
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| 295 |
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| 296 |
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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| 298 |
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/* Cycle based emulation. */
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| 300 |
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#define OUTPUTCP(i,a,b)
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#define NCYCLE
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#define SCYCLE
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#define ICYCLE
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| 304 |
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#define CCYCLE
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#define NEXTCYCLE(c)
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| 306 |
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| 307 |
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/* Macros to extract parts of instructions. */
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| 308 |
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#define DESTReg (BITS (12, 15))
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| 309 |
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#define LHSReg (BITS (16, 19))
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| 310 |
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#define RHSReg (BITS ( 0, 3))
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| 312 |
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#define DEST (state->Reg[DESTReg])
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| 314 |
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#ifdef MODE32
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#ifdef MODET
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#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
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#else
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#define LHS (state->Reg[LHSReg])
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#endif
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| 320 |
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#else
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| 321 |
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#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
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#endif
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| 323 |
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| 324 |
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#define MULDESTReg (BITS (16, 19))
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| 325 |
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#define MULLHSReg (BITS ( 0, 3))
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| 326 |
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#define MULRHSReg (BITS ( 8, 11))
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| 327 |
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#define MULACCReg (BITS (12, 15))
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| 328 |
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| 329 |
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#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
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| 330 |
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#define DPSImmRHS temp = BITS(0,11) ; \
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| 331 |
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rhs = ARMul_ImmedTable[temp] ; \
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| 332 |
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if (temp > 255) /* There was a shift. */ \
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| 333 |
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ASSIGNC (rhs >> 31) ;
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| 334 |
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| 335 |
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#ifdef MODE32
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| 336 |
|
|
#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
|
| 337 |
|
|
: GetDPRegRHS (state, instr))
|
| 338 |
|
|
#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
|
| 339 |
|
|
: GetDPSRegRHS (state, instr))
|
| 340 |
|
|
#else
|
| 341 |
|
|
#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
|
| 342 |
|
|
: GetDPRegRHS (state, instr))
|
| 343 |
|
|
#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
|
| 344 |
|
|
: GetDPSRegRHS (state, instr))
|
| 345 |
|
|
#endif
|
| 346 |
|
|
|
| 347 |
|
|
#define LSBase state->Reg[LHSReg]
|
| 348 |
|
|
#define LSImmRHS (BITS(0,11))
|
| 349 |
|
|
|
| 350 |
|
|
#ifdef MODE32
|
| 351 |
|
|
#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
|
| 352 |
|
|
: GetLSRegRHS (state, instr))
|
| 353 |
|
|
#else
|
| 354 |
|
|
#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
|
| 355 |
|
|
: GetLSRegRHS (state, instr))
|
| 356 |
|
|
#endif
|
| 357 |
|
|
|
| 358 |
|
|
#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
|
| 359 |
|
|
(ARMword) ARMul_BitList[BITS (8, 15)] )
|
| 360 |
|
|
#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
|
| 361 |
|
|
(BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
|
| 362 |
|
|
|
| 363 |
|
|
#define SWAPSRC (state->Reg[RHSReg])
|
| 364 |
|
|
|
| 365 |
|
|
#define LSCOff (BITS (0, 7) << 2)
|
| 366 |
|
|
#define CPNum BITS (8, 11)
|
| 367 |
|
|
|
| 368 |
|
|
/* Determine if access to coprocessor CP is permitted.
|
| 369 |
|
|
The XScale has a register in CP15 which controls access to CP0 - CP13. */
|
| 370 |
|
|
#define CP_ACCESS_ALLOWED(STATE, CP) \
|
| 371 |
|
|
( ((CP) >= 14) \
|
| 372 |
|
|
|| (! (STATE)->is_XScale) \
|
| 373 |
|
|
|| (read_cp15_reg (15, 0, 1) & (1 << (CP))))
|
| 374 |
|
|
|
| 375 |
|
|
/* Macro to rotate n right by b bits. */
|
| 376 |
|
|
#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
|
| 377 |
|
|
|
| 378 |
|
|
/* Macros to store results of instructions. */
|
| 379 |
|
|
#define WRITEDEST(d) \
|
| 380 |
|
|
do \
|
| 381 |
|
|
{ \
|
| 382 |
|
|
if (DESTReg == 15) \
|
| 383 |
|
|
WriteR15 (state, d); \
|
| 384 |
|
|
else \
|
| 385 |
|
|
DEST = d; \
|
| 386 |
|
|
} \
|
| 387 |
|
|
while (0)
|
| 388 |
|
|
|
| 389 |
|
|
#define WRITESDEST(d) \
|
| 390 |
|
|
do \
|
| 391 |
|
|
{ \
|
| 392 |
|
|
if (DESTReg == 15) \
|
| 393 |
|
|
WriteSR15 (state, d); \
|
| 394 |
|
|
else \
|
| 395 |
|
|
{ \
|
| 396 |
|
|
DEST = d; \
|
| 397 |
|
|
ARMul_NegZero (state, d); \
|
| 398 |
|
|
} \
|
| 399 |
|
|
} \
|
| 400 |
|
|
while (0)
|
| 401 |
|
|
|
| 402 |
|
|
#define WRITEDESTB(d) \
|
| 403 |
|
|
do \
|
| 404 |
|
|
{ \
|
| 405 |
|
|
if (DESTReg == 15) \
|
| 406 |
|
|
WriteR15Branch (state, d); \
|
| 407 |
|
|
else \
|
| 408 |
|
|
DEST = d; \
|
| 409 |
|
|
} \
|
| 410 |
|
|
while (0)
|
| 411 |
|
|
|
| 412 |
|
|
#define BYTETOBUS(data) ((data & 0xff) | \
|
| 413 |
|
|
((data & 0xff) << 8) | \
|
| 414 |
|
|
((data & 0xff) << 16) | \
|
| 415 |
|
|
((data & 0xff) << 24))
|
| 416 |
|
|
|
| 417 |
|
|
#define BUSTOBYTE(address, data) \
|
| 418 |
|
|
do \
|
| 419 |
|
|
{ \
|
| 420 |
|
|
if (state->bigendSig) \
|
| 421 |
|
|
temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
|
| 422 |
|
|
else \
|
| 423 |
|
|
temp = (data >> ((address & 3) << 3)) & 0xff; \
|
| 424 |
|
|
} \
|
| 425 |
|
|
while (0)
|
| 426 |
|
|
|
| 427 |
|
|
#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
|
| 428 |
|
|
#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
|
| 429 |
|
|
#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
|
| 430 |
|
|
#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
|
| 431 |
|
|
|
| 432 |
|
|
#define POSBRANCH ((instr & 0x7fffff) << 2)
|
| 433 |
|
|
#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
/* Values for Emulate. */
|
| 437 |
|
|
#define STOP 0 /* stop */
|
| 438 |
|
|
#define CHANGEMODE 1 /* change mode */
|
| 439 |
|
|
#define ONCE 2 /* execute just one interation */
|
| 440 |
|
|
#define RUN 3 /* continuous execution */
|
| 441 |
|
|
|
| 442 |
|
|
/* Stuff that is shared across modes. */
|
| 443 |
|
|
extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
|
| 444 |
|
|
extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
|
| 445 |
|
|
extern char ARMul_BitList[]; /* Number of bits in a byte table. */
|
| 446 |
|
|
|
| 447 |
|
|
#define EVENTLISTSIZE 1024L
|
| 448 |
|
|
|
| 449 |
|
|
/* Thumb support. */
|
| 450 |
|
|
typedef enum
|
| 451 |
|
|
{
|
| 452 |
|
|
t_undefined, /* Undefined Thumb instruction. */
|
| 453 |
|
|
t_decoded, /* Instruction decoded to ARM equivalent. */
|
| 454 |
|
|
t_branch /* Thumb branch (already processed). */
|
| 455 |
|
|
}
|
| 456 |
|
|
tdstate;
|
| 457 |
|
|
|
| 458 |
|
|
/* Macros to scrutinize instructions. */
|
| 459 |
|
|
#define UNDEF_Test
|
| 460 |
|
|
#define UNDEF_Shift
|
| 461 |
|
|
#define UNDEF_MSRPC
|
| 462 |
|
|
#define UNDEF_MRSPC
|
| 463 |
|
|
#define UNDEF_MULPCDest
|
| 464 |
|
|
#define UNDEF_MULDestEQOp1
|
| 465 |
|
|
#define UNDEF_LSRBPC
|
| 466 |
|
|
#define UNDEF_LSRBaseEQOffWb
|
| 467 |
|
|
#define UNDEF_LSRBaseEQDestWb
|
| 468 |
|
|
#define UNDEF_LSRPCBaseWb
|
| 469 |
|
|
#define UNDEF_LSRPCOffWb
|
| 470 |
|
|
#define UNDEF_LSMNoRegs
|
| 471 |
|
|
#define UNDEF_LSMPCBase
|
| 472 |
|
|
#define UNDEF_LSMUserBankWb
|
| 473 |
|
|
#define UNDEF_LSMBaseInListWb
|
| 474 |
|
|
#define UNDEF_SWPPC
|
| 475 |
|
|
#define UNDEF_CoProHS
|
| 476 |
|
|
#define UNDEF_MCRPC
|
| 477 |
|
|
#define UNDEF_LSCPCBaseWb
|
| 478 |
|
|
#define UNDEF_UndefNotBounced
|
| 479 |
|
|
#define UNDEF_ShortInt
|
| 480 |
|
|
#define UNDEF_IllegalMode
|
| 481 |
|
|
#define UNDEF_Prog32SigChange
|
| 482 |
|
|
#define UNDEF_Data32SigChange
|
| 483 |
|
|
|
| 484 |
|
|
/* Prototypes for exported functions. */
|
| 485 |
|
|
extern unsigned ARMul_NthReg (ARMword, unsigned);
|
| 486 |
|
|
extern int AddOverflow (ARMword, ARMword, ARMword);
|
| 487 |
|
|
extern int SubOverflow (ARMword, ARMword, ARMword);
|
| 488 |
|
|
extern ARMword ARMul_Emulate26 (ARMul_State *);
|
| 489 |
|
|
extern ARMword ARMul_Emulate32 (ARMul_State *);
|
| 490 |
|
|
extern unsigned IntPending (ARMul_State *);
|
| 491 |
|
|
extern void ARMul_CPSRAltered (ARMul_State *);
|
| 492 |
|
|
extern void ARMul_R15Altered (ARMul_State *);
|
| 493 |
|
|
extern ARMword ARMul_GetPC (ARMul_State *);
|
| 494 |
|
|
extern ARMword ARMul_GetNextPC (ARMul_State *);
|
| 495 |
|
|
extern ARMword ARMul_GetR15 (ARMul_State *);
|
| 496 |
|
|
extern ARMword ARMul_GetCPSR (ARMul_State *);
|
| 497 |
|
|
extern void ARMul_EnvokeEvent (ARMul_State *);
|
| 498 |
|
|
extern unsigned long ARMul_Time (ARMul_State *);
|
| 499 |
|
|
extern void ARMul_NegZero (ARMul_State *, ARMword);
|
| 500 |
|
|
extern void ARMul_SetPC (ARMul_State *, ARMword);
|
| 501 |
|
|
extern void ARMul_SetR15 (ARMul_State *, ARMword);
|
| 502 |
|
|
extern void ARMul_SetCPSR (ARMul_State *, ARMword);
|
| 503 |
|
|
extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
|
| 504 |
|
|
extern void ARMul_Abort26 (ARMul_State *, ARMword);
|
| 505 |
|
|
extern void ARMul_Abort32 (ARMul_State *, ARMword);
|
| 506 |
|
|
extern ARMword ARMul_MRC (ARMul_State *, ARMword);
|
| 507 |
|
|
extern void ARMul_CDP (ARMul_State *, ARMword);
|
| 508 |
|
|
extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
|
| 509 |
|
|
extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
|
| 510 |
|
|
extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
|
| 511 |
|
|
extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
|
| 512 |
|
|
extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
|
| 513 |
|
|
extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
|
| 514 |
|
|
extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
|
| 515 |
|
|
extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
|
| 516 |
|
|
extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
|
| 517 |
|
|
extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
|
| 518 |
|
|
extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
|
| 519 |
|
|
extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
|
| 520 |
|
|
extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
|
| 521 |
|
|
extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
|
| 522 |
|
|
extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
|
| 523 |
|
|
extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *));
|
| 524 |
|
|
/* Coprocessor support functions. */
|
| 525 |
|
|
extern unsigned ARMul_CoProInit (ARMul_State *);
|
| 526 |
|
|
extern void ARMul_CoProExit (ARMul_State *);
|
| 527 |
|
|
extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
|
| 528 |
|
|
ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
|
| 529 |
|
|
ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
|
| 530 |
|
|
extern void ARMul_CoProDetach (ARMul_State *, unsigned);
|
| 531 |
|
|
extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
|
| 532 |
|
|
|
