OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.3/] [sim/] [fr30/] [traps.c] - Blame information for rev 1767

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1181 sfurman
// OBSOLETE /* fr30 exception, interrupt, and trap (EIT) support
2
// OBSOLETE    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
3
// OBSOLETE    Contributed by Cygnus Solutions.
4
// OBSOLETE 
5
// OBSOLETE This file is part of the GNU simulators.
6
// OBSOLETE 
7
// OBSOLETE This program is free software; you can redistribute it and/or modify
8
// OBSOLETE it under the terms of the GNU General Public License as published by
9
// OBSOLETE the Free Software Foundation; either version 2, or (at your option)
10
// OBSOLETE any later version.
11
// OBSOLETE 
12
// OBSOLETE This program is distributed in the hope that it will be useful,
13
// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
14
// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
// OBSOLETE GNU General Public License for more details.
16
// OBSOLETE 
17
// OBSOLETE You should have received a copy of the GNU General Public License along
18
// OBSOLETE with this program; if not, write to the Free Software Foundation, Inc.,
19
// OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
20
// OBSOLETE 
21
// OBSOLETE #include "sim-main.h"
22
// OBSOLETE #include "targ-vals.h"
23
// OBSOLETE #include "cgen-engine.h"
24
// OBSOLETE 
25
// OBSOLETE /* The semantic code invokes this for invalid (unrecognized) instructions.  */
26
// OBSOLETE 
27
// OBSOLETE SEM_PC
28
// OBSOLETE sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
29
// OBSOLETE {
30
// OBSOLETE   SIM_DESC sd = CPU_STATE (current_cpu);
31
// OBSOLETE 
32
// OBSOLETE #if 0
33
// OBSOLETE   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
34
// OBSOLETE     {
35
// OBSOLETE       h_bsm_set (current_cpu, h_sm_get (current_cpu));
36
// OBSOLETE       h_bie_set (current_cpu, h_ie_get (current_cpu));
37
// OBSOLETE       h_bcond_set (current_cpu, h_cond_get (current_cpu));
38
// OBSOLETE       /* sm not changed */
39
// OBSOLETE       h_ie_set (current_cpu, 0);
40
// OBSOLETE       h_cond_set (current_cpu, 0);
41
// OBSOLETE 
42
// OBSOLETE       h_bpc_set (current_cpu, cia);
43
// OBSOLETE 
44
// OBSOLETE       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
45
// OBSOLETE                       EIT_RSVD_INSN_ADDR);
46
// OBSOLETE     }
47
// OBSOLETE   else
48
// OBSOLETE #endif
49
// OBSOLETE     sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
50
// OBSOLETE   return vpc;
51
// OBSOLETE }
52
// OBSOLETE 
53
// OBSOLETE /* Process an address exception.  */
54
// OBSOLETE 
55
// OBSOLETE void
56
// OBSOLETE fr30_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
57
// OBSOLETE               unsigned int map, int nr_bytes, address_word addr,
58
// OBSOLETE               transfer_type transfer, sim_core_signals sig)
59
// OBSOLETE {
60
// OBSOLETE #if 0
61
// OBSOLETE   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
62
// OBSOLETE     {
63
// OBSOLETE       h_bsm_set (current_cpu, h_sm_get (current_cpu));
64
// OBSOLETE       h_bie_set (current_cpu, h_ie_get (current_cpu));
65
// OBSOLETE       h_bcond_set (current_cpu, h_cond_get (current_cpu));
66
// OBSOLETE       /* sm not changed */
67
// OBSOLETE       h_ie_set (current_cpu, 0);
68
// OBSOLETE       h_cond_set (current_cpu, 0);
69
// OBSOLETE 
70
// OBSOLETE       h_bpc_set (current_cpu, cia);
71
// OBSOLETE 
72
// OBSOLETE       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
73
// OBSOLETE                       EIT_ADDR_EXCP_ADDR);
74
// OBSOLETE     }
75
// OBSOLETE   else
76
// OBSOLETE #endif
77
// OBSOLETE     sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
78
// OBSOLETE                  transfer, sig);
79
// OBSOLETE }
80
// OBSOLETE 
81
// OBSOLETE /* Read/write functions for system call interface.  */
82
// OBSOLETE 
83
// OBSOLETE static int
84
// OBSOLETE syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
85
// OBSOLETE               unsigned long taddr, char *buf, int bytes)
86
// OBSOLETE {
87
// OBSOLETE   SIM_DESC sd = (SIM_DESC) sc->p1;
88
// OBSOLETE   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
89
// OBSOLETE 
90
// OBSOLETE   return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
91
// OBSOLETE }
92
// OBSOLETE 
93
// OBSOLETE static int
94
// OBSOLETE syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
95
// OBSOLETE                unsigned long taddr, const char *buf, int bytes)
96
// OBSOLETE {
97
// OBSOLETE   SIM_DESC sd = (SIM_DESC) sc->p1;
98
// OBSOLETE   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
99
// OBSOLETE 
100
// OBSOLETE   return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
101
// OBSOLETE }
102
// OBSOLETE 
103
// OBSOLETE /* Subroutine of fr30_int to save the PS and PC and setup for INT and INTE.  */
104
// OBSOLETE 
105
// OBSOLETE static void
106
// OBSOLETE setup_int (SIM_CPU *current_cpu, PCADDR pc)
107
// OBSOLETE {
108
// OBSOLETE   USI ssp = fr30bf_h_dr_get (current_cpu, H_DR_SSP);
109
// OBSOLETE   USI ps = fr30bf_h_ps_get (current_cpu);
110
// OBSOLETE 
111
// OBSOLETE   ssp -= 4;
112
// OBSOLETE   SETMEMSI (current_cpu, pc, ssp, ps);
113
// OBSOLETE   ssp -= 4;
114
// OBSOLETE   SETMEMSI (current_cpu, pc, ssp, pc + 2);
115
// OBSOLETE   fr30bf_h_dr_set (current_cpu, H_DR_SSP, ssp);
116
// OBSOLETE   fr30bf_h_sbit_set (current_cpu, 0);
117
// OBSOLETE }
118
// OBSOLETE 
119
// OBSOLETE /* Trap support.
120
// OBSOLETE    The result is the pc address to continue at.
121
// OBSOLETE    Preprocessing like saving the various registers has already been done.  */
122
// OBSOLETE 
123
// OBSOLETE USI
124
// OBSOLETE fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
125
// OBSOLETE {
126
// OBSOLETE   SIM_DESC sd = CPU_STATE (current_cpu);
127
// OBSOLETE   host_callback *cb = STATE_CALLBACK (sd);
128
// OBSOLETE 
129
// OBSOLETE #ifdef SIM_HAVE_BREAKPOINTS
130
// OBSOLETE   /* Check for breakpoints "owned" by the simulator first, regardless
131
// OBSOLETE      of --environment.  */
132
// OBSOLETE   if (num == TRAP_BREAKPOINT)
133
// OBSOLETE     {
134
// OBSOLETE       /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
135
// OBSOLETE      it doesn't return.  Otherwise it returns and let's us try.  */
136
// OBSOLETE       sim_handle_breakpoint (sd, current_cpu, pc);
137
// OBSOLETE       /* Fall through.  */
138
// OBSOLETE     }
139
// OBSOLETE #endif
140
// OBSOLETE 
141
// OBSOLETE   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
142
// OBSOLETE     {
143
// OBSOLETE       /* The new pc is the trap vector entry.
144
// OBSOLETE      We assume there's a branch there to some handler.  */
145
// OBSOLETE       USI new_pc;
146
// OBSOLETE       setup_int (current_cpu, pc);
147
// OBSOLETE       fr30bf_h_ibit_set (current_cpu, 0);
148
// OBSOLETE       new_pc = GETMEMSI (current_cpu, pc,
149
// OBSOLETE                      fr30bf_h_dr_get (current_cpu, H_DR_TBR)
150
// OBSOLETE                      + 1024 - ((num + 1) * 4));
151
// OBSOLETE       return new_pc;
152
// OBSOLETE     }
153
// OBSOLETE 
154
// OBSOLETE   switch (num)
155
// OBSOLETE     {
156
// OBSOLETE     case TRAP_SYSCALL :
157
// OBSOLETE       {
158
// OBSOLETE     /* TODO: find out what the ABI for this is */
159
// OBSOLETE     CB_SYSCALL s;
160
// OBSOLETE 
161
// OBSOLETE     CB_SYSCALL_INIT (&s);
162
// OBSOLETE     s.func = fr30bf_h_gr_get (current_cpu, 0);
163
// OBSOLETE     s.arg1 = fr30bf_h_gr_get (current_cpu, 4);
164
// OBSOLETE     s.arg2 = fr30bf_h_gr_get (current_cpu, 5);
165
// OBSOLETE     s.arg3 = fr30bf_h_gr_get (current_cpu, 6);
166
// OBSOLETE 
167
// OBSOLETE     if (s.func == TARGET_SYS_exit)
168
// OBSOLETE       {
169
// OBSOLETE         sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
170
// OBSOLETE       }
171
// OBSOLETE 
172
// OBSOLETE     s.p1 = (PTR) sd;
173
// OBSOLETE     s.p2 = (PTR) current_cpu;
174
// OBSOLETE     s.read_mem = syscall_read_mem;
175
// OBSOLETE     s.write_mem = syscall_write_mem;
176
// OBSOLETE     cb_syscall (cb, &s);
177
// OBSOLETE     fr30bf_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
178
// OBSOLETE     fr30bf_h_gr_set (current_cpu, 4, s.result);
179
// OBSOLETE     fr30bf_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
180
// OBSOLETE     break;
181
// OBSOLETE       }
182
// OBSOLETE 
183
// OBSOLETE     case TRAP_BREAKPOINT:
184
// OBSOLETE       sim_engine_halt (sd, current_cpu, NULL, pc,
185
// OBSOLETE                    sim_stopped, SIM_SIGTRAP);
186
// OBSOLETE       break;
187
// OBSOLETE 
188
// OBSOLETE     default :
189
// OBSOLETE       {
190
// OBSOLETE     USI new_pc;
191
// OBSOLETE     setup_int (current_cpu, pc);
192
// OBSOLETE     fr30bf_h_ibit_set (current_cpu, 0);
193
// OBSOLETE     new_pc = GETMEMSI (current_cpu, pc,
194
// OBSOLETE                        fr30bf_h_dr_get (current_cpu, H_DR_TBR)
195
// OBSOLETE                        + 1024 - ((num + 1) * 4));
196
// OBSOLETE     return new_pc;
197
// OBSOLETE       }
198
// OBSOLETE     }
199
// OBSOLETE 
200
// OBSOLETE   /* Fake an "reti" insn.
201
// OBSOLETE      Since we didn't push anything to stack, all we need to do is
202
// OBSOLETE      update pc.  */
203
// OBSOLETE   return pc + 2;
204
// OBSOLETE }
205
// OBSOLETE 
206
// OBSOLETE USI
207
// OBSOLETE fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num)
208
// OBSOLETE {
209
// OBSOLETE   /* The new pc is the trap #9 vector entry.
210
// OBSOLETE      We assume there's a branch there to some handler.  */
211
// OBSOLETE   USI new_pc;
212
// OBSOLETE   setup_int (current_cpu, pc);
213
// OBSOLETE   fr30bf_h_ilm_set (current_cpu, 4);
214
// OBSOLETE   new_pc = GETMEMSI (current_cpu, pc,
215
// OBSOLETE                  fr30bf_h_dr_get (current_cpu, H_DR_TBR)
216
// OBSOLETE                  + 1024 - ((9 + 1) * 4));
217
// OBSOLETE   return new_pc;
218
// OBSOLETE }

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.