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1181 |
sfurman |
/* The IGEN simulator generator for GDB, the GNU Debugger.
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Copyright 2002 Free Software Foundation, Inc.
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Contributed by Andrew Cagney.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Output code to manipulate the instruction cache: either create it
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or reference it */
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typedef enum
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{
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declare_variables,
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define_variables,
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undef_variables,
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}
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icache_decl_type;
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typedef enum
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{
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do_not_use_icache = 0,
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get_values_from_icache = 0x1,
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put_values_in_icache = 0x2,
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both_values_and_icache = 0x3,
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}
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icache_body_type;
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extern void print_icache_body
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(lf *file,
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insn_entry * instruction,
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opcode_bits *expanded_bits,
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cache_entry *cache_rules,
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icache_decl_type what_to_declare,
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icache_body_type what_to_do, int nr_prefetched_words);
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/* Output an instruction cache decode function */
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extern void print_icache_declaration
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(lf *file,
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insn_entry * insn,
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opcode_bits *expanded_bits,
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insn_opcodes *opcodes, int nr_prefetched_words);
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extern void print_icache_definition
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(lf *file,
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insn_entry * insn,
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opcode_bits *expanded_bits,
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insn_opcodes *opcodes, cache_entry *cache_rules, int nr_prefetched_words);
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/* Output an instruction cache support function */
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extern function_entry_handler print_icache_internal_function_declaration;
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extern function_entry_handler print_icache_internal_function_definition;
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/* Output the instruction cache table data structure */
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extern void print_icache_struct
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(lf *file, insn_table *instructions, cache_entry *cache_rules);
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/* Output a single instructions decoder */
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