OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.3/] [sim/] [m32r/] [cpux.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1181 sfurman 
/* CPU family header for m32rxf.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU simulators.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#ifndef CPU_M32RXF_H
26 
#define CPU_M32RXF_H
27 
 
28 
/* Maximum number of instructions that are fetched at a time.
29 
   This is for LIW type instructions sets (e.g. m32r).  */
30 
#define MAX_LIW_INSNS 2
31 
 
32 
/* Maximum number of instructions that can be executed in parallel.  */
33 
#define MAX_PARALLEL_INSNS 2
34 
 
35 
/* CPU state information.  */
36 
typedef struct {
37 
  /* Hardware elements.  */
38 
  struct {
39 
  /* program counter */
40 
  USI h_pc;
41 
#define GET_H_PC() CPU (h_pc)
42 
#define SET_H_PC(x) (CPU (h_pc) = (x))
43 
  /* general registers */
44 
  SI h_gr[16];
45 
#define GET_H_GR(a1) CPU (h_gr)[a1]
46 
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 
  /* control registers */
48 
  USI h_cr[16];
49 
#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
50 
#define SET_H_CR(index, x) \
51 
do { \
52 
m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
53 
;} while (0)
54 
  /* accumulator */
55 
  DI h_accum;
56 
#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
57 
#define SET_H_ACCUM(x) \
58 
do { \
59 
m32rxf_h_accum_set_handler (current_cpu, (x));\
60 
;} while (0)
61 
  /* accumulators */
62 
  DI h_accums[2];
63 
#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
64 
#define SET_H_ACCUMS(index, x) \
65 
do { \
66 
m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
67 
;} while (0)
68 
  /* condition bit */
69 
  BI h_cond;
70 
#define GET_H_COND() CPU (h_cond)
71 
#define SET_H_COND(x) (CPU (h_cond) = (x))
72 
  /* psw part of psw */
73 
  UQI h_psw;
74 
#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
75 
#define SET_H_PSW(x) \
76 
do { \
77 
m32rxf_h_psw_set_handler (current_cpu, (x));\
78 
;} while (0)
79 
  /* backup psw */
80 
  UQI h_bpsw;
81 
#define GET_H_BPSW() CPU (h_bpsw)
82 
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
83 
  /* backup bpsw */
84 
  UQI h_bbpsw;
85 
#define GET_H_BBPSW() CPU (h_bbpsw)
86 
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
87 
  /* lock */
88 
  BI h_lock;
89 
#define GET_H_LOCK() CPU (h_lock)
90 
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
91 
  } hardware;
92 
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
93 
} M32RXF_CPU_DATA;
94 
 
95 
/* Cover fns for register access.  */
96 
USI m32rxf_h_pc_get (SIM_CPU *);
97 
void m32rxf_h_pc_set (SIM_CPU *, USI);
98 
SI m32rxf_h_gr_get (SIM_CPU *, UINT);
99 
void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
100 
USI m32rxf_h_cr_get (SIM_CPU *, UINT);
101 
void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
102 
DI m32rxf_h_accum_get (SIM_CPU *);
103 
void m32rxf_h_accum_set (SIM_CPU *, DI);
104 
DI m32rxf_h_accums_get (SIM_CPU *, UINT);
105 
void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
106 
BI m32rxf_h_cond_get (SIM_CPU *);
107 
void m32rxf_h_cond_set (SIM_CPU *, BI);
108 
UQI m32rxf_h_psw_get (SIM_CPU *);
109 
void m32rxf_h_psw_set (SIM_CPU *, UQI);
110 
UQI m32rxf_h_bpsw_get (SIM_CPU *);
111 
void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
112 
UQI m32rxf_h_bbpsw_get (SIM_CPU *);
113 
void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
114 
BI m32rxf_h_lock_get (SIM_CPU *);
115 
void m32rxf_h_lock_set (SIM_CPU *, BI);
116 
 
117 
/* These must be hand-written.  */
118 
extern CPUREG_FETCH_FN m32rxf_fetch_register;
119 
extern CPUREG_STORE_FN m32rxf_store_register;
120 
 
121 
typedef struct {
122 
  int empty;
123 
} MODEL_M32RX_DATA;
124 
 
125 
/* Instruction argument buffer.  */
126 
 
127 
union sem_fields {
128 
  struct { /* no operands */
129 
    int empty;
130 
  } fmt_empty;
131 
  struct { /*  */
132 
    UINT f_uimm4;
133 
  } sfmt_trap;
134 
  struct { /*  */
135 
    IADDR i_disp24;
136 
    unsigned char out_h_gr_SI_14;
137 
  } sfmt_bl24;
138 
  struct { /*  */
139 
    IADDR i_disp8;
140 
    unsigned char out_h_gr_SI_14;
141 
  } sfmt_bl8;
142 
  struct { /*  */
143 
    SI f_imm1;
144 
    UINT f_accd;
145 
    UINT f_accs;
146 
  } sfmt_rac_dsi;
147 
  struct { /*  */
148 
    SI* i_dr;
149 
    UINT f_hi16;
150 
    UINT f_r1;
151 
    unsigned char out_dr;
152 
  } sfmt_seth;
153 
  struct { /*  */
154 
    SI* i_src1;
155 
    UINT f_accs;
156 
    UINT f_r1;
157 
    unsigned char in_src1;
158 
  } sfmt_mvtachi_a;
159 
  struct { /*  */
160 
    SI* i_dr;
161 
    UINT f_accs;
162 
    UINT f_r1;
163 
    unsigned char out_dr;
164 
  } sfmt_mvfachi_a;
165 
  struct { /*  */
166 
    ADDR i_uimm24;
167 
    SI* i_dr;
168 
    UINT f_r1;
169 
    unsigned char out_dr;
170 
  } sfmt_ld24;
171 
  struct { /*  */
172 
    SI* i_sr;
173 
    UINT f_r2;
174 
    unsigned char in_sr;
175 
    unsigned char out_h_gr_SI_14;
176 
  } sfmt_jl;
177 
  struct { /*  */
178 
    SI* i_dr;
179 
    UINT f_r1;
180 
    UINT f_uimm5;
181 
    unsigned char in_dr;
182 
    unsigned char out_dr;
183 
  } sfmt_slli;
184 
  struct { /*  */
185 
    SI* i_dr;
186 
    INT f_simm8;
187 
    UINT f_r1;
188 
    unsigned char in_dr;
189 
    unsigned char out_dr;
190 
  } sfmt_addi;
191 
  struct { /*  */
192 
    SI* i_src1;
193 
    SI* i_src2;
194 
    UINT f_r1;
195 
    UINT f_r2;
196 
    unsigned char in_src1;
197 
    unsigned char in_src2;
198 
    unsigned char out_src2;
199 
  } sfmt_st_plus;
200 
  struct { /*  */
201 
    SI* i_src1;
202 
    SI* i_src2;
203 
    INT f_simm16;
204 
    UINT f_r1;
205 
    UINT f_r2;
206 
    unsigned char in_src1;
207 
    unsigned char in_src2;
208 
  } sfmt_st_d;
209 
  struct { /*  */
210 
    SI* i_src1;
211 
    SI* i_src2;
212 
    UINT f_acc;
213 
    UINT f_r1;
214 
    UINT f_r2;
215 
    unsigned char in_src1;
216 
    unsigned char in_src2;
217 
  } sfmt_machi_a;
218 
  struct { /*  */
219 
    SI* i_dr;
220 
    SI* i_sr;
221 
    UINT f_r1;
222 
    UINT f_r2;
223 
    unsigned char in_sr;
224 
    unsigned char out_dr;
225 
    unsigned char out_sr;
226 
  } sfmt_ld_plus;
227 
  struct { /*  */
228 
    IADDR i_disp16;
229 
    SI* i_src1;
230 
    SI* i_src2;
231 
    UINT f_r1;
232 
    UINT f_r2;
233 
    unsigned char in_src1;
234 
    unsigned char in_src2;
235 
  } sfmt_beq;
236 
  struct { /*  */
237 
    SI* i_dr;
238 
    SI* i_sr;
239 
    UINT f_r1;
240 
    UINT f_r2;
241 
    UINT f_uimm16;
242 
    unsigned char in_sr;
243 
    unsigned char out_dr;
244 
  } sfmt_and3;
245 
  struct { /*  */
246 
    SI* i_dr;
247 
    SI* i_sr;
248 
    INT f_simm16;
249 
    UINT f_r1;
250 
    UINT f_r2;
251 
    unsigned char in_sr;
252 
    unsigned char out_dr;
253 
  } sfmt_add3;
254 
  struct { /*  */
255 
    SI* i_dr;
256 
    SI* i_sr;
257 
    UINT f_r1;
258 
    UINT f_r2;
259 
    unsigned char in_dr;
260 
    unsigned char in_sr;
261 
    unsigned char out_dr;
262 
  } sfmt_add;
263 
#if WITH_SCACHE_PBB
264 
  /* Writeback handler.  */
265 
  struct {
266 
    /* Pointer to argbuf entry for insn whose results need writing back.  */
267 
    const struct argbuf *abuf;
268 
  } write;
269 
  /* x-before handler */
270 
  struct {
271 
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
272 
    int first_p;
273 
  } before;
274 
  /* x-after handler */
275 
  struct {
276 
    int empty;
277 
  } after;
278 
  /* This entry is used to terminate each pbb.  */
279 
  struct {
280 
    /* Number of insns in pbb.  */
281 
    int insn_count;
282 
    /* Next pbb to execute.  */
283 
    SCACHE *next;
284 
    SCACHE *branch_target;
285 
  } chain;
286 
#endif
287 
};
288 
 
289 
/* The ARGBUF struct.  */
290 
struct argbuf {
291 
  /* These are the baseclass definitions.  */
292 
  IADDR addr;
293 
  const IDESC *idesc;
294 
  char trace_p;
295 
  char profile_p;
296 
  /* ??? Temporary hack for skip insns.  */
297 
  char skip_count;
298 
  char unused;
299 
  /* cpu specific data follows */
300 
  union sem semantic;
301 
  int written;
302 
  union sem_fields fields;
303 
};
304 
 
305 
/* A cached insn.
306 
 
307 
   ??? SCACHE used to contain more than just argbuf.  We could delete the
308 
   type entirely and always just use ARGBUF, but for future concerns and as
309 
   a level of abstraction it is left in.  */
310 
 
311 
struct scache {
312 
  struct argbuf argbuf;
313 
};
314 
 
315 
/* Macros to simplify extraction, reading and semantic code.
316 
   These define and assign the local vars that contain the insn's fields.  */
317 
 
318 
#define EXTRACT_IFMT_EMPTY_VARS \
319 
  unsigned int length;
320 
#define EXTRACT_IFMT_EMPTY_CODE \
321 
  length = 0; \
322 
 
323 
#define EXTRACT_IFMT_ADD_VARS \
324 
  UINT f_op1; \
325 
  UINT f_r1; \
326 
  UINT f_op2; \
327 
  UINT f_r2; \
328 
  unsigned int length;
329 
#define EXTRACT_IFMT_ADD_CODE \
330 
  length = 2; \
331 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
332 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
333 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
334 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
335 
 
336 
#define EXTRACT_IFMT_ADD3_VARS \
337 
  UINT f_op1; \
338 
  UINT f_r1; \
339 
  UINT f_op2; \
340 
  UINT f_r2; \
341 
  INT f_simm16; \
342 
  unsigned int length;
343 
#define EXTRACT_IFMT_ADD3_CODE \
344 
  length = 4; \
345 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
346 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
347 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
348 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
349 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
350 
 
351 
#define EXTRACT_IFMT_AND3_VARS \
352 
  UINT f_op1; \
353 
  UINT f_r1; \
354 
  UINT f_op2; \
355 
  UINT f_r2; \
356 
  UINT f_uimm16; \
357 
  unsigned int length;
358 
#define EXTRACT_IFMT_AND3_CODE \
359 
  length = 4; \
360 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
361 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
362 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
363 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
364 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
365 
 
366 
#define EXTRACT_IFMT_OR3_VARS \
367 
  UINT f_op1; \
368 
  UINT f_r1; \
369 
  UINT f_op2; \
370 
  UINT f_r2; \
371 
  UINT f_uimm16; \
372 
  unsigned int length;
373 
#define EXTRACT_IFMT_OR3_CODE \
374 
  length = 4; \
375 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
376 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
377 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
378 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
379 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
380 
 
381 
#define EXTRACT_IFMT_ADDI_VARS \
382 
  UINT f_op1; \
383 
  UINT f_r1; \
384 
  INT f_simm8; \
385 
  unsigned int length;
386 
#define EXTRACT_IFMT_ADDI_CODE \
387 
  length = 2; \
388 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
389 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
390 
  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
391 
 
392 
#define EXTRACT_IFMT_ADDV3_VARS \
393 
  UINT f_op1; \
394 
  UINT f_r1; \
395 
  UINT f_op2; \
396 
  UINT f_r2; \
397 
  INT f_simm16; \
398 
  unsigned int length;
399 
#define EXTRACT_IFMT_ADDV3_CODE \
400 
  length = 4; \
401 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
402 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
403 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
404 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
405 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
406 
 
407 
#define EXTRACT_IFMT_BC8_VARS \
408 
  UINT f_op1; \
409 
  UINT f_r1; \
410 
  SI f_disp8; \
411 
  unsigned int length;
412 
#define EXTRACT_IFMT_BC8_CODE \
413 
  length = 2; \
414 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
415 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
416 
  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
417 
 
418 
#define EXTRACT_IFMT_BC24_VARS \
419 
  UINT f_op1; \
420 
  UINT f_r1; \
421 
  SI f_disp24; \
422 
  unsigned int length;
423 
#define EXTRACT_IFMT_BC24_CODE \
424 
  length = 4; \
425 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
426 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
427 
  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
428 
 
429 
#define EXTRACT_IFMT_BEQ_VARS \
430 
  UINT f_op1; \
431 
  UINT f_r1; \
432 
  UINT f_op2; \
433 
  UINT f_r2; \
434 
  SI f_disp16; \
435 
  unsigned int length;
436 
#define EXTRACT_IFMT_BEQ_CODE \
437 
  length = 4; \
438 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
439 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
440 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
441 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
442 
  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
443 
 
444 
#define EXTRACT_IFMT_BEQZ_VARS \
445 
  UINT f_op1; \
446 
  UINT f_r1; \
447 
  UINT f_op2; \
448 
  UINT f_r2; \
449 
  SI f_disp16; \
450 
  unsigned int length;
451 
#define EXTRACT_IFMT_BEQZ_CODE \
452 
  length = 4; \
453 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
454 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
455 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
456 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
457 
  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
458 
 
459 
#define EXTRACT_IFMT_CMP_VARS \
460 
  UINT f_op1; \
461 
  UINT f_r1; \
462 
  UINT f_op2; \
463 
  UINT f_r2; \
464 
  unsigned int length;
465 
#define EXTRACT_IFMT_CMP_CODE \
466 
  length = 2; \
467 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
468 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
469 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
470 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
471 
 
472 
#define EXTRACT_IFMT_CMPI_VARS \
473 
  UINT f_op1; \
474 
  UINT f_r1; \
475 
  UINT f_op2; \
476 
  UINT f_r2; \
477 
  INT f_simm16; \
478 
  unsigned int length;
479 
#define EXTRACT_IFMT_CMPI_CODE \
480 
  length = 4; \
481 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
482 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
483 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
484 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
485 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
486 
 
487 
#define EXTRACT_IFMT_CMPZ_VARS \
488 
  UINT f_op1; \
489 
  UINT f_r1; \
490 
  UINT f_op2; \
491 
  UINT f_r2; \
492 
  unsigned int length;
493 
#define EXTRACT_IFMT_CMPZ_CODE \
494 
  length = 2; \
495 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
496 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
497 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
498 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
499 
 
500 
#define EXTRACT_IFMT_DIV_VARS \
501 
  UINT f_op1; \
502 
  UINT f_r1; \
503 
  UINT f_op2; \
504 
  UINT f_r2; \
505 
  INT f_simm16; \
506 
  unsigned int length;
507 
#define EXTRACT_IFMT_DIV_CODE \
508 
  length = 4; \
509 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
510 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
511 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
512 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
513 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
514 
 
515 
#define EXTRACT_IFMT_JC_VARS \
516 
  UINT f_op1; \
517 
  UINT f_r1; \
518 
  UINT f_op2; \
519 
  UINT f_r2; \
520 
  unsigned int length;
521 
#define EXTRACT_IFMT_JC_CODE \
522 
  length = 2; \
523 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
524 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
525 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
526 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
527 
 
528 
#define EXTRACT_IFMT_LD24_VARS \
529 
  UINT f_op1; \
530 
  UINT f_r1; \
531 
  UINT f_uimm24; \
532 
  unsigned int length;
533 
#define EXTRACT_IFMT_LD24_CODE \
534 
  length = 4; \
535 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
536 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
537 
  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
538 
 
539 
#define EXTRACT_IFMT_LDI16_VARS \
540 
  UINT f_op1; \
541 
  UINT f_r1; \
542 
  UINT f_op2; \
543 
  UINT f_r2; \
544 
  INT f_simm16; \
545 
  unsigned int length;
546 
#define EXTRACT_IFMT_LDI16_CODE \
547 
  length = 4; \
548 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
549 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
550 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
551 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
552 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
553 
 
554 
#define EXTRACT_IFMT_MACHI_A_VARS \
555 
  UINT f_op1; \
556 
  UINT f_r1; \
557 
  UINT f_acc; \
558 
  UINT f_op23; \
559 
  UINT f_r2; \
560 
  unsigned int length;
561 
#define EXTRACT_IFMT_MACHI_A_CODE \
562 
  length = 2; \
563 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
564 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
565 
  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
566 
  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
567 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
568 
 
569 
#define EXTRACT_IFMT_MVFACHI_A_VARS \
570 
  UINT f_op1; \
571 
  UINT f_r1; \
572 
  UINT f_op2; \
573 
  UINT f_accs; \
574 
  UINT f_op3; \
575 
  unsigned int length;
576 
#define EXTRACT_IFMT_MVFACHI_A_CODE \
577 
  length = 2; \
578 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
579 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
580 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
581 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
582 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
583 
 
584 
#define EXTRACT_IFMT_MVFC_VARS \
585 
  UINT f_op1; \
586 
  UINT f_r1; \
587 
  UINT f_op2; \
588 
  UINT f_r2; \
589 
  unsigned int length;
590 
#define EXTRACT_IFMT_MVFC_CODE \
591 
  length = 2; \
592 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
593 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
594 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
595 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
596 
 
597 
#define EXTRACT_IFMT_MVTACHI_A_VARS \
598 
  UINT f_op1; \
599 
  UINT f_r1; \
600 
  UINT f_op2; \
601 
  UINT f_accs; \
602 
  UINT f_op3; \
603 
  unsigned int length;
604 
#define EXTRACT_IFMT_MVTACHI_A_CODE \
605 
  length = 2; \
606 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
607 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
608 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
609 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
610 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
611 
 
612 
#define EXTRACT_IFMT_MVTC_VARS \
613 
  UINT f_op1; \
614 
  UINT f_r1; \
615 
  UINT f_op2; \
616 
  UINT f_r2; \
617 
  unsigned int length;
618 
#define EXTRACT_IFMT_MVTC_CODE \
619 
  length = 2; \
620 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
621 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
622 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
623 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
624 
 
625 
#define EXTRACT_IFMT_NOP_VARS \
626 
  UINT f_op1; \
627 
  UINT f_r1; \
628 
  UINT f_op2; \
629 
  UINT f_r2; \
630 
  unsigned int length;
631 
#define EXTRACT_IFMT_NOP_CODE \
632 
  length = 2; \
633 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
634 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
635 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
636 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
637 
 
638 
#define EXTRACT_IFMT_RAC_DSI_VARS \
639 
  UINT f_op1; \
640 
  UINT f_accd; \
641 
  UINT f_bits67; \
642 
  UINT f_op2; \
643 
  UINT f_accs; \
644 
  UINT f_bit14; \
645 
  SI f_imm1; \
646 
  unsigned int length;
647 
#define EXTRACT_IFMT_RAC_DSI_CODE \
648 
  length = 2; \
649 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
650 
  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
651 
  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
652 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
653 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
654 
  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
655 
  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
656 
 
657 
#define EXTRACT_IFMT_SETH_VARS \
658 
  UINT f_op1; \
659 
  UINT f_r1; \
660 
  UINT f_op2; \
661 
  UINT f_r2; \
662 
  UINT f_hi16; \
663 
  unsigned int length;
664 
#define EXTRACT_IFMT_SETH_CODE \
665 
  length = 4; \
666 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
667 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
668 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
669 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
670 
  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
671 
 
672 
#define EXTRACT_IFMT_SLLI_VARS \
673 
  UINT f_op1; \
674 
  UINT f_r1; \
675 
  UINT f_shift_op2; \
676 
  UINT f_uimm5; \
677 
  unsigned int length;
678 
#define EXTRACT_IFMT_SLLI_CODE \
679 
  length = 2; \
680 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
681 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
682 
  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
683 
  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
684 
 
685 
#define EXTRACT_IFMT_ST_D_VARS \
686 
  UINT f_op1; \
687 
  UINT f_r1; \
688 
  UINT f_op2; \
689 
  UINT f_r2; \
690 
  INT f_simm16; \
691 
  unsigned int length;
692 
#define EXTRACT_IFMT_ST_D_CODE \
693 
  length = 4; \
694 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
695 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
696 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
697 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
698 
  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
699 
 
700 
#define EXTRACT_IFMT_TRAP_VARS \
701 
  UINT f_op1; \
702 
  UINT f_r1; \
703 
  UINT f_op2; \
704 
  UINT f_uimm4; \
705 
  unsigned int length;
706 
#define EXTRACT_IFMT_TRAP_CODE \
707 
  length = 2; \
708 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
709 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
710 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
711 
  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
712 
 
713 
#define EXTRACT_IFMT_SATB_VARS \
714 
  UINT f_op1; \
715 
  UINT f_r1; \
716 
  UINT f_op2; \
717 
  UINT f_r2; \
718 
  UINT f_uimm16; \
719 
  unsigned int length;
720 
#define EXTRACT_IFMT_SATB_CODE \
721 
  length = 4; \
722 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
723 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
724 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
725 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
726 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
727 
 
728 
/* Queued output values of an instruction.  */
729 
 
730 
struct parexec {
731 
  union {
732 
    struct { /* empty sformat for unspecified field list */
733 
      int empty;
734 
    } sfmt_empty;
735 
    struct { /* e.g. add $dr,$sr */
736 
      SI dr;
737 
    } sfmt_add;
738 
    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
739 
      SI dr;
740 
    } sfmt_add3;
741 
    struct { /* e.g. and3 $dr,$sr,$uimm16 */
742 
      SI dr;
743 
    } sfmt_and3;
744 
    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
745 
      SI dr;
746 
    } sfmt_or3;
747 
    struct { /* e.g. addi $dr,$simm8 */
748 
      SI dr;
749 
    } sfmt_addi;
750 
    struct { /* e.g. addv $dr,$sr */
751 
      BI condbit;
752 
      SI dr;
753 
    } sfmt_addv;
754 
    struct { /* e.g. addv3 $dr,$sr,$simm16 */
755 
      BI condbit;
756 
      SI dr;
757 
    } sfmt_addv3;
758 
    struct { /* e.g. addx $dr,$sr */
759 
      BI condbit;
760 
      SI dr;
761 
    } sfmt_addx;
762 
    struct { /* e.g. bc.s $disp8 */
763 
      USI pc;
764 
    } sfmt_bc8;
765 
    struct { /* e.g. bc.l $disp24 */
766 
      USI pc;
767 
    } sfmt_bc24;
768 
    struct { /* e.g. beq $src1,$src2,$disp16 */
769 
      USI pc;
770 
    } sfmt_beq;
771 
    struct { /* e.g. beqz $src2,$disp16 */
772 
      USI pc;
773 
    } sfmt_beqz;
774 
    struct { /* e.g. bl.s $disp8 */
775 
      SI h_gr_SI_14;
776 
      USI pc;
777 
    } sfmt_bl8;
778 
    struct { /* e.g. bl.l $disp24 */
779 
      SI h_gr_SI_14;
780 
      USI pc;
781 
    } sfmt_bl24;
782 
    struct { /* e.g. bcl.s $disp8 */
783 
      SI h_gr_SI_14;
784 
      USI pc;
785 
    } sfmt_bcl8;
786 
    struct { /* e.g. bcl.l $disp24 */
787 
      SI h_gr_SI_14;
788 
      USI pc;
789 
    } sfmt_bcl24;
790 
    struct { /* e.g. bra.s $disp8 */
791 
      USI pc;
792 
    } sfmt_bra8;
793 
    struct { /* e.g. bra.l $disp24 */
794 
      USI pc;
795 
    } sfmt_bra24;
796 
    struct { /* e.g. cmp $src1,$src2 */
797 
      BI condbit;
798 
    } sfmt_cmp;
799 
    struct { /* e.g. cmpi $src2,$simm16 */
800 
      BI condbit;
801 
    } sfmt_cmpi;
802 
    struct { /* e.g. cmpz $src2 */
803 
      BI condbit;
804 
    } sfmt_cmpz;
805 
    struct { /* e.g. div $dr,$sr */
806 
      SI dr;
807 
    } sfmt_div;
808 
    struct { /* e.g. jc $sr */
809 
      USI pc;
810 
    } sfmt_jc;
811 
    struct { /* e.g. jl $sr */
812 
      SI h_gr_SI_14;
813 
      USI pc;
814 
    } sfmt_jl;
815 
    struct { /* e.g. jmp $sr */
816 
      USI pc;
817 
    } sfmt_jmp;
818 
    struct { /* e.g. ld $dr,@$sr */
819 
      SI dr;
820 
    } sfmt_ld;
821 
    struct { /* e.g. ld $dr,@($slo16,$sr) */
822 
      SI dr;
823 
    } sfmt_ld_d;
824 
    struct { /* e.g. ldb $dr,@$sr */
825 
      SI dr;
826 
    } sfmt_ldb;
827 
    struct { /* e.g. ldb $dr,@($slo16,$sr) */
828 
      SI dr;
829 
    } sfmt_ldb_d;
830 
    struct { /* e.g. ldh $dr,@$sr */
831 
      SI dr;
832 
    } sfmt_ldh;
833 
    struct { /* e.g. ldh $dr,@($slo16,$sr) */
834 
      SI dr;
835 
    } sfmt_ldh_d;
836 
    struct { /* e.g. ld $dr,@$sr+ */
837 
      SI dr;
838 
      SI sr;
839 
    } sfmt_ld_plus;
840 
    struct { /* e.g. ld24 $dr,$uimm24 */
841 
      SI dr;
842 
    } sfmt_ld24;
843 
    struct { /* e.g. ldi8 $dr,$simm8 */
844 
      SI dr;
845 
    } sfmt_ldi8;
846 
    struct { /* e.g. ldi16 $dr,$hash$slo16 */
847 
      SI dr;
848 
    } sfmt_ldi16;
849 
    struct { /* e.g. lock $dr,@$sr */
850 
      SI dr;
851 
      BI h_lock_BI;
852 
    } sfmt_lock;
853 
    struct { /* e.g. machi $src1,$src2,$acc */
854 
      DI acc;
855 
    } sfmt_machi_a;
856 
    struct { /* e.g. mulhi $src1,$src2,$acc */
857 
      DI acc;
858 
    } sfmt_mulhi_a;
859 
    struct { /* e.g. mv $dr,$sr */
860 
      SI dr;
861 
    } sfmt_mv;
862 
    struct { /* e.g. mvfachi $dr,$accs */
863 
      SI dr;
864 
    } sfmt_mvfachi_a;
865 
    struct { /* e.g. mvfc $dr,$scr */
866 
      SI dr;
867 
    } sfmt_mvfc;
868 
    struct { /* e.g. mvtachi $src1,$accs */
869 
      DI accs;
870 
    } sfmt_mvtachi_a;
871 
    struct { /* e.g. mvtc $sr,$dcr */
872 
      USI dcr;
873 
    } sfmt_mvtc;
874 
    struct { /* e.g. nop */
875 
      int empty;
876 
    } sfmt_nop;
877 
    struct { /* e.g. rac $accd,$accs,$imm1 */
878 
      DI accd;
879 
    } sfmt_rac_dsi;
880 
    struct { /* e.g. rte */
881 
      UQI h_bpsw_UQI;
882 
      USI h_cr_USI_6;
883 
      UQI h_psw_UQI;
884 
      USI pc;
885 
    } sfmt_rte;
886 
    struct { /* e.g. seth $dr,$hash$hi16 */
887 
      SI dr;
888 
    } sfmt_seth;
889 
    struct { /* e.g. sll3 $dr,$sr,$simm16 */
890 
      SI dr;
891 
    } sfmt_sll3;
892 
    struct { /* e.g. slli $dr,$uimm5 */
893 
      SI dr;
894 
    } sfmt_slli;
895 
    struct { /* e.g. st $src1,@$src2 */
896 
      SI h_memory_SI_src2;
897 
      USI h_memory_SI_src2_idx;
898 
    } sfmt_st;
899 
    struct { /* e.g. st $src1,@($slo16,$src2) */
900 
      SI h_memory_SI_add__DFLT_src2_slo16;
901 
      USI h_memory_SI_add__DFLT_src2_slo16_idx;
902 
    } sfmt_st_d;
903 
    struct { /* e.g. stb $src1,@$src2 */
904 
      QI h_memory_QI_src2;
905 
      USI h_memory_QI_src2_idx;
906 
    } sfmt_stb;
907 
    struct { /* e.g. stb $src1,@($slo16,$src2) */
908 
      QI h_memory_QI_add__DFLT_src2_slo16;
909 
      USI h_memory_QI_add__DFLT_src2_slo16_idx;
910 
    } sfmt_stb_d;
911 
    struct { /* e.g. sth $src1,@$src2 */
912 
      HI h_memory_HI_src2;
913 
      USI h_memory_HI_src2_idx;
914 
    } sfmt_sth;
915 
    struct { /* e.g. sth $src1,@($slo16,$src2) */
916 
      HI h_memory_HI_add__DFLT_src2_slo16;
917 
      USI h_memory_HI_add__DFLT_src2_slo16_idx;
918 
    } sfmt_sth_d;
919 
    struct { /* e.g. st $src1,@+$src2 */
920 
      SI h_memory_SI_new_src2;
921 
      USI h_memory_SI_new_src2_idx;
922 
      SI src2;
923 
    } sfmt_st_plus;
924 
    struct { /* e.g. trap $uimm4 */
925 
      UQI h_bbpsw_UQI;
926 
      UQI h_bpsw_UQI;
927 
      USI h_cr_USI_14;
928 
      USI h_cr_USI_6;
929 
      UQI h_psw_UQI;
930 
      SI pc;
931 
    } sfmt_trap;
932 
    struct { /* e.g. unlock $src1,@$src2 */
933 
      BI h_lock_BI;
934 
      SI h_memory_SI_src2;
935 
      USI h_memory_SI_src2_idx;
936 
    } sfmt_unlock;
937 
    struct { /* e.g. satb $dr,$sr */
938 
      SI dr;
939 
    } sfmt_satb;
940 
    struct { /* e.g. sat $dr,$sr */
941 
      SI dr;
942 
    } sfmt_sat;
943 
    struct { /* e.g. sadd */
944 
      DI h_accums_DI_0;
945 
    } sfmt_sadd;
946 
    struct { /* e.g. macwu1 $src1,$src2 */
947 
      DI h_accums_DI_1;
948 
    } sfmt_macwu1;
949 
    struct { /* e.g. msblo $src1,$src2 */
950 
      DI accum;
951 
    } sfmt_msblo;
952 
    struct { /* e.g. mulwu1 $src1,$src2 */
953 
      DI h_accums_DI_1;
954 
    } sfmt_mulwu1;
955 
    struct { /* e.g. sc */
956 
      int empty;
957 
    } sfmt_sc;
958 
  } operands;
959 
  /* For conditionally written operands, bitmask of which ones were.  */
960 
  int written;
961 
};
962 
 
963 
/* Collection of various things for the trace handler to use.  */
964 
 
965 
typedef struct trace_record {
966 
  IADDR pc;
967 
  /* FIXME:wip */
968 
} TRACE_RECORD;
969 
 
970 
#endif /* CPU_M32RXF_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.