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[/] [or1k/] [trunk/] [gdb-5.3/] [sim/] [testsuite/] [sim/] [fr30/] [mov.cgs] - Blame information for rev 1765

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Line No. Rev Author Line
1 1181 sfurman
# fr30 testcase for mov $Rj,$Ri
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# mach(): fr30
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        .include "testutils.inc"
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        START
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        .text
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        .global mov
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mov:
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        ; Test mov $Rj,$Ri
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        mvi_h_gr        1,r7
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        mvi_h_dr        0xa,tbr
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        mvi_h_dr        0xb,rp
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        mvi_h_dr        0xc,mdh
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        mvi_h_dr        0xd,mdl
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        mvr_h_gr        sp,ssp
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        mvr_h_gr        sp,usp
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        mov             r7,r7
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        set_cc          0x0f            ; Condition codes should not change
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        test_cc         1 1 1 1
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        test_h_gr       1,r7
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        mov             r7,r8
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        set_cc          0x0e            ; Condition codes should not change
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        test_cc         1 1 1 0
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        test_h_gr       1,r7
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        test_h_gr       1,r8
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        ; Test mov $Rs,$Ri
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        set_cc          0x0d            ; Condition codes should not change
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        mov             tbr,r7
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        test_cc         1 1 0 1
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        test_h_gr       0xa,r7
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        set_cc          0x0c            ; Condition codes should not change
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        mov             rp,r7
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        test_cc         1 1 0 0
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        test_h_gr       0xb,r7
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        set_cc          0x0b            ; Condition codes should not change
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        mov             mdh,r7
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        test_cc         1 0 1 1
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        test_h_gr       0xc,r7
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        set_cc          0x0a            ; Condition codes should not change
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        mov             mdl,r7
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        test_cc         1 0 1 0
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        test_h_gr       0xd,r7
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        set_cc          0x09            ; Condition codes should not change
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        mov             usp,r7
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        test_cc         1 0 0 1
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        testr_h_gr      sp,r7
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        set_cc          0x08            ; Condition codes should not change
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        mov             ssp,r7
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        test_cc         1 0 0 0
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        testr_h_gr      sp,r7
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        ; Test mov $Ri,$Rs
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        set_cc          0x07            ; Condition codes should not change
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        mov             r8,tbr
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        test_cc         0 1 1 1
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        test_h_dr       0x1,tbr
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        set_cc          0x06            ; Condition codes should not change
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        mov             r8,rp
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        test_cc         0 1 1 0
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        test_h_dr       0x1,rp
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        set_cc          0x05            ; Condition codes should not change
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        mov             r8,mdh
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        test_cc         0 1 0 1
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        test_h_dr       0x1,mdh
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        set_cc          0x04            ; Condition codes should not change
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        mov             r8,mdl
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        test_cc         0 1 0 0
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        test_h_dr       0x1,mdl
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        set_cc          0x03            ; Condition codes should not change
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        mov             r8,ssp
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        test_cc         0 0 1 1
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        test_h_dr       0x1,ssp
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        set_cc          0x02            ; Condition codes should not change
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        mov             r8,usp
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        test_cc         0 0 1 0
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        test_h_dr       0x1,usp
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        ; Test mov $PS,$Ri
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        set_cc          0x01            ; Condition codes affect result
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        set_dbits       0x3
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        mov             ps,r7
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        test_cc         0 0 0 1
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        test_h_gr       0x00000601,r7
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        ; Test mov $Ri,PS
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        set_cc          0x01            ; Set opposite of expected
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        set_dbits       0x1             ; Set opposite of expected
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        mvi_h_gr        0x0000040e,r7
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        mov             r7,PS
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        test_cc         1 1 1 0
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        test_dbits      0x2
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        pass

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