OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [gdb-5.3/] [sim/] [z8k/] [tm.h] - Blame information for rev 1776

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1181 sfurman
/* tm.h
2
   Copyright (C) 1992, 1993 Free Software Foundation, Inc.
3
 
4
This file is part of Z8KSIM
5
 
6
Z8KSIM is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2, or (at your option)
9
any later version.
10
 
11
Z8KSIM is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with Z8KZIM; if not, write to the Free Software
18
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
19
 
20
#ifndef _TM_H
21
#define _TM_H
22
 
23
#ifdef __FOOBEYGNUC__
24
typedef SFtype __attribute__ ((mode (SF)));
25
typedef DFtype __attribute__ ((mode (DF)));
26
 
27
typedef int HItype __attribute__ ((mode (HI)));
28
typedef int SItype __attribute__ ((mode (SI)));
29
 
30
typedef unsigned int UHItype __attribute__ ((mode (HI)));
31
typedef unsigned int USItype __attribute__ ((mode (SI)));
32
#else
33
typedef float SFtype;
34
typedef double DFtype;
35
typedef short int HItype;
36
typedef long int SItype;
37
typedef unsigned short UHItype ;
38
typedef unsigned int USItype ;
39
#endif
40
 
41
typedef struct UDIstruct
42
{
43
  USItype high;
44
  USItype low;
45
} UDItype;
46
 
47
#define BIG_ENDIAN_HOST
48
typedef unsigned int sim_phys_addr_type;
49
typedef unsigned int sim_logical_addr_type;
50
 
51
#define PAGE_POWER 23           /*  only one pages */
52
 
53
#define MAP_PHYSICAL_TO_LOGICAL(x)  (((x >> 8) & 0x7f0000) | (x & 0xffff))
54
#define MAP_LOGICAL_TO_PHYSICAL(x)  (((x <<8) & 0x7f000000) | (x & 0xffff))
55
#define REG_PC     17
56
#define REG_CYCLES 18
57
#define REG_INSTS  19
58
#define REG_TIME   20
59
#define REG_FP     21
60
#define REG_SP     22
61
#define REG_CCR    16
62
 
63
#define SET_REG(x,y)  set_reg(x,y)
64
#define SINGLE_STEP 1
65
 
66
#define PSW_CARRY context->carry
67
#define PSW_OP    context->op
68
#define PSW_OVERFLOW context->overflow
69
#define PSW_SIGN context->sign
70
#define PSW_ZERO context->zero
71
#define GET_PC()  context->pc
72
#define SET_PC(x) context->pc = x
73
 
74
struct op_info
75
{
76
  short int exec;
77
};
78
 
79
extern struct op_info op_info_table[];
80
 
81
typedef union
82
{
83
  unsigned short int word;
84
 
85
}
86
 
87
borw_type;
88
 
89
typedef struct state_struct
90
{
91
  unsigned short *memory;
92
  int carry;
93
  int sign;
94
  int zero;
95
  int overflow;
96
  int op;
97
  int cycles;
98
 
99
  borw_type regs[16];
100
 
101
  sim_phys_addr_type sometimes_pc;
102
#ifdef __GNUC__
103
  volatile
104
#endif
105
  int exception;
106
 
107
#define iwords_0  iwords0
108
#define iwords_1  iwords1
109
#define iwords_2  iwords2
110
#define iwords_3  iwords3
111
 
112
#define ibytes_0    (iwords_0>>8)
113
#define ibytes_1    (iwords_0&0xff)
114
#define ibytes_2    (iwords_1>>8)
115
#define ibytes_3    (iwords_1& 0xff)
116
#define ibytes_4    (iwords_2>>8)
117
 
118
  int insts;
119
  int ticks;
120
 
121
  int next_inst;
122
  int broken_flags;
123
 
124
  int srca;
125
  int srcb;
126
  int dst;
127
  int size;
128
}
129
 
130
sim_state_type;
131
 
132
#define CMP_FLAGS 100
133
#define TST_FLAGS 101
134
#endif
135
 
136
extern int get_word_mem_da PARAMS((sim_state_type *context, int addr));
137
extern int get_word_reg PARAMS((sim_state_type *context, int reg));
138
extern void support_call PARAMS((sim_state_type *context, int sc));
139
extern void tm_exception PARAMS((int x));
140
extern int tm_read_byte PARAMS((int x));
141
extern int tm_signal PARAMS((void));
142
extern void tm_state PARAMS((sim_state_type *x));
143
extern void tm_write_byte PARAMS((int x, int y));
144
extern void bfop_bad1 PARAMS(());
145
extern int fail PARAMS((sim_state_type *context, int v));
146
extern void fop_bad PARAMS((sim_state_type *context));
147
extern void sfop_bad1 PARAMS(());
148
extern void swap_long PARAMS((char *buf, int val));
149
extern void swap_word PARAMS((char *buf, int val));
150
extern void tm_fetch_register PARAMS((int regno, char *buf));
151
extern void tm_info_print PARAMS((sim_state_type *x));
152
extern void tm_resume PARAMS((int step));
153
extern void tm_store_register PARAMS((int regno, int value));
154
 
155
 
156
#ifndef __GNUC__
157
/* If were using gnuc then these will be inlined, so the prototypes
158
 won't be right */
159
long int sitoptr PARAMS((long int si));
160
long int ptrtosi PARAMS((long int ptr));
161
void put_long_reg PARAMS((sim_state_type *context, int reg, int val));
162
void put_quad_reg PARAMS((sim_state_type *context, int reg, int val1, int val2));
163
void put_word_reg PARAMS((sim_state_type *context, int reg, int val));
164
SItype get_long_reg PARAMS((sim_state_type *context, int reg));
165
void put_byte_reg PARAMS((sim_state_type *context, int reg, int val));
166
int get_byte_reg PARAMS((sim_state_type *context, int reg));
167
void put_word_mem_da PARAMS((sim_state_type *context, int addr, int value));
168
unsigned char get_byte_mem_da PARAMS((sim_state_type *context, int addr));
169
void put_byte_mem_da PARAMS((sim_state_type *context, int addr, int value));
170
SItype get_long_mem_da PARAMS((sim_state_type *context, int addr));
171
void put_long_mem_da PARAMS((sim_state_type *context, int addr, int value));
172
int get_word_mem_ir PARAMS((sim_state_type *context, int reg));
173
void put_word_mem_ir PARAMS((sim_state_type *context, int reg, int value));
174
int get_byte_mem_ir PARAMS((sim_state_type *context, int reg));
175
void put_byte_mem_ir PARAMS((sim_state_type *context, int reg, int value));
176
int get_long_mem_ir PARAMS((sim_state_type *context, int reg));
177
void put_long_mem_ir PARAMS((sim_state_type *context, int reg, int value));
178
void put_long_mem_x PARAMS((sim_state_type *context, int base, int reg, int value));
179
void put_word_mem_x PARAMS((sim_state_type *context, int base, int reg, int value));
180
void put_byte_mem_x PARAMS((sim_state_type *context, int base, int reg, int value));
181
int get_word_mem_x PARAMS((sim_state_type *context, int base, int reg));
182
int get_byte_mem_x PARAMS((sim_state_type *context, int base, int reg));
183
int get_long_mem_x PARAMS((sim_state_type *context, int base, int reg));
184
int COND PARAMS((sim_state_type *context, int c));
185
void NORMAL_FLAGS PARAMS((sim_state_type *context, int size, int dst, int srca, int srcb));
186
void TEST_NORMAL_FLAGS PARAMS((sim_state_type *context, int size, int dst));
187
void put_ptr_long_reg PARAMS((sim_state_type *context, int reg, int val));
188
long int get_ptr_long_reg PARAMS((sim_state_type *context, int reg));
189
long int get_ptr_long_mem_ir PARAMS((sim_state_type *context, int reg));
190
long int get_ptr_long_mem_da PARAMS((sim_state_type *context, long int addr));
191
void put_ptr_long_mem_da PARAMS((sim_state_type *context, long int addr, long int ptr));
192
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.