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[/] [or1k/] [trunk/] [gen_or1k_isa/] [sources/] [or1k_isadesc.h] - Blame information for rev 109

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1 14 lampret 
/* Information about OR1K ISA. W/o this we can't generate or1k_isa_part.tex.
2 
*/
3 
 
4 
struct or1k_isa {
5 
        char *name;
6 
        char *title;
7 
        char *desc;
8 87 lampret 
        char *oper32;
9 
        char *oper64;
10 14 lampret 
        char *except;
11 
        int  class;
12 87 lampret 
        int  printed;
13 14 lampret 
};
14 
 
15 87 lampret 
#define ORBIS32I        1
16 
#define ORBIS32II       2
17 
#define ORBIS64I        3
18 
#define ORBIS64II       4
19 
#define ORFPX32I        5
20 
#define ORFPX32II       6
21 
#define ORFPX64I        7
22 
#define ORFPX64II       8
23 
#define ORVDX64I        9
24 
#define ORVDX64II       10
25 
 
26 14 lampret 
static struct or1k_isa or1k_isa_info[] =
27 
{
28 
 
29 87 lampret 
/*** ORBIS32 ***/
30 14 lampret 
 
31 87 lampret 
{"l.addi", "Add Immediate Signed",
32 
        "Immediate is signed-extended and added to the contents of general-purpose"
33 
        "register rA to form the result. The result is placed into general-purpose"
34 
        "register rD.",
35 95 lampret 
        "rD[31:0] <- rA[31:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
36 
        "rD[63:0] <- rA[63:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
37 
        "Range Exception", ORBIS32I,},
38 14 lampret 
 
39 87 lampret 
{"l.andi", "And with Immediate Half Word",
40 
        "Immediate is zero-extended and combined with the contents "
41 
        "of general-purpose register rB in a bit-wise logical AND operation. The "
42 
        "result is placed into general-purpose register rD.",
43 
        "rD[31:0] <- rB[31:0] AND extz(Immediate)",
44 
        "rD[63:0] <- rB[63:0] AND extz(Immediate)",
45 
        "None", ORBIS32I,},
46 14 lampret 
 
47 87 lampret 
{"l.ori", "Or with Immediate Half Word",
48 
        "Immediate is zero-extended and combined with the contents "
49 
        "of general-purpose register rB in a bit-wise logical OR operation. The "
50 
        "result is placed into general-purpose register rD.",
51 
        "rD[31:0] <- rB[31:0] OR extz(Immediate)",
52 
        "rD[63:0] <- rB[63:0] OR extz(Immediate)",
53 
        "None", ORBIS32I,},
54 14 lampret 
 
55 87 lampret 
{"l.xori", "Exclusive Or with Immediate Half Word",
56 
        "Immediate is zero-extended and combined with the contents of general-purpose "
57 
        "register rB in a bit-wise logical XOR operation. The result is "
58 
        "placed into general-purpose register rD.",
59 
        "rD[31:0] <- rB[31:0] XOR exts(Immediate)",
60 
        "rD[63:0] <- rB[63:0] XOR exts(Immediate)",
61 
        "None", ORBIS32I,},
62 14 lampret 
 
63 87 lampret 
{"l.slli", "Shift Left Logical with Immediate",
64 
        "6-bit immediate specifies the number of "
65 
        "bit positions the contents of general-purpose register rA are shifted left, "
66 
        "inserting zeros into the low-order bits. Result is written into general-purpose "
67 
        "rD.",
68 
        "rD[31:L] <- rA[31-L:0]\\rD[L-1:0] <- 0",
69 
        "rD[63:L] <- rA[63-L:0]\\rD[L-1:0] <- 0",
70 
        "None", ORBIS32I,},
71 14 lampret 
 
72 87 lampret 
{"l.srai", "Shift Right Arithmetic with Immediate",
73 
        "6-bit immediate specifies the number of "
74 
        "bit positions the contents of general-purpose register rA are shifted right, "
75 
        "sign-extending the high-order bits. Result is written into "
76 
        "general-purpose register rD.",
77 
        "rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[31]",
78 
        "rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[63]",
79 
        "None", ORBIS32I,},
80 
 
81 
{"l.srli", "Shift Right Logical with Immediate",
82 
        "6-bit Immediate specifies the number of "
83 
        "bit positions the contents of general-purpose register rA are shifted right, "
84 
        "inserting zeros into the high-order bits. Result is written into general-purpose "
85 
        "register rD.",
86 
        "rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- 0",
87 
        "rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- 0",
88 
        "None", ORBIS32I,},
89 
 
90 
{"l.rori", "Rotate Right with Immediate",
91 
        "6-bit immediate specifies the number of "
92 
        "bit positions the contents of general-purpose register rA are rotated right. "
93 
        "Result is written into general-purpose register rD.",
94 
        "rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[L-1:0]",
95 
        "rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[L-1:0]",
96 
        "None", ORBIS32I,},
97 
 
98 
{"l.muli", "Multiply Immediate Signed",
99 
        "Immediate and the contents of general-purpose register rA are "
100 
        "multiplied and the result is truncated to destination register width and placed into "
101 
        "general-purpose register rD.",
102 95 lampret 
        "rD[31:0] <- rA[31:0] * Immediate\\SR[OV] <- overflow",
103 
        "rD[63:0] <- rA[63:0] * Immediate\\SR[OV] <- overflow",
104 87 lampret 
        "None", ORBIS32I,},
105 
 
106 95 lampret 
{"l.maci", "Multiply Immediate Signed and Accumulate",
107 
        "Immediate and the contents of general-purpose register rA are "
108 
        "multiplied and the result is truncated to 32 bits and added "
109 
        "to the special-purpose registers MACHI and MACLO. "
110 
        "All operands are treated as signed integers.",
111 
        "M[31:0] <- rA[31:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
112 
        "SR[OV] <- overflow",
113 
        "M[31:0] <- rA[63:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
114 
        "SR[OV] <- overflow",
115 
        "None", ORBIS32II,},
116 
 
117 87 lampret 
{"l.exths", "Extend Half Word with Sign",
118 
        "Bit 15 of general-purpose register rA is placed in high-order bits of "
119 
        "general-purpose register rD. The low-order 16 bits of general-purpose register rA "
120 
        "are copied into low-order 16 bits of general-purpose register rD.",
121 
        "rD[31:16] <- rA[15]\\rD[15:0] <- rA[15:0]",
122 
        "rD[63:16] <- rA[15]\\rD[15:0] <- rA[15:0]",
123 
        "None", ORBIS32II,},
124 
 
125 
{"l.extbs", "Extend Byte with Sign",
126 
        "Bit 7 of general-purpose register rA is placed in high-order bits of "
127 
        "general-purpose register rD. The low-order eight bits of general-purpose register rA "
128 
        "are copied from low-order eight bits of general-purpose register rD.",
129 
        "rD[31:8] <- rA[7]\\rD[7:0] <- rA[7:0]",
130 
        "rD[63:8] <- rA[7]\\rD[7:0] <- rA[7:0]",
131 
        "None", ORBIS32II,},
132 
 
133 
{"l.extbz", "Extend Byte with Zero",
134 
        "Zero is placed in high-order bits of "
135 
        "general-purpose register rD. The low-order eight bits of general-purpose register rA "
136 
        "are copied into low-order eight bits of general-purpose register rD.",
137 
        "rD[31:8] <- 0\\rD[7:0] <- rA[7:0]",
138 
        "rD[63:8] <- 0\\rD[7:0] <- rA[7:0]",
139 
        "None", ORBIS32II,},
140 
 
141 
{"l.exthz", "Extend Half Word with Zero",
142 
        "Zero is placed in high-order bits of "
143 
        "general-purpose register rD. The low-order 16 bits of general-purpose register rA "
144 
        "are copied into low-order 16 bits of general-purpose register rD.",
145 
        "rD[31:16] <- 0\\rD[15:0] <- rA[15:0]",
146 
        "rD[63:16] <- 0\\rD[15:0] <- rA[15:0]",
147 
        "None", ORBIS32II,},
148 
 
149 
{"l.extwz", "Extend Word with Zero",
150 
        "Zero is placed in high-order bits of "
151 
        "general-purpose register rD. The low-order 32 bits of general-purpose register rA "
152 
        "are copied into low-order 32 bits of general-purpose register rD.",
153 
        "rD[31:0] <- rA[31:0]",
154 
        "rD[63:32] <- 0\\rD[31:0] <- rA[31:0]",
155 
        "None", ORBIS64II,},
156 
 
157 
{"l.extws", "Extend Word with Sign",
158 
        "Bit 31 of general-purpose register rA is placed in high-order bits of "
159 
        "general-purpose register rD. The low-order 32 bits of general-purpose register rA "
160 
        "are copied from low-order 32 bits of general-purpose register rD.",
161 
        "rD[31:0] <- rA[31:0]",
162 
        "rD[63:32] <- rA[31]\\rD[31:0] <- rA[31:0]",
163 
        "None", ORBIS64II,},
164 
 
165 109 lampret 
{"l.cmov", "Conditional Move",
166 
        "If SR[CF] is set, general-purpose register rA is placed in "
167 
        "general-purpose register rD. If SR[CF] is cleared, general-purpose register rB "
168 
        "is placed in general-purpose register rD.",
169 
        "rD[31:0] <- SR[CF] ? rA[31:0] : rB[31:0]",
170 
        "rD[63:0] <- SR[CF] ? rA[63:0] : rB[63:0]",
171 
        "None", ORBIS32II,},
172 
 
173 
{"l.ff1", "Find First 1",
174 
        "Position of the first '1' bit is written into general-purpose register rD. Checking for "
175 
        "bit '1' starts with MSB and counting is decremented for every zero bit. If first '1' bit is "
176 
        "discovered in LSB, one is written into rD. If there is no '1' bits, zero is written in rD.",
177 
        "rD[31:0] <- rA[31] ? 32 : rA[30] ? 31 ... r[0] ? 1 : 0",
178 
        "rD[63:0] <- rA[63] ? 64 : rA[62] ? 63 ... r[0] ? 1 : 0",
179 
        "None", ORBIS32II,},
180 
 
181 87 lampret 
{"l.lbs", "Load Byte and Extend with Sign",
182 
        "Offset is sign-extended and added to the contents of general-purpose "
183 
        "register rA. Sum represents effective address. The byte in memory "
184 14 lampret 
        "addressed by EA is loaded into the low-order eight bits of "
185 87 lampret 
        "general-purpose register rD. "
186 
        "High-order bits of general-purpose register rD are replaced with "
187 14 lampret 
        "bit 7 of the loaded value.",
188 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- rA[8]",
189 
        "EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- rA[8]",
190 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
191 14 lampret 
 
192 87 lampret 
{"l.lhs", "Load Half Word and Extend with Sign",
193 
        "Offset is sign-extended and added to the contents of general-purpose "
194 
        "register rA. Sum represents effective address. The half word in memory "
195 14 lampret 
        "addressed by EA is loaded into the low-order 16 bits of "
196 87 lampret 
        "general-purpose register rD. "
197 
        "High-order bits of general-purpose register rD are replaced with "
198 14 lampret 
        "bit 15 of the loaded value.",
199 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- rA[15]",
200 
        "EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- rA[15]",
201 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
202 14 lampret 
 
203 87 lampret 
{"l.lws", "Load Single Word and Extend with Sign",
204 
        "Offset is sign-extended and added to the contents of general-purpose "
205 
        "register rA. Sum represents effective address. The single word in memory "
206 
        "addressed by EA is loaded into the low-order 32 bits of "
207 
        "general-purpose register rD. "
208 
        "High-order bits of general-purpose register rD are replaced with "
209 
        "bit 31 of the loaded value.",
210 
        "EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]",
211 
        "EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- rA[31]",
212 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
213 
 
214 
{"l.lbz", "Load Byte and Extend with Zero",
215 
        "Offset is sign-extended and added to the contents of general-purpose "
216 
        "register rA. Sum represents effective address. The byte in memory "
217 14 lampret 
        "addressed by EA is loaded into the low-order eight bits of "
218 87 lampret 
        "general-purpose register rD. "
219 
        "High-order bits of general-purpose register rD are replaced with "
220 14 lampret 
        "zero.",
221 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- 0",
222 
        "EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- 0",
223 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
224 14 lampret 
 
225 87 lampret 
{"l.lhz", "Load Half Word and Extend with Zero",
226 
        "Offset is sign-extended and added to the contents of general-purpose "
227 
        "register rA. Sum represents effective address. The half word in memory "
228 14 lampret 
        "addressed by EA is loaded into the low-order 16 bits of "
229 87 lampret 
        "general-purpose register rD. "
230 
        "High-order bits of general-purpose register rD are replaced with "
231 14 lampret 
        "zero.",
232 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- 0",
233 
        "EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- 0",
234 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
235 14 lampret 
 
236 87 lampret 
{"l.lwz", "Load Single Word and Extend with Zero",
237 
        "Offset is sign-extended and added to the contents of general-purpose "
238 
        "register rA. Sum represents effective address. The single word in memory "
239 
        "addressed by EA is loaded into the low-order 32 bits of "
240 
        "general-purpose register rD. "
241 
        "High-order bits of general-purpose register rD are replaced with "
242 
        "zero.",
243 
        "EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]",
244 
        "EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- 0",
245 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
246 14 lampret 
 
247 87 lampret 
{"l.ld", "Load Double Word",
248 
        "Offset is sign-extended and added to the contents of general-purpose "
249 
        "register rA. Sum represents effective address. The double word in memory "
250 
        "addressed by EA is loaded into general-purpose register rD. ",
251 
        "N/A",
252 
        "EA <- exts(Immediate) + rA[63:0]\\rD[63:0] <- (EA)[63:0]",
253 
        "TLB miss\\Page fault\\Bus error", ORBIS64I,},
254 14 lampret 
 
255 87 lampret 
{"l.sd", "Store Double Word",
256 
        "Offset is sign-extended and added to the contents of general-purpose "
257 
        "register rA. Sum represents effective address. The double word in "
258 95 lampret 
        "general-purpose register rB is stored to memory location addressed by EA. ",
259 87 lampret 
        "N/A",
260 
        "EA <- exts(Immediate) + rA[63:0]\\(EA)[63:0] <- rB[63:0]",
261 
        "TLB miss\\Page fault\\Bus error", ORBIS64I,},
262 14 lampret 
 
263 87 lampret 
{"l.sw", "Store Single Word",
264 
        "Offset is sign-extended and added to the contents of general-purpose "
265 
        "register rA. Sum represents effective address. The low-order 32 bits of "
266 95 lampret 
        "general-purpose register rB are stored to memory location addressed by EA. ",
267 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\(EA)[31:0] <- rB[31:0]",
268 
        "EA <- exts(Immediate) + rA[63:0]\\(EA)[31:0] <- rB[31:0]",
269 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
270 14 lampret 
 
271 87 lampret 
{"l.sh", "Store Half Word",
272 
        "Offset is sign-extended and added to the contents of general-purpose "
273 14 lampret 
        "register rA. Sum represents effective address. The low-order 16 bits "
274 95 lampret 
        "of general-purpose register rB are stored to memory location addressed by EA. ",
275 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\(EA)[15:0] <- rB[15:0]",
276 
        "EA <- exts(Immediate) + rA[63:0]\\(EA)[15:0] <- rB[15:0]",
277 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
278 14 lampret 
 
279 87 lampret 
{"l.sb", "Store Byte",
280 
        "Offset is sign-extended and added to the contents of general-purpose "
281 14 lampret 
        "register rA. Sum represents effective address. The low-order 8 bits "
282 95 lampret 
        "of general-purpose register rB are stored to memory location addressed by EA. ",
283 87 lampret 
        "EA <- exts(Immediate) + rA[31:0]\\(EA)[7:0] <- rB[7:0]",
284 
        "EA <- exts(Immediate) + rA[63:0]\\(EA)[7:0] <- rB[7:0]",
285 
        "TLB miss\\Page fault\\Bus error", ORBIS32I,},
286 14 lampret 
 
287 87 lampret 
{"l.add", "Add Signed",
288 
        "The contents of general-purpose register rA is added to the contents "
289 
        "of general-purpose register rB to form the result. The result is placed into "
290 
        "general-purpose register rD.",
291 95 lampret 
        "rD[31:0] <- rA[31:0] + rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
292 
        "rD[63:0] <- rA[63:0] + rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
293 
        "Range Exception", ORBIS32I,},
294 14 lampret 
 
295 87 lampret 
{"l.addc", "Add Signed and Carry",
296 
        "The contents of general-purpose register rA is added to the contents "
297 
        "of general-purpose register rB and carry SR[CY] to form the result. "
298 
        "The result is placed into general-purpose register rD.",
299 95 lampret 
        "rD[31:0] <- rA[31:0] + rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
300 
        "rD[63:0] <- rA[63:0] + rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
301 
        "Range Exception", ORBIS32I,},
302 14 lampret 
 
303 87 lampret 
{"l.sub", "Subtract Signed",
304 
        "The contents of general-purpose register rB is subtracted from the contents "
305 
        "of general-purpose register rA to form the result. The result is placed into "
306 
        "general-purpose register rD.",
307 95 lampret 
        "rD[31:0] <- rA[31:0] - rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
308 
        "rD[63:0] <- rA[63:0] - rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
309 
        "Range Exception", ORBIS32I,},
310 14 lampret 
 
311 87 lampret 
{"l.sll", "Shift Left Logical",
312 
        "General-purpose register rB specifies the number of "
313 
        "bit positions the contents of general-purpose register rA are shifted left, "
314 
        "inserting zeros into the low-order bits. Result is written into general-purpose "
315 
        "rD.",
316 
        "rD[31:rB] <- rA[31-rB:0]\\rD[rB-1:0] <- 0",
317 
        "rD[63:rB] <- rA[63-rB:0]\\rD[rB-1:0] <- 0",
318 
        "None", ORBIS32I,},
319 14 lampret 
 
320 87 lampret 
{"l.sra", "Shift Right Arithmetic",
321 
        "General-purpose register rB specifies the number of "
322 
        "bit positions the contents of general-purpose register rA are shifted right, "
323 
        "sign-extending the high-order bits. Result is written into "
324 
        "general-purpose register rD.",
325 
        "rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rB[31]",
326 
        "rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rB[63]",
327 
        "None", ORBIS32I,},
328 14 lampret 
 
329 87 lampret 
{"l.srl", "Shift Right Logical",
330 
        "General-purpose register rB specifies the number of "
331 
        "bit positions the contents of general-purpose register rA are shifted right, "
332 
        "inserting zeros into the high-order bits. Result is written into general-purpose "
333 
        "register rD.",
334 
        "rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- 0",
335 
        "rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- 0",
336 
        "None", ORBIS32I,},
337 14 lampret 
 
338 87 lampret 
{"l.ror", "Rotate Right",
339 
        "General-purpose register rB specifies the number of "
340 
        "bit positions the contents of general-purpose register rA are rotated right. "
341 
        "Result is written into general-purpose register rD.",
342 
        "rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rA[rB-1:0]",
343 
        "rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rA[rB-1:0]",
344 
        "None", ORBIS32II,},
345 14 lampret 
 
346 87 lampret 
{"l.and", "And",
347 
        "The contents of general-purpose register rA are combined with the contents "
348 
        "of general-purpose register rB in a bit-wise logical AND operation. The "
349 
        "result is placed into general-purpose register rD.",
350 
        "rD[31:0] <- rA[31:0] AND rB[31:0]",
351 
        "rD[63:0] <- rA[63:0] AND rB[63:0]",
352 
        "None", ORBIS32I,},
353 14 lampret 
 
354 87 lampret 
{"l.or", "Or",
355 
        "The contents of general-purpose register rA are combined with the contents "
356 
        "of general-purpose register rB in a bit-wise logical OR operation. The "
357 
        "result is placed into general-purpose register rD.",
358 
        "rD[31:0] <- rA[31:0] OR rB[31:0]",
359 
        "rD[63:0] <- rA[63:0] OR rB[63:0]",
360 
        "None", ORBIS32I,},
361 14 lampret 
 
362 87 lampret 
{"l.xor", "Exclusive Or",
363 
        "The contents of general-purpose register rA are combined with the contents "
364 
        "of general-purpose register rB in a bit-wise logical XOR operation. The "
365 
        "result is placed into general-purpose register rD.",
366 
        "rD[31:0] <- rA[31:0] XOR rB[31:0]",
367 
        "rD[63:0] <- rA[63:0] XOR rB[63:0]",
368 
        "None", ORBIS32I,},
369 14 lampret 
 
370 87 lampret 
{"l.mac", "Multiply Signed and Accumulate",
371 
        "The contents of general-purpose register rA and the contents of general-purpose "
372 
        "register rB are multiplied and the result is truncated to 32 bits and added "
373 
        "to the special-purpose registers MACHI and MACLO. "
374 
        "All operands are treated as signed integers.",
375 95 lampret 
        "M[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
376 
        "SR[OV] <- overflow",
377 
        "M[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
378 
        "SR[OV] <- overflow",
379 87 lampret 
        "None", ORBIS32II,},
380 
 
381 
{"l.mul", "Multiply Signed",
382 
        "The contents of general-purpose register rA and the contents of general-purpose "
383 
        "register rB are multiplied and the result is truncated to destination register width "
384 
        "and placed into general-purpose register rD. "
385 
        "Both operands are treated as unsigned integers.",
386 95 lampret 
        "rD[31:0] <- rA[31:0] * rB[31:0]\\SR[OV] <- overflow",
387 
        "rD[63:0] <- rA[63:0] * rB[63:0]\\SR[OV] <- overflow",
388 87 lampret 
        "None", ORBIS32I,},
389 
 
390 
{"l.mulu", "Multiply Unsigned",
391 
        "The contents of general-purpose register rA and the contents of general-purpose "
392 
        "register rB are multiplied and the result is truncated to destination register width "
393 
        "and placed into general-purpose register rD. "
394 
        "Both operands are treated as unsigned integers.",
395 95 lampret 
        "rD[31:0] <- rA[31:0] * rB[31:0]\\SR[OV] <- overflow",
396 
        "rD[63:0] <- rA[63:0] * rB[63:0]\\SR[OV] <- overflow",
397 87 lampret 
        "None", ORBIS32I,},
398 
 
399 
{"l.div", "Divide Signed",
400 
        "The contents of general-purpose register rA are divided by the contents of "
401 
        "general-purpose register rB and the result is placed into general-purpose register "
402 
        "rD. Both operands are treated as signed integers. A divide by zero "
403 14 lampret 
        "flag is set when the divisor is zero.",
404 95 lampret 
        "rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow",
405 
        "rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow",
406 87 lampret 
        "None", ORBIS32II,},
407 14 lampret 
 
408 87 lampret 
{"l.divu", "Divide Unsigned",
409 
        "The contents of general-purpose register rA are divided by the contents of "
410 
        "general-purpose register rA and the result is placed into general-purpose register "
411 
        "rD. Both operands are treated as unsigned integers. A divide by zero "
412 14 lampret 
        "flag is set when the divisor is zero.",
413 95 lampret 
        "rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow",
414 
        "rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow",
415 87 lampret 
        "None", ORBIS32II,},
416 14 lampret 
 
417 87 lampret 
{"l.sfeq", "Set Flag if Equal",
418 
        "The contents of general-purpose register rA and the contents of general-purpose "
419 14 lampret 
        "register rB are compared. If the two registers are equal, "
420 
        "then the compare flag is set; otherwise the compare flag is cleared.",
421 87 lampret 
        "flag <- rA[31:0] == rB[31:0]",
422 
        "flag <- rA[63:0] == rB[63:0]",
423 
        "None", ORBIS32I,},
424 14 lampret 
 
425 87 lampret 
{"l.sfne", "Set Flag if Not Equal",
426 
        "The contents of general-purpose register rA and the contents of general-purpose "
427 14 lampret 
        "register rB are compared. If the two registers are not equal, "
428 
        "then the compare flag is set; otherwise the compare flag is cleared.",
429 87 lampret 
        "flag <- rA[31:0] != rB[31:0]",
430 
        "flag <- rA[63:0] != rB[63:0]",
431 
        "None", ORBIS32I,},
432 14 lampret 
 
433 87 lampret 
{"l.sfgts", "Set Flag if Greater Than Signed",
434 
        "The contents of general-purpose register rA and the contents of general-purpose "
435 14 lampret 
        "register rB are compared as signed integers. If the contents "
436 
        "of the first register are greater than the contents of the second "
437 
        "register, "
438 
        "then the compare flag is set; otherwise the compare flag is cleared.",
439 87 lampret 
        "flag <- rA[31:0] > rB[31:0]",
440 
        "flag <- rA[63:0] > rB[63:0]",
441 
        "None", ORBIS32I,},
442 14 lampret 
 
443 87 lampret 
{"l.sfges", "Set Flag if Greater or Equal Than Signed",
444 
        "The contents of general-purpose register rA and the contents of general-purpose "
445 14 lampret 
        "register rB are compared as signed integers. If the contents "
446 
        "of the first register are greater or equal than the contents of the second "
447 
        "register, "
448 
        "then the compare flag is set; otherwise the compare flag is cleared.",
449 87 lampret 
        "flag <- rA[31:0] >= rB[31:0]",
450 
        "flag <- rA[63:0] >= rB[63:0]",
451 
        "None", ORBIS32I,},
452 14 lampret 
 
453 87 lampret 
{"l.sflts", "Set Flag if Less Than Signed",
454 
        "The contents of general-purpose register rA and the contents of general-purpose "
455 14 lampret 
        "register rB are compared as signed integers. If the contents "
456 
        "of the first register are less than the contents of the second "
457 
        "register, "
458 
        "then the compare flag is set; otherwise the compare flag is cleared.",
459 87 lampret 
        "flag <- rA[31:0] < rB[31:0]",
460 
        "flag <- rA[63:0] < rB[63:0]",
461 
        "None", ORBIS32I,},
462 14 lampret 
 
463 87 lampret 
{"l.sfles", "Set Flag if Less or Equal Than Signed",
464 
        "The contents of general-purpose register rA and the contents of general-purpose "
465 14 lampret 
        "register rB are compared as signed integers. If the contents "
466 
        "of the first register are less or equal than the contents of the second "
467 
        "register, "
468 
        "then the compare flag is set; otherwise the compare flag is cleared.",
469 87 lampret 
        "flag <- rA[31:0] <= rB[31:0]",
470 
        "flag <- rA[63:0] <= rB[63:0]",
471 
        "None", ORBIS32I,},
472 14 lampret 
 
473 87 lampret 
{"l.sfgtu", "Set Flag if Greater Than Unsigned",
474 
        "The contents of general-purpose register rA and the contents of general-purpose "
475 14 lampret 
        "register rB are compared as unsigned integers. If the contents "
476 
        "of the first register are greater than the contents of the second "
477 
        "register, "
478 
        "then the compare flag is set; otherwise the compare flag is cleared.",
479 87 lampret 
        "flag <- rA[31:0] > rB[31:0]",
480 
        "flag <- rA[63:0] > rB[63:0]",
481 
        "None", ORBIS32I,},
482 14 lampret 
 
483 87 lampret 
{"l.sfgeu", "Set Flag if Greater or Equal Than Unsigned",
484 
        "The contents of general-purpose register rA and the contents of general-purpose "
485 14 lampret 
        "register rB are compared as unsigned integers. If the contents "
486 
        "of the first register are greater or equal than the contents of the second "
487 
        "register, "
488 
        "then the compare flag is set; otherwise the compare flag is cleared.",
489 87 lampret 
        "flag <- rA[31:0] >= rB[31:0]",
490 
        "flag <- rA[63:0] >= rB[63:0]",
491 
        "None", ORBIS32I,},
492 14 lampret 
 
493 87 lampret 
{"l.sfltu", "Set Flag if Less Than Unsigned",
494 
        "The contents of general-purpose register rA and the contents of general-purpose "
495 14 lampret 
        "register rB are compared as unsigned integers. If the contents "
496 
        "of the first register are less than the contents of the second "
497 
        "register, "
498 
        "then the compare flag is set; otherwise the compare flag is cleared.",
499 87 lampret 
        "flag <- rA[31:0] < rB[31:0]",
500 
        "flag <- rA[63:0] < rB[63:0]",
501 
        "None", ORBIS32I,},
502 14 lampret 
 
503 87 lampret 
{"l.sfleu", "Set Flag if Less or Equal Than Unsigned",
504 
        "The contents of general-purpose register rA and the contents of general-purpose "
505 14 lampret 
        "register rB are compared as unsigned integers. If the contents "
506 
        "of the first register are less or equal than the contents of the second "
507 
        "register, "
508 
        "then the compare flag is set; otherwise the compare flag is cleared.",
509 87 lampret 
        "flag <- rA[31:0] <= rB[31:0]",
510 
        "flag <- rA[63:0] <= rB[63:0]",
511 
        "None", ORBIS32I,},
512 14 lampret 
 
513 87 lampret 
{"l.sfeqi", "Set Flag if Equal Immediate",
514 
        "The contents of general-purpose register rA and sign-extended immediate "
515 
        "are compared. If the two registers are equal, "
516 
        "then the compare flag is set; otherwise the compare flag is cleared.",
517 
        "flag <- rA[31:0] == rB[31:0]",
518 
        "flag <- rA[63:0] == rB[63:0]",
519 
        "None", ORBIS32II,},
520 14 lampret 
 
521 87 lampret 
{"l.sfnei", "Set Flag if Not Equal Immediate",
522 
        "The contents of general-purpose register rA and "
523 
        "sign-extended immediate are compared. If the two registers are not equal, "
524 
        "then the compare flag is set; otherwise the compare flag is cleared.",
525 
        "flag <- rA[31:0] != rB[31:0]",
526 
        "flag <- rA[63:0] != rB[63:0]",
527 
        "None", ORBIS32II,},
528 14 lampret 
 
529 87 lampret 
{"l.sfgtsi", "Set Flag if Greater Than Immediate Signed",
530 
        "The contents of general-purpose register rA and "
531 
        "sign-extended immediate are compared as signed integers. If the contents "
532 
        "of the first register are greater than the contents of the second "
533 
        "register, "
534 
        "then the compare flag is set; otherwise the compare flag is cleared.",
535 
        "flag <- rA[31:0] > rB[31:0]",
536 
        "flag <- rA[63:0] > rB[63:0]",
537 
        "None", ORBIS32II,},
538 14 lampret 
 
539 87 lampret 
{"l.sfgesi", "Set Flag if Greater or Equal Than Immediate Signed",
540 
        "The contents of general-purpose register rA and "
541 
        "sign-extended immediate are compared as signed integers. If the contents "
542 
        "of the first register are greater or equal than the contents of the second "
543 
        "register, "
544 
        "then the compare flag is set; otherwise the compare flag is cleared.",
545 
        "flag <- rA[31:0] >= rB[31:0]",
546 
        "flag <- rA[63:0] >= rB[63:0]",
547 
        "None", ORBIS32II,},
548 14 lampret 
 
549 87 lampret 
{"l.sfltsi", "Set Flag if Less Than Immediate Signed",
550 
        "The contents of general-purpose register rA and "
551 
        "sign-extended immediate are compared as signed integers. If the contents "
552 
        "of the first register are less than the contents of the second "
553 
        "register, "
554 
        "then the compare flag is set; otherwise the compare flag is cleared.",
555 
        "flag <- rA[31:0] < rB[31:0]",
556 
        "flag <- rA[63:0] < rB[63:0]",
557 
        "None", ORBIS32II,},
558 14 lampret 
 
559 87 lampret 
{"l.sflesi", "Set Flag if Less or Equal Than Immediate Signed",
560 
        "The contents of general-purpose register rA and "
561 
        "sign-extended immediate are compared as signed integers. If the contents "
562 
        "of the first register are less or equal than the contents of the second "
563 
        "register, "
564 
        "then the compare flag is set; otherwise the compare flag is cleared.",
565 
        "flag <- rA[31:0] <= rB[31:0]",
566 
        "flag <- rA[63:0] <= rB[63:0]",
567 
        "None", ORBIS32II,},
568 14 lampret 
 
569 87 lampret 
{"l.sfgtui", "Set Flag if Greater Than Immediate Unsigned",
570 
        "The contents of general-purpose register rA and "
571 
        "zero-extended immediate are compared as unsigned integers. If the contents "
572 
        "of the first register are greater than the contents of the second "
573 
        "register, "
574 
        "then the compare flag is set; otherwise the compare flag is cleared.",
575 
        "flag <- rA[31:0] > rB[31:0]",
576 
        "flag <- rA[63:0] > rB[63:0]",
577 
        "None", ORBIS32II,},
578 14 lampret 
 
579 87 lampret 
{"l.sfgeui", "Set Flag if Greater or Equal Than Immediate Unsigned",
580 
        "The contents of general-purpose register rA and "
581 
        "zero-extended immediate are compared as unsigned integers. If the contents "
582 
        "of the first register are greater or equal than the contents of the second "
583 
        "register, "
584 
        "then the compare flag is set; otherwise the compare flag is cleared.",
585 
        "flag <- rA[31:0] >= rB[31:0]",
586 
        "flag <- rA[63:0] >= rB[63:0]",
587 
        "None", ORBIS32II,},
588 
 
589 
{"l.sfltui", "Set Flag if Less Than Immediate Unsigned",
590 
        "The contents of general-purpose register rA and "
591 
        "zero-extended immediate are compared as unsigned integers. If the contents "
592 
        "of the first register are less than the contents of the second "
593 
        "register, "
594 
        "then the compare flag is set; otherwise the compare flag is cleared.",
595 
        "flag <- rA[31:0] < rB[31:0]",
596 
        "flag <- rA[63:0] < rB[63:0]",
597 
        "None", ORBIS32II,},
598 
 
599 
{"l.sfleui", "Set Flag if Less or Equal Than Immediate Unsigned",
600 
        "The contents of general-purpose register rA and "
601 
        "zero-extended immediate are compared as unsigned integers. If the contents "
602 
        "of the first register are less or equal than the contents of the second "
603 
        "register, "
604 
        "then the compare flag is set; otherwise the compare flag is cleared.",
605 
        "flag <- rA[31:0] <= rB[31:0]",
606 
        "flag <- rA[63:0] <= rB[63:0]",
607 
        "None", ORBIS32II,},
608 
 
609 95 lampret 
{"l.mtspr", "Move To Special-Purpose Register",
610 87 lampret 
        "The contents of general-purpose register rB are moved into special register "
611 
        "identified by the sum of general-purpose register rA and zero-extended immediate.",
612 
        "spr(rA+extz(Immediate)) <- rA[31:0]",
613 
        "spr(rA+extz(Immediate)) <- rA[31:0]",
614 
        "None", ORBIS32I,},
615 
 
616 95 lampret 
{"l.mfspr", "Move From Special-Purpose Register",
617 87 lampret 
        "The contents of special register identified by the sum of general-purpose rA and "
618 
        "zero-extended immediate are moved into general-purpose register rD.",
619 
        "rD[31:0] <- spr(rA+extz(Immediate))",
620 
        "rD[63:0] <- spr(rA+extz(Immediate))",
621 
        "None", ORBIS32I,},
622 
 
623 
{"l.nop", "No Operation",
624 
        "This instruction does not do anything except it takes at least one "
625 
        "clock cycle to complete. It is often used to fill delay slot gaps.",
626 
        "",
627 
        "",
628 
        "None", ORBIS32I,},
629 
 
630 
{"l.movhi", "Move Immediate High",
631 
        "16-bit immediate is zero-extended, shifted left by 16 bits and placed "
632 
        "into general-purpose register rD.",
633 
        "rA[31:0] <- extz(Immediate) << 16",
634 
        "rA[63:0] <- extz(Immediate) << 16",
635 
        "None", ORBIS32I,},
636 
 
637 14 lampret 
{"l.bf", "Branch if Flag",
638 
        "The immediate is shifted left two bits, sign-extended to "
639 87 lampret 
        "program counter width and then added to the address of the delay slot. The result "
640 14 lampret 
        "is effective address of the branch. If the compare flag is set, "
641 
        "then the program branches "
642 87 lampret 
        "to EA with a delay of one instruction.",
643 14 lampret 
        "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set",
644 87 lampret 
        "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set",
645 
        "None", ORBIS32I,},
646 14 lampret 
 
647 
{"l.bnf", "Branch if No Flag",
648 
        "The immediate is shifted left two bits, sign-extended to "
649 87 lampret 
        "program counter width and then added to the address of the delay slot. The result "
650 14 lampret 
        "is effective address of the branch. If the compare flag is cleared, "
651 
        "then the program branches "
652 87 lampret 
        "to EA with a delay of one instruction.",
653 14 lampret 
        "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared",
654 
        "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared",
655 87 lampret 
        "None", ORBIS32I,},
656 14 lampret 
 
657 
{"l.jal", "Jump and Link",
658 
        "The immediate is shifted left two bits, sign-extended to "
659 87 lampret 
        "program counter width and then added to the address of the delay slot. The result "
660 14 lampret 
        "is effective address of the jump. The program unconditionally jumps "
661 87 lampret 
        "to EA with a delay of one instruction. The "
662 14 lampret 
        "address of the instruction after the delay slot is placed in the "
663 
        "link register. ",
664 87 lampret 
        "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
665 
        "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
666 
        "None", ORBIS32I,},
667 14 lampret 
 
668 
{"l.j", "Jump",
669 
        "The immediate is shifted left two bits, sign-extended to "
670 87 lampret 
        "program counter width and then added to the address of the delay slot. The result "
671 14 lampret 
        "is effective address of the jump. The program unconditionally jumps "
672 87 lampret 
        "to EA with a delay of one instruction.",
673 
        "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
674 
        "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
675 
        "None", ORBIS32I,},
676 14 lampret 
 
677 87 lampret 
{"l.jalr", "Jump and Link Register",
678 
        "The contents of general-purpose register rB "
679 14 lampret 
        "is effective address of the jump. The program unconditionally jumps "
680 87 lampret 
        "to EA with a delay of one instruction. The "
681 14 lampret 
        "address of the instruction after the delay slot is placed in the "
682 87 lampret 
        "link register.",
683 
        "PC <- rB\\LR <- DelayInsnAddr + 4",
684 
        "PC <- rB\\LR <- DelayInsnAddr + 4",
685 
        "None", ORBIS32I,},
686 14 lampret 
 
687 87 lampret 
{"l.jr", "Jump Register",
688 
        "The contents of general-purpose register rB "
689 14 lampret 
        "is effective address of the jump. The program unconditionally jumps "
690 87 lampret 
        "to EA with a delay of one instruction.",
691 
        "PC <- rB",
692 
        "PC <- rB",
693 
        "None", ORBIS32I,},
694 14 lampret 
 
695 87 lampret 
{"l.sys", "System Call",
696 
        "Execution of system call instruction results in the system call "
697 
        "exception. System calls exception is a request to the operating system "
698 95 lampret 
        "to provide operating system services. Immediate specifies which system service "
699 87 lampret 
        "is required.",
700 
        "system-call-exception(K)",
701 
        "system-call-exception(K)",
702 
        "None", ORBIS32I,},
703 14 lampret 
 
704 95 lampret 
{"l.brk", "Breakpoint",
705 
        "Execution of the breakpoint instruction results in the breakpoint "
706 
        "exception. Breakpoint exception is a request to the operating system "
707 
        "and to the debug facility to execute certain debug services. "
708 
        "Immediate is used by the debug to identify which breakpoint it is. ",
709 
        "breakpoint-exception(K)",
710 
        "breakpoint-exception(K)",
711 
        "None", ORBIS32I,},
712 
 
713 89 lampret 
{"l.msync", "Memory Syncronization",
714 
        "Execution of memory synchronization instruction results in completion "
715 
        "of all load/store operations before the RISC core continues.",
716 
        "memory-synchronization",
717 
        "memory-synchronization",
718 
        "None", ORBIS32II,},
719 
 
720 95 lampret 
{"l.psync", "Pipeline Syncronization",
721 
        "Execution of pipeline synchronization instruction results in completion "
722 
        "of all instructions that were fetched before l.psync instruction. Once all "
723 
        "instructions are completed, instructions fetched after l.psync are flushed from the "
724 
        " pipeline and fetched again.",
725 
        "pipeline-synchronization",
726 
        "pipeline-synchronization",
727 
        "None", ORBIS32II,},
728 
 
729 
{"l.csync", "Context Syncronization",
730 
        "Execution of context synchronization instruction results in completion "
731 
        "of all operations inside RISC and flush of the instruction pipelines. "
732 
        "When all operations are complete, RISC core resumes with empty instruction pipeline and "
733 
        "fresh context in all units (MMU for example).",
734 
        "context-synchronization",
735 
        "context-synchronization",
736 
        "None", ORBIS32II,},
737 
 
738 87 lampret 
{"l.rfe", "Return From Exception",
739 
        "Execution of this instruction restores the state of the processor prior to "
740 
        "the exception.",
741 
        "state_restore()",
742 
        "state_restore()",
743 
        "None", ORBIS32I,},
744 14 lampret 
 
745 95 lampret 
{"l.cust1", "Reserved for ORBIS32/64 Custom Instructions",
746 
        "This fake instruction only allocates instruction set space for custom instructions. "
747 
        "Custom instructions are those that are not defined by the architecture, but instead "
748 
        "by the implementation itself.",
749 
        "N/A",
750 
        "N/A",
751 
        "N/A", ORBIS32II,},
752 
 
753 
{"l.cust2", "Reserved for ORBIS32/64 Custom Instructions",
754 
        "This fake instruction only allocates instruction set space for custom instructions. "
755 
        "Custom instructions are those that are not defined by the architecture, but instead "
756 
        "by the implementation itself.",
757 
        "N/A",
758 
        "N/A",
759 
        "N/A", ORBIS32II,},
760 
 
761 
{"l.cust3", "Reserved for ORBIS32/64 Custom Instructions",
762 
        "This fake instruction only allocates instruction set space for custom instructions. "
763 
        "Custom instructions are those that are not defined by the architecture, but instead "
764 
        "by the implementation itself.",
765 
        "N/A",
766 
        "N/A",
767 
        "N/A", ORBIS32II,},
768 
 
769 
{"l.cust4", "Reserved for ORBIS32/64 Custom Instructions",
770 
        "This fake instruction only allocates instruction set space for custom instructions. "
771 
        "Custom instructions are those that are not defined by the architecture, but instead "
772 
        "by the implementation itself.",
773 
        "N/A",
774 
        "N/A",
775 
        "N/A", ORBIS32II,},
776 
 
777 
{"l.cust5", "Reserved for ORBIS32/64 Custom Instructions",
778 
        "This fake instruction only allocates instruction set space for custom instructions. "
779 
        "Custom instructions are those that are not defined by the architecture, but instead "
780 
        "by the implementation itself.",
781 
        "N/A",
782 
        "N/A",
783 
        "N/A", ORBIS32II,},
784 
 
785 
{"l.cust6", "Reserved for ORBIS32/64 Custom Instructions",
786 
        "This fake instruction only allocates instruction set space for custom instructions. "
787 
        "Custom instructions are those that are not defined by the architecture, but instead "
788 
        "by the implementation itself.",
789 
        "N/A",
790 
        "N/A",
791 
        "N/A", ORBIS32II,},
792 
 
793 
{"l.cust7", "Reserved for ORBIS32/64 Custom Instructions",
794 
        "This fake instruction only allocates instruction set space for custom instructions. "
795 
        "Custom instructions are those that are not defined by the architecture, but instead "
796 
        "by the implementation itself.",
797 
        "N/A",
798 
        "N/A",
799 
        "N/A", ORBIS32II,},
800 
 
801 
{"l.cust8", "Reserved for ORBIS32/64 Custom Instructions",
802 
        "This fake instruction only allocates instruction set space for custom instructions. "
803 
        "Custom instructions are those that are not defined by the architecture, but instead "
804 
        "by the implementation itself.",
805 
        "N/A",
806 
        "N/A",
807 
        "N/A", ORBIS32II,},
808 
 
809 87 lampret 
/*** ORFPX32 ***/
810 14 lampret 
 
811 87 lampret 
{"lf.add.s", "Add Floating-Point Single-Precision",
812 
        "The contents of vector/floating-point register vfrA is added to the contents "
813 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
814 
        "vector/floating-point register vfrD.",
815 
        "vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]",
816 
        "",
817 
        "", ORFPX32I,},
818 14 lampret 
 
819 87 lampret 
{"lf.sub.s", "Subtract Floating-Point Single-Precision",
820 
        "The contents of vector/floating-point register vfrB is subtracted from the contents "
821 
        "of vector/floating-point register vfrA to form the result. The result is placed into "
822 
        "vector/floating-point register vfrD.",
823 
        "vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]",
824 
        "",
825 
        "", ORFPX32I,},
826 14 lampret 
 
827 87 lampret 
{"lf.mul.s", "Multiply Floating-Point Single-Precision",
828 
        "The contents of vector/floating-point register vfrA is multiplied by the contents "
829 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
830 
        "vector/floating-point register vfrD.",
831 
        "vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]",
832 
        "",
833 
        "", ORFPX32I,},
834 14 lampret 
 
835 87 lampret 
{"lf.div.s", "Divide Floating-Point Single-Precision",
836 
        "The contents of vector/floating-point register vfrA is divided by the contents "
837 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
838 
        "vector/floating-point register vfrD.",
839 
        "vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]",
840 
        "",
841 
        "", ORFPX32II,},
842 14 lampret 
 
843 87 lampret 
{"lf.rem.s", "Remainder Floating-Point Single-Precision",
844 
        "The contents of vector/floating-point register vfrA is divided by the contents "
845 
        "of vector/floating-point register vfrB and remainder is used as the result. The result is placed into "
846 
        "vector/floating-point register vfrD.",
847 
        "vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]",
848 
        "",
849 
        "", ORFPX32II,},
850 14 lampret 
 
851 87 lampret 
{"lf.madd.s", "Multiply and Add Floating-Point Single-Precision",
852 
        "The contents of vector/floating-point register vfrA is multiplied by the contents "
853 
        "of vector/floating-point register vfrB and added to special-purpose register "
854 
        "FPMADDLO/FPMADDHI.",
855 
        "FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
856 
        "",
857 
        "", ORFPX32II,},
858 14 lampret 
 
859 87 lampret 
{"lf.sfeq.s", "Set Flag if Equal Floating-Point Single-Precision",
860 
        "The contents of vector/floating-point register vfrA and the contents of "
861 
        "vector/floating-point register vfrB are compared. If the two registers are equal, "
862 
        "then the compare flag is set; otherwise the compare flag is cleared.",
863 
        "flag <- vfrA[31:0] == vfrB[31:0]",
864 
        "",
865 
        "None", ORFPX32I,},
866 14 lampret 
 
867 87 lampret 
{"lf.sfne.s", "Set Flag if Not Equal Floating-Point Single-Precision",
868 
        "The contents of vector/floating-point register vfrA and the contents of "
869 
        "vector/floating-point register vfrB are compared. If the two registers are not equal, "
870 
        "then the compare flag is set; otherwise the compare flag is cleared.",
871 
        "flag <- vfrA[31:0] != vfrB[31:0]",
872 
        "",
873 
        "None", ORFPX32I,},
874 14 lampret 
 
875 87 lampret 
{"lf.sfgt.s", "Set Flag if Greater Than Floating-Point Single-Precision",
876 
        "The contents of vector/floating-point register vfrA and the contents of "
877 
        "vector/floating-point register vfrB are compared. If first register is greater than "
878 
        "second register, then the compare flag is set; otherwise the compare flag is cleared.",
879 
        "flag <- vfrA[31:0] > vfrB[31:0]",
880 
        "",
881 
        "None", ORFPX32I,},
882 14 lampret 
 
883 87 lampret 
{"lf.sfge.s", "Set Flag if Greater or Equal Than Floating-Point Single-Precision",
884 
        "The contents of vector/floating-point register vfrA and the contents of "
885 
        "vector/floating-point register vfrB are compared. If first register is greater "
886 
        "or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
887 
        "flag <- vfrA[31:0] >= vfrB[31:0]",
888 
        "",
889 
        "None", ORFPX32I,},
890 14 lampret 
 
891 87 lampret 
{"lf.sflt.s", "Set Flag if Less Than Floating-Point Single-Precision",
892 
        "The contents of vector/floating-point register vfrA and the contents of "
893 
        "vector/floating-point register vfrB are compared. If first register is less than "
894 
        "second register, then the compare flag is set; otherwise the compare flag is cleared.",
895 
        "flag <- vfrA[31:0] < vfrB[31:0]",
896 
        "",
897 
        "None", ORFPX32I,},
898 
 
899 
{"lf.sfle.s", "Set Flag if Less or Equal Than Floating-Point Single-Precision",
900 
        "The contents of vector/floating-point register vfrA and the contents of "
901 
        "vector/floating-point register vfrB are compared. If first register is less "
902 
        "or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
903 
        "flag <- vfrA[31:0] <= vfrB[31:0]",
904 
        "",
905 
        "None", ORFPX32I,},
906 
 
907 
{"lf.ftoi.s", "Floating-Point Single-Precision To Integer",
908 
        "The contents of vector/floating-point register vfrA are converted to integer "
909 
        "and stored into general-purpose register rD.",
910 
        "rD[31:0] <- ftoi(vfrA[31:0])",
911 
        "",
912 
        "None", ORFPX32I,},
913 
 
914 
{"lf.itof.s", "Integer To Floating-Point Single-Precision",
915 
        "The contents of general-purpose register rA are converted to single-precision "
916 
        "floating-point number and stored into vector/floating-point register vfrD.",
917 
        "vfrD[31:0] <- itof(rA[31:0])",
918 
        "",
919 
        "None", ORFPX32I,},
920 
 
921 95 lampret 
{"lf.cust1.s", "Reserved for ORFPX32 Custom Instructions",
922 
        "This fake instruction only allocates instruction set space for custom instructions. "
923 
        "Custom instructions are those that are not defined by the architecture, but instead "
924 
        "by the implementation itself.",
925 
        "N/A",
926 
        "N/A",
927 
        "N/A", ORFPX32II,},
928 
 
929 87 lampret 
/*** ORFPX64 ***/
930 
 
931 
{"lf.add.d", "Add Floating-Point Double-Precision",
932 
        "The contents of vector/floating-point register vfrA is added to the contents "
933 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
934 
        "vector/floating-point register vfrD.",
935 
        "",
936 
        "vfrD[63:0] <- vfrA[63:0] + vfrB[63:0]",
937 
        "", ORFPX64I,},
938 
 
939 
{"lf.sub.d", "Subtract Floating-Point Double-Precision",
940 
        "The contents of vector/floating-point register vfrB is subtracted from the contents "
941 
        "of vector/floating-point register vfrA to form the result. The result is placed into "
942 
        "vector/floating-point register vfrD.",
943 
        "",
944 
        "vfrD[63:0] <- vfrA[63:0] - vfrB[63:0]",
945 
        "", ORFPX64I,},
946 
 
947 
{"lf.mul.d", "Multiply Floating-Point Double-Precision",
948 
        "The contents of vector/floating-point register vfrA is multiplied by the contents "
949 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
950 
        "vector/floating-point register vfrD.",
951 
        "",
952 
        "vfrD[63:0] <- vfrA[63:0] * vfrB[63:0]",
953 
        "", ORFPX64I,},
954 
 
955 
{"lf.div.d", "Divide Floating-Point Double-Precision",
956 
        "The contents of vector/floating-point register vfrA is divided by the contents "
957 
        "of vector/floating-point register vfrB to form the result. The result is placed into "
958 
        "vector/floating-point register vfrD.",
959 
        "",
960 
        "vfrD[63:0] <- vfrA[63:0] / vfrB[63:0]",
961 
        "", ORFPX64II,},
962 
 
963 
{"lf.rem.d", "Remainder Floating-Point Double-Precision",
964 
        "The contents of vector/floating-point register vfrA is divided by the contents "
965 
        "of vector/floating-point register vfrB and remainder is used as the result. The result is placed into "
966 
        "vector/floating-point register vfrD.",
967 
        "",
968 
        "vfrD[63:0] <- vfrA[63:0] % vfrB[63:0]",
969 
        "", ORFPX64II,},
970 
 
971 
{"lf.madd.d", "Multiply and Add Floating-Point Double-Precision",
972 
        "The contents of vector/floating-point register vfrA is multiplied by the contents "
973 
        "of vector/floating-point register vfrB and added to special-purpose register "
974 
        "FPMADDLO/FPMADDHI.",
975 
        "",
976 
        "FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[63:0] * vfrB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
977 
        "", ORFPX64II,},
978 
 
979 
{"lf.sfeq.d", "Set Flag if Equal Floating-Point Double-Precision",
980 
        "The contents of vector/floating-point register vfrA and the contents of "
981 
        "vector/floating-point register vfrB are compared. If the two registers are equal, "
982 
        "then the compare flag is set; otherwise the compare flag is cleared.",
983 
        "",
984 
        "flag <- vfrA[63:0] == vfrB[63:0]",
985 
        "None", ORFPX64I,},
986 
 
987 
{"lf.sfne.d", "Set Flag if Not Equal Floating-Point Double-Precision",
988 
        "The contents of vector/floating-point register vfrA and the contents of "
989 
        "vector/floating-point register vfrB are compared. If the two registers are not equal, "
990 
        "then the compare flag is set; otherwise the compare flag is cleared.",
991 
        "",
992 
        "flag <- vfrA[63:0] != vfrB[63:0]",
993 
        "None", ORFPX64I,},
994 
 
995 
{"lf.sfgt.d", "Set Flag if Greater Than Floating-Point Double-Precision",
996 
        "The contents of vector/floating-point register vfrA and the contents of "
997 
        "vector/floating-point register vfrB are compared. If first register is greater than "
998 
        "second register, then the compare flag is set; otherwise the compare flag is cleared.",
999 
        "",
1000 
        "flag <- vfrA[63:0] > vfrB[63:0]",
1001 
        "None", ORFPX64I,},
1002 
 
1003 
{"lf.sfge.d", "Set Flag if Greater or Equal Than Floating-Point Double-Precision",
1004 
        "The contents of vector/floating-point register vfrA and the contents of "
1005 
        "vector/floating-point register vfrB are compared. If first register is greater "
1006 
        "or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
1007 
        "",
1008 
        "flag <- vfrA[63:0] >= vfrB[63:0]",
1009 
        "None", ORFPX64I,},
1010 
 
1011 
{"lf.sflt.d", "Set Flag if Less Than Floating-Point Double-Precision",
1012 
        "The contents of vector/floating-point register vfrA and the contents of "
1013 
        "vector/floating-point register vfrB are compared. If first register is less than "
1014 
        "second register, then the compare flag is set; otherwise the compare flag is cleared.",
1015 
        "",
1016 
        "flag <- vfrA[63:0] < vfrB[63:0]",
1017 
        "None", ORFPX64I,},
1018 
 
1019 
{"lf.sfle.d", "Set Flag if Less or Equal Than Floating-Point Double-Precision",
1020 
        "The contents of vector/floating-point register vfrA and the contents of "
1021 
        "vector/floating-point register vfrB are compared. If first register is less "
1022 
        "or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
1023 
        "",
1024 
        "flag <- vfrA[363:0] <= vfrB[63:0]",
1025 
        "None", ORFPX64I,},
1026 
 
1027 
{"lf.ftoi.d", "Floating-Point Double-Precision To Integer",
1028 
        "The contents of vector/floating-point register vfrA are converted to integer "
1029 
        "and stored into general-purpose register rD.",
1030 
        "",
1031 
        "rD[63:0] <- ftoi(vfrA[63:0])",
1032 
        "None", ORFPX64I,},
1033 
 
1034 
{"lf.itof.d", "Integer To Floating-Point Double-Precision",
1035 
        "The contents of general-purpose register rA are converted to Double-precision "
1036 
        "floating-point number and stored into vector/floating-point register vfrD.",
1037 
        "",
1038 
        "vfrD[63:0] <- itof(rA[63:0])",
1039 
        "None", ORFPX64I,},
1040 
 
1041 95 lampret 
{"lf.cust1.d", "Reserved for ORFPX64 Custom Instructions",
1042 
        "This fake instruction only allocates instruction set space for custom instructions. "
1043 
        "Custom instructions are those that are not defined by the architecture, but instead "
1044 
        "by the implementation itself.",
1045 
        "N/A",
1046 
        "N/A",
1047 
        "N/A", ORFPX64II,},
1048 
 
1049 87 lampret 
/*** ORVDX64 ***/
1050 
 
1051 
{"lv.all_eq.b", "Vector Byte Elements All Equal",
1052 
        "All byte elements of vector/floating-point register vfrA are compared "
1053 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1054 
        "set if all corresponding elements are equal; otherwise compare flag is cleared. "
1055 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1056 
        "register vfrD.",
1057 
        "",
1058 
        "flag <- vfrA[7:0] == vfrB[7:0] \\"
1059 
        "\tvfrA[15:8] == vfrB[15:8] \\"
1060 
        "\tvfrA[23:16] == vfrB[23:16] \\"
1061 
        "\tvfrA[31:24] == vfrB[31:24] \\"
1062 
        "\tvfrA[39:32] == vfrB[39:32] \\"
1063 
        "\tvfrA[47:40] == vfrB[47:40] \\"
1064 
        "\tvfrA[55:48] == vfrB[55:48] \\"
1065 
        "\tvfrA[63:56] == vfrB[63:56]"
1066 
        "vfrD[63:0] <- repl(flag)",
1067 
        "None", ORVDX64I,},
1068 
 
1069 
{"lv.all_eq.h", "Vector Half-Word Elements All Equal",
1070 
        "All half-word elements of vector/floating-point register vfrA are compared "
1071 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1072 
        "set if all corresponding elements are equal; otherwise compare flag is cleared. "
1073 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1074 
        "register vfrD.",
1075 
        "",
1076 
        "flag <- vfrA[15:0] == vfrB[15:0] \\"
1077 
        "\tvfrA[31:16] == vfrB[31:16] \\"
1078 
        "\tvfrA[47:32] == vfrB[47:32] \\"
1079 
        "\tvfrA[63:48] == vfrB[63:48]"
1080 
        "vfrD[63:0] <- repl(flag)",
1081 
        "None", ORVDX64I,},
1082 
 
1083 
{"lv.all_ge.b", "Vector Byte Elements All Greater or Equal Than",
1084 
        "All byte elements of vector/floating-point register vfrA are compared "
1085 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1086 
        "set if all elements of vfrA are greater or equal than elements of vfrB;"
1087 
        "otherwise compare flag is cleared. "
1088 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1089 
        "register vfrD.",
1090 
        "",
1091 
        "flag <- vfrA[7:0] >= vfrB[7:0] \\"
1092 
        "\tvfrA[15:8] >= vfrB[15:8] \\"
1093 
        "\tvfrA[23:16] >= vfrB[23:16] \\"
1094 
        "\tvfrA[31:24] >= vfrB[31:24] \\"
1095 
        "\tvfrA[39:32] >= vfrB[39:32] \\"
1096 
        "\tvfrA[47:40] >= vfrB[47:40] \\"
1097 
        "\tvfrA[55:48] >= vfrB[55:48] \\"
1098 
        "\tvfrA[63:56] >= vfrB[63:56]"
1099 
        "vfrD[63:0] <- repl(flag)",
1100 
        "None", ORVDX64I,},
1101 
 
1102 
{"lv.all_ge.h", "Vector Half-Word Elements All Greater or Equal Than",
1103 
        "All half-word elements of vector/floating-point register vfrA are compared "
1104 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1105 
        "set if all elements of vfrA are greater or equal than elements of vfrB;"
1106 
        "otherwise compare flag is cleared. "
1107 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1108 
        "register vfrD.",
1109 
        "",
1110 
        "flag <- vfrA[15:0] >= vfrB[15:0] \\"
1111 
        "\tvfrA[31:16] >= vfrB[31:16] \\"
1112 
        "\tvfrA[47:32] >= vfrB[47:32] \\"
1113 
        "\tvfrA[63:48] >= vfrB[63:48]"
1114 
        "vfrD[63:0] <- repl(flag)",
1115 
        "None", ORVDX64I,},
1116 
 
1117 
{"lv.all_gt.b", "Vector Byte Elements All Greater Than",
1118 
        "All byte elements of vector/floating-point register vfrA are compared "
1119 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1120 
        "set if all elements of vfrA are greater than elements of vfrB;"
1121 
        "otherwise compare flag is cleared. "
1122 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1123 
        "register vfrD.",
1124 
        "",
1125 
        "flag <- vfrA[7:0] > vfrB[7:0] \\"
1126 
        "\tvfrA[15:8] > vfrB[15:8] \\"
1127 
        "\tvfrA[23:16] > vfrB[23:16] \\"
1128 
        "\tvfrA[31:24] > vfrB[31:24] \\"
1129 
        "\tvfrA[39:32] > vfrB[39:32] \\"
1130 
        "\tvfrA[47:40] > vfrB[47:40] \\"
1131 
        "\tvfrA[55:48] > vfrB[55:48] \\"
1132 
        "\tvfrA[63:56] > vfrB[63:56]"
1133 
        "vfrD[63:0] <- repl(flag)",
1134 
        "None", ORVDX64I,},
1135 
 
1136 
{"lv.all_gt.h", "Vector Half-Word Elements All Greater Than",
1137 
        "All half-word elements of vector/floating-point register vfrA are compared "
1138 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1139 
        "set if all elements of vfrA are greater than elements of vfrB;"
1140 
        "otherwise compare flag is cleared. "
1141 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1142 
        "register vfrD.",
1143 
        "",
1144 
        "flag <- vfrA[15:0] > vfrB[15:0] \\"
1145 
        "\tvfrA[31:16] > vfrB[31:16] \\"
1146 
        "\tvfrA[47:32] > vfrB[47:32] \\"
1147 
        "\tvfrA[63:48] > vfrB[63:48]"
1148 
        "vfrD[63:0] <- repl(flag)",
1149 
        "None", ORVDX64I,},
1150 
 
1151 
{"lv.all_lt.b", "Vector Byte Elements All Less Than",
1152 
        "All byte elements of vector/floating-point register vfrA are compared "
1153 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1154 
        "set if all elements of vfrA are less than elements of vfrB;"
1155 
        "otherwise compare flag is cleared. "
1156 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1157 
        "register vfrD.",
1158 
        "",
1159 
        "flag <- vfrA[7:0] < vfrB[7:0] \\"
1160 
        "\tvfrA[15:8] < vfrB[15:8] \\"
1161 
        "\tvfrA[23:16] < vfrB[23:16] \\"
1162 
        "\tvfrA[31:24] < vfrB[31:24] \\"
1163 
        "\tvfrA[39:32] < vfrB[39:32] \\"
1164 
        "\tvfrA[47:40] < vfrB[47:40] \\"
1165 
        "\tvfrA[55:48] < vfrB[55:48] \\"
1166 
        "\tvfrA[63:56] < vfrB[63:56]"
1167 
        "vfrD[63:0] <- repl(flag)",
1168 
        "None", ORVDX64I,},
1169 
 
1170 
{"lv.all_lt.h", "Vector Half-Word Elements All Less Than",
1171 
        "All half-word elements of vector/floating-point register vfrA are compared "
1172 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1173 
        "set if all elements of vfrA are less than elements of vfrB;"
1174 
        "otherwise compare flag is cleared. "
1175 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1176 
        "register vfrD.",
1177 
        "",
1178 
        "flag <- vfrA[15:0] < vfrB[15:0] \\"
1179 
        "\tvfrA[31:16] < vfrB[31:16] \\"
1180 
        "\tvfrA[47:32] < vfrB[47:32] \\"
1181 
        "\tvfrA[63:48] < vfrB[63:48]"
1182 
        "vfrD[63:0] <- repl(flag)",
1183 
        "None", ORVDX64I,},
1184 
 
1185 
{"lv.all_le.b", "Vector Byte Elements All Less or Equal Than",
1186 
        "All byte elements of vector/floating-point register vfrA are compared "
1187 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1188 
        "set if all elements of vfrA are less or equal than elements of vfrB;"
1189 
        "otherwise compare flag is cleared. "
1190 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1191 
        "register vfrD.",
1192 
        "",
1193 
        "flag <- vfrA[7:0] <= vfrB[7:0] \\"
1194 
        "\tvfrA[15:8] <= vfrB[15:8] \\"
1195 
        "\tvfrA[23:16] <= vfrB[23:16] \\"
1196 
        "\tvfrA[31:24] <= vfrB[31:24] \\"
1197 
        "\tvfrA[39:32] <= vfrB[39:32] \\"
1198 
        "\tvfrA[47:40] <= vfrB[47:40] \\"
1199 
        "\tvfrA[55:48] <= vfrB[55:48] \\"
1200 
        "\tvfrA[63:56] <= vfrB[63:56]"
1201 
        "vfrD[63:0] <- repl(flag)",
1202 
        "None", ORVDX64I,},
1203 
 
1204 
{"lv.all_le.h", "Vector Half-Word Elements All Less or Equal Than",
1205 
        "All half-word elements of vector/floating-point register vfrA are compared "
1206 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1207 
        "set if all elements of vfrA are less or equal than elements of vfrB;"
1208 
        "otherwise compare flag is cleared. "
1209 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1210 
        "register vfrD.",
1211 
        "",
1212 
        "flag <- vfrA[15:0] ,= vfrB[15:0] \\"
1213 
        "\tvfrA[31:16] <= vfrB[31:16] \\"
1214 
        "\tvfrA[47:32] <= vfrB[47:32] \\"
1215 
        "\tvfrA[63:48] <= vfrB[63:48]"
1216 
        "vfrD[63:0] <- repl(flag)",
1217 
        "None", ORVDX64I,},
1218 
 
1219 
{"lv.all_ne.b", "Vector Byte Elements All Not Equal",
1220 
        "All byte elements of vector/floating-point register vfrA are compared "
1221 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1222 
        "set if all corresponding elements are not equal; otherwise compare flag is cleared. "
1223 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1224 
        "register vfrD.",
1225 
        "",
1226 
        "flag <- vfrA[7:0] != vfrB[7:0] \\"
1227 
        "\tvfrA[15:8] != vfrB[15:8] \\"
1228 
        "\tvfrA[23:16] != vfrB[23:16] \\"
1229 
        "\tvfrA[31:24] != vfrB[31:24] \\"
1230 
        "\tvfrA[39:32] != vfrB[39:32] \\"
1231 
        "\tvfrA[47:40] != vfrB[47:40] \\"
1232 
        "\tvfrA[55:48] != vfrB[55:48] \\"
1233 
        "\tvfrA[63:56] != vfrB[63:56]"
1234 
        "vfrD[63:0] <- repl(flag)",
1235 
        "None", ORVDX64I,},
1236 
 
1237 
{"lv.all_ne.h", "Vector Half-Word Elements All Not Equal",
1238 
        "All half-word elements of vector/floating-point register vfrA are compared "
1239 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1240 
        "set if all corresponding elements are not equal; otherwise compare flag is cleared. "
1241 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1242 
        "register vfrD.",
1243 
        "",
1244 
        "flag <- vfrA[15:0] != vfrB[15:0] \\"
1245 
        "\tvfrA[31:16] != vfrB[31:16] \\"
1246 
        "\tvfrA[47:32] != vfrB[47:32] \\"
1247 
        "\tvfrA[63:48] != vfrB[63:48]"
1248 
        "vfrD[63:0] <- repl(flag)",
1249 
        "None", ORVDX64I,},
1250 
 
1251 
{"lv.any_eq.b", "Vector Byte Elements Any Equal",
1252 
        "All byte elements of vector/floating-point register vfrA are compared "
1253 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1254 
        "set if any two corresponding elements are equal; otherwise compare flag is cleared. "
1255 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1256 
        "register vfrD.",
1257 
        "",
1258 
        "flag <- vfrA[7:0] == vfrB[7:0] ||\\"
1259 
        "\tvfrA[15:8] == vfrB[15:8] ||\\"
1260 
        "\tvfrA[23:16] == vfrB[23:16] ||\\"
1261 
        "\tvfrA[31:24] == vfrB[31:24] ||\\"
1262 
        "\tvfrA[39:32] == vfrB[39:32] ||\\"
1263 
        "\tvfrA[47:40] == vfrB[47:40] ||\\"
1264 
        "\tvfrA[55:48] == vfrB[55:48] ||\\"
1265 
        "\tvfrA[63:56] == vfrB[63:56]"
1266 
        "vfrD[63:0] <- repl(flag)",
1267 
        "None", ORVDX64I,},
1268 
 
1269 
{"lv.any_eq.h", "Vector Half-Word Elements Any Equal",
1270 
        "All half-word elements of vector/floating-point register vfrA are compared "
1271 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1272 
        "set if any two corresponding elements are equal; otherwise compare flag is cleared. "
1273 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1274 
        "register vfrD.",
1275 
        "",
1276 
        "flag <- vfrA[15:0] == vfrB[15:0] ||\\"
1277 
        "\tvfrA[31:16] == vfrB[31:16] ||\\"
1278 
        "\tvfrA[47:32] == vfrB[47:32] ||\\"
1279 
        "\tvfrA[63:48] == vfrB[63:48]"
1280 
        "vfrD[63:0] <- repl(flag)",
1281 
        "None", ORVDX64I,},
1282 
 
1283 
{"lv.any_ge.b", "Vector Byte Elements Any Greater or Equal Than",
1284 
        "All byte elements of vector/floating-point register vfrA are compared "
1285 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1286 
        "set if any element of vfrA is greater or equal than corresponding element of vfrB;"
1287 
        "otherwise compare flag is cleared. "
1288 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1289 
        "register vfrD.",
1290 
        "",
1291 
        "flag <- vfrA[7:0] >= vfrB[7:0] ||\\"
1292 
        "\tvfrA[15:8] >= vfrB[15:8] ||\\"
1293 
        "\tvfrA[23:16] >= vfrB[23:16] ||\\"
1294 
        "\tvfrA[31:24] >= vfrB[31:24] ||\\"
1295 
        "\tvfrA[39:32] >= vfrB[39:32] ||\\"
1296 
        "\tvfrA[47:40] >= vfrB[47:40] ||\\"
1297 
        "\tvfrA[55:48] >= vfrB[55:48] ||\\"
1298 
        "\tvfrA[63:56] >= vfrB[63:56]"
1299 
        "vfrD[63:0] <- repl(flag)",
1300 
        "None", ORVDX64I,},
1301 
 
1302 
{"lv.any_ge.h", "Vector Half-Word Elements Any Greater or Equal Than",
1303 
        "All half-word elements of vector/floating-point register vfrA are compared "
1304 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1305 
        "set if any element of vfrA is greater or equal than corresponding element of vfrB;"
1306 
        "otherwise compare flag is cleared. "
1307 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1308 
        "register vfrD.",
1309 
        "",
1310 
        "flag <- vfrA[15:0] >= vfrB[15:0] ||\\"
1311 
        "\tvfrA[31:16] >= vfrB[31:16] ||\\"
1312 
        "\tvfrA[47:32] >= vfrB[47:32] ||\\"
1313 
        "\tvfrA[63:48] >= vfrB[63:48]"
1314 
        "vfrD[63:0] <- repl(flag)",
1315 
        "None", ORVDX64I,},
1316 
 
1317 
{"lv.any_gt.b", "Vector Byte Elements Any Greater Than",
1318 
        "All byte elements of vector/floating-point register vfrA are compared "
1319 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1320 
        "set if any element of vfrA is greater than corresponding element of vfrB;"
1321 
        "otherwise compare flag is cleared. "
1322 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1323 
        "register vfrD.",
1324 
        "",
1325 
        "flag <- vfrA[7:0] > vfrB[7:0] ||\\"
1326 
        "\tvfrA[15:8] > vfrB[15:8] ||\\"
1327 
        "\tvfrA[23:16] > vfrB[23:16] ||\\"
1328 
        "\tvfrA[31:24] > vfrB[31:24] ||\\"
1329 
        "\tvfrA[39:32] > vfrB[39:32] ||\\"
1330 
        "\tvfrA[47:40] > vfrB[47:40] ||\\"
1331 
        "\tvfrA[55:48] > vfrB[55:48] ||\\"
1332 
        "\tvfrA[63:56] > vfrB[63:56]"
1333 
        "vfrD[63:0] <- repl(flag)",
1334 
        "None", ORVDX64I,},
1335 
 
1336 
{"lv.any_gt.h", "Vector Half-Word Elements Any Greater Than",
1337 
        "All half-word elements of vector/floating-point register vfrA are compared "
1338 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1339 
        "set if any element of vfrA is greater than corresponding element of vfrB;"
1340 
        "otherwise compare flag is cleared. "
1341 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1342 
        "register vfrD.",
1343 
        "",
1344 
        "flag <- vfrA[15:0] > vfrB[15:0] ||\\"
1345 
        "\tvfrA[31:16] > vfrB[31:16] ||\\"
1346 
        "\tvfrA[47:32] > vfrB[47:32] ||\\"
1347 
        "\tvfrA[63:48] > vfrB[63:48]"
1348 
        "vfrD[63:0] <- repl(flag)",
1349 
        "None", ORVDX64I,},
1350 
 
1351 
{"lv.any_lt.b", "Vector Byte Elements Any Less Than",
1352 
        "All byte elements of vector/floating-point register vfrA are compared "
1353 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1354 
        "set if any element of vfrA is less than corresponding element of vfrB;"
1355 
        "otherwise compare flag is cleared. "
1356 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1357 
        "register vfrD.",
1358 
        "",
1359 
        "flag <- vfrA[7:0] < vfrB[7:0] ||\\"
1360 
        "\tvfrA[15:8] < vfrB[15:8] ||\\"
1361 
        "\tvfrA[23:16] < vfrB[23:16] ||\\"
1362 
        "\tvfrA[31:24] < vfrB[31:24] ||\\"
1363 
        "\tvfrA[39:32] < vfrB[39:32] ||\\"
1364 
        "\tvfrA[47:40] < vfrB[47:40] ||\\"
1365 
        "\tvfrA[55:48] < vfrB[55:48] ||\\"
1366 
        "\tvfrA[63:56] < vfrB[63:56]"
1367 
        "vfrD[63:0] <- repl(flag)",
1368 
        "None", ORVDX64I,},
1369 
 
1370 
{"lv.any_lt.h", "Vector Half-Word Elements Any Less Than",
1371 
        "All half-word elements of vector/floating-point register vfrA are compared "
1372 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1373 
        "set if any element of vfrA is less than corresponding element of vfrB;"
1374 
        "otherwise compare flag is cleared. "
1375 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1376 
        "register vfrD.",
1377 
        "",
1378 
        "flag <- vfrA[15:0] < vfrB[15:0] ||\\"
1379 
        "\tvfrA[31:16] < vfrB[31:16] ||\\"
1380 
        "\tvfrA[47:32] < vfrB[47:32] ||\\"
1381 
        "\tvfrA[63:48] < vfrB[63:48]"
1382 
        "vfrD[63:0] <- repl(flag)",
1383 
        "None", ORVDX64I,},
1384 
 
1385 
{"lv.any_le.b", "Vector Byte Elements Any Less or Equal Than",
1386 
        "All byte elements of vector/floating-point register vfrA are compared "
1387 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1388 
        "set if any element of vfrA is less or equal than corresponding element of vfrB;"
1389 
        "otherwise compare flag is cleared. "
1390 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1391 
        "register vfrD.",
1392 
        "",
1393 
        "flag <- vfrA[7:0] <= vfrB[7:0] ||\\"
1394 
        "\tvfrA[15:8] <= vfrB[15:8] ||\\"
1395 
        "\tvfrA[23:16] <= vfrB[23:16] ||\\"
1396 
        "\tvfrA[31:24] <= vfrB[31:24] ||\\"
1397 
        "\tvfrA[39:32] <= vfrB[39:32] ||\\"
1398 
        "\tvfrA[47:40] <= vfrB[47:40] ||\\"
1399 
        "\tvfrA[55:48] <= vfrB[55:48] ||\\"
1400 
        "\tvfrA[63:56] <= vfrB[63:56]"
1401 
        "vfrD[63:0] <- repl(flag)",
1402 
        "None", ORVDX64I,},
1403 
 
1404 
{"lv.any_le.h", "Vector Half-Word Elements Any Less or Equal Than",
1405 
        "All half-word elements of vector/floating-point register vfrA are compared "
1406 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1407 
        "set if any element of vfrA is less or equal than corresponding element of vfrB;"
1408 
        "otherwise compare flag is cleared. "
1409 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1410 
        "register vfrD.",
1411 
        "",
1412 
        "flag <- vfrA[15:0] ,= vfrB[15:0] ||\\"
1413 
        "\tvfrA[31:16] <= vfrB[31:16] ||\\"
1414 
        "\tvfrA[47:32] <= vfrB[47:32] ||\\"
1415 
        "\tvfrA[63:48] <= vfrB[63:48]"
1416 
        "vfrD[63:0] <- repl(flag)",
1417 
        "None", ORVDX64I,},
1418 
 
1419 
{"lv.any_ne.b", "Vector Byte Elements Any Not Equal",
1420 
        "All byte elements of vector/floating-point register vfrA are compared "
1421 
        "to byte elements of vector/floating-point register vfrB. Compare flag is "
1422 
        "set if any two corresponding elements are not equal; otherwise compare flag is cleared. "
1423 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1424 
        "register vfrD.",
1425 
        "",
1426 
        "flag <- vfrA[7:0] != vfrB[7:0] ||\\"
1427 
        "\tvfrA[15:8] != vfrB[15:8] ||\\"
1428 
        "\tvfrA[23:16] != vfrB[23:16] ||\\"
1429 
        "\tvfrA[31:24] != vfrB[31:24] ||\\"
1430 
        "\tvfrA[39:32] != vfrB[39:32] ||\\"
1431 
        "\tvfrA[47:40] != vfrB[47:40] ||\\"
1432 
        "\tvfrA[55:48] != vfrB[55:48] ||\\"
1433 
        "\tvfrA[63:56] != vfrB[63:56]"
1434 
        "vfrD[63:0] <- repl(flag)",
1435 
        "None", ORVDX64I,},
1436 
 
1437 
{"lv.any_ne.h", "Vector Half-Word Elements Any Not Equal",
1438 
        "All half-word elements of vector/floating-point register vfrA are compared "
1439 
        "to half-word elements of vector/floating-point register vfrB. Compare flag is "
1440 
        "set if any two corresponding elements are not equal; otherwise compare flag is cleared. "
1441 
        "\\Compare flag is replicated into all bit positions of vector/floating-point "
1442 
        "register vfrD.",
1443 
        "",
1444 
        "flag <- vfrA[15:0] != vfrB[15:0] ||\\"
1445 
        "\tvfrA[31:16] != vfrB[31:16] ||\\"
1446 
        "\tvfrA[47:32] != vfrB[47:32] ||\\"
1447 
        "\tvfrA[63:48] != vfrB[63:48]"
1448 
        "vfrD[63:0] <- repl(flag)",
1449 
        "None", ORVDX64I,},
1450 
 
1451 
{"lv.cmp_eq.b", "Vector Byte Elements Compare Equal",
1452 
        "All byte elements of vector/floating-point register vfrA are compared "
1453 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1454 
        "in vector/floating-point register vfrD are set if two corresponding compared "
1455 
        "elements are equal; otherwise element bits are cleared. ",
1456 
        "",
1457 
        "vfrD[7:0] <- repl(vfrA[7:0] == vfrB[7:0]\\"
1458 
        "vfrD[15:8] <- repl(vfrA[15:8] == vfrB[15:8]\\"
1459 
        "vfrD[23:16] <- repl(vfrA[23:16] == vfrB[23:16]\\"
1460 
        "vfrD[31:24] <- repl(vfrA[31:24] == vfrB[31:24]\\"
1461 
        "vfrD[39:32] <- repl(vfrA[39:32] == vfrB[39:32]\\"
1462 
        "vfrD[47:40] <- repl(vfrA[47:40] == vfrB[47:40]\\"
1463 
        "vfrD[55:48] <- repl(vfrA[55:48] == vfrB[55:48]\\"
1464 
        "vfrD[63:56] <- repl(vfrA[63:56] == vfrB[63:56]\\",
1465 
        "None", ORVDX64I,},
1466 
 
1467 
{"lv.cmp_eq.h", "Vector Half-Word Elements Compare Equal",
1468 
        "All half-word elements of vector/floating-point register vfrA are compared "
1469 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1470 
        "in vector/floating-point register vfrD are set if two corresponding compared "
1471 
        "elements are equal; otherwise element bits are cleared. ",
1472 
        "",
1473 
        "vfrD[15:0] <- repl(vfrA[7:0] == vfrB[7:0]\\"
1474 
        "vfrD[31:16] <- repl(vfrA[23:16] == vfrB[23:16]\\"
1475 
        "vfrD[47:32] <- repl(vfrA[39:32] == vfrB[39:32]\\"
1476 
        "vfrD[63:48] <- repl(vfrA[55:48] == vfrB[55:48]\\",
1477 
        "None", ORVDX64I,},
1478 
 
1479 
{"lv.cmp_ge.b", "Vector Byte Elements Compare Greater Than or Equal",
1480 
        "All byte elements of vector/floating-point register vfrA are compared "
1481 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1482 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1483 
        "greater than or equal to element in vfrB; otherwise element bits are cleared. ",
1484 
        "",
1485 
        "vfrD[7:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\"
1486 
        "vfrD[15:8] <- repl(vfrA[15:8] >= vfrB[15:8]\\"
1487 
        "vfrD[23:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\"
1488 
        "vfrD[31:24] <- repl(vfrA[31:24] >= vfrB[31:24]\\"
1489 
        "vfrD[39:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\"
1490 
        "vfrD[47:40] <- repl(vfrA[47:40] >= vfrB[47:40]\\"
1491 
        "vfrD[55:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\"
1492 
        "vfrD[63:56] <- repl(vfrA[63:56] >= vfrB[63:56]\\",
1493 
        "None", ORVDX64I,},
1494 
 
1495 
{"lv.cmp_ge.h", "Vector Half-Word Elements Compare Greater Than or Equal",
1496 
        "All half-word elements of vector/floating-point register vfrA are compared "
1497 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1498 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1499 
        "greater than or equal to element in vfrB; otherwise element bits are cleared. ",
1500 
        "",
1501 
        "vfrD[15:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\"
1502 
        "vfrD[31:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\"
1503 
        "vfrD[47:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\"
1504 
        "vfrD[63:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\",
1505 
        "None", ORVDX64I,},
1506 
 
1507 
{"lv.cmp_gt.b", "Vector Byte Elements Compare Greater Than",
1508 
        "All byte elements of vector/floating-point register vfrA are compared "
1509 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1510 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1511 
        "greater than element in vfrB; otherwise element bits are cleared. ",
1512 
        "",
1513 
        "vfrD[7:0] <- repl(vfrA[7:0] > vfrB[7:0]\\"
1514 
        "vfrD[15:8] <- repl(vfrA[15:8] > vfrB[15:8]\\"
1515 
        "vfrD[23:16] <- repl(vfrA[23:16] > vfrB[23:16]\\"
1516 
        "vfrD[31:24] <- repl(vfrA[31:24] > vfrB[31:24]\\"
1517 
        "vfrD[39:32] <- repl(vfrA[39:32] > vfrB[39:32]\\"
1518 
        "vfrD[47:40] <- repl(vfrA[47:40] > vfrB[47:40]\\"
1519 
        "vfrD[55:48] <- repl(vfrA[55:48] > vfrB[55:48]\\"
1520 
        "vfrD[63:56] <- repl(vfrA[63:56] > vfrB[63:56]\\",
1521 
        "None", ORVDX64I,},
1522 
 
1523 
{"lv.cmp_gt.h", "Vector Half-Word Elements Compare Greater Than",
1524 
        "All half-word elements of vector/floating-point register vfrA are compared "
1525 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1526 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1527 
        "greater than element in vfrB; otherwise element bits are cleared. ",
1528 
        "",
1529 
        "vfrD[15:0] <- repl(vfrA[7:0] > vfrB[7:0]\\"
1530 
        "vfrD[31:16] <- repl(vfrA[23:16] > vfrB[23:16]\\"
1531 
        "vfrD[47:32] <- repl(vfrA[39:32] > vfrB[39:32]\\"
1532 
        "vfrD[63:48] <- repl(vfrA[55:48] > vfrB[55:48]\\",
1533 
        "None", ORVDX64I,},
1534 
 
1535 
{"lv.cmp_le.b", "Vector Byte Elements Compare Less Than or Equal",
1536 
        "All byte elements of vector/floating-point register vfrA are compared "
1537 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1538 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1539 
        "less than or equal to element in vfrB; otherwise element bits are cleared. ",
1540 
        "",
1541 
        "vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
1542 
        "vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\"
1543 
        "vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
1544 
        "vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\"
1545 
        "vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
1546 
        "vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\"
1547 
        "vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\"
1548 
        "vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\",
1549 
        "None", ORVDX64I,},
1550 
 
1551 
{"lv.cmp_le.h", "Vector Half-Word Elements Compare Less Than or Equal",
1552 
        "All half-word elements of vector/floating-point register vfrA are compared "
1553 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1554 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1555 
        "less than or equal to element in vfrB; otherwise element bits are cleared. ",
1556 
        "",
1557 
        "vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
1558 
        "vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
1559 
        "vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
1560 
        "vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\",
1561 
        "None", ORVDX64I,},
1562 
 
1563 
{"lv.cmp_lt.b", "Vector Byte Elements Compare Less Than",
1564 
        "All byte elements of vector/floating-point register vfrA are compared "
1565 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1566 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1567 
        "less than element in vfrB; otherwise element bits are cleared. ",
1568 
        "",
1569 
        "vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
1570 
        "vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\"
1571 
        "vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
1572 
        "vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\"
1573 
        "vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
1574 
        "vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\"
1575 
        "vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\"
1576 
        "vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\",
1577 
        "None", ORVDX64I,},
1578 
 
1579 
{"lv.cmp_lt.h", "Vector Half-Word Elements Compare Less Than",
1580 
        "All half-word elements of vector/floating-point register vfrA are compared "
1581 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1582 
        "in vector/floating-point register vfrD are set if element in vfrA is "
1583 
        "less than element in vfrB; otherwise element bits are cleared. ",
1584 
        "",
1585 
        "vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
1586 
        "vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
1587 
        "vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
1588 
        "vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\",
1589 
        "None", ORVDX64I,},
1590 
 
1591 
{"lv.cmp_ne.b", "Vector Byte Elements Compare Not Equal",
1592 
        "All byte elements of vector/floating-point register vfrA are compared "
1593 
        "to byte elements of vector/floating-point register vfrB. Bits of the element "
1594 
        "in vector/floating-point register vfrD are set if two corresponding compared "
1595 
        "elements are not equal; otherwise element bits are cleared. ",
1596 
        "",
1597 
        "vfrD[7:0] <- repl(vfrA[7:0] != vfrB[7:0])\\"
1598 
        "vfrD[15:8] <- repl(vfrA[15:8] != vfrB[15:8])\\"
1599 
        "vfrD[23:16] <- repl(vfrA[23:16] != vfrB[23:16])\\"
1600 
        "vfrD[31:24] <- repl(vfrA[31:24] != vfrB[31:24])\\"
1601 
        "vfrD[39:32] <- repl(vfrA[39:32] != vfrB[39:32])\\"
1602 
        "vfrD[47:40] <- repl(vfrA[47:40] != vfrB[47:40])\\"
1603 
        "vfrD[55:48] <- repl(vfrA[55:48] != vfrB[55:48])\\"
1604 
        "vfrD[63:56] <- repl(vfrA[63:56] != vfrB[63:56])\\",
1605 
        "None", ORVDX64I,},
1606 
 
1607 
{"lv.cmp_ne.h", "Vector Half-Word Elements Compare Not Equal",
1608 
        "All half-word elements of vector/floating-point register vfrA are compared "
1609 
        "to half-word elements of vector/floating-point register vfrB. Bits of the element "
1610 
        "in vector/floating-point register vfrD are set if two corresponding compared "
1611 
        "elements are not equal; otherwise element bits are cleared. ",
1612 
        "",
1613 
        "vfrD[15:0] <- repl(vfrA[7:0] != vfrB[7:0])\\"
1614 
        "vfrD[31:16] <- repl(vfrA[23:16] != vfrB[23:16])\\"
1615 
        "vfrD[47:32] <- repl(vfrA[39:32] != vfrB[39:32])\\"
1616 
        "vfrD[63:48] <- repl(vfrA[55:48] != vfrB[55:48])\\",
1617 
        "None", ORVDX64I,},
1618 
 
1619 
{"lv.and", "Vector And",
1620 
        "The contents of vector/floating-point register vfrA are combined with the contents "
1621 
        "of vector/floating-point register vfrB in a bit-wise logical AND operation. The "
1622 
        "result is placed into vector/floating-point register vfrD.",
1623 
        "",
1624 
        "vfrD[63:0] <- vfrA[63:0] AND vfrB[63:0]",
1625 
        "None", ORVDX64I,},
1626 
 
1627 
{"lv.nand", "Vector Not And",
1628 
        "The contents of vector/floating-point register vfrA are combined with the contents "
1629 
        "of vector/floating-point register vfrB in a bit-wise logical NAND operation. The "
1630 
        "result is placed into vector/floating-point register vfrD.",
1631 
        "",
1632 
        "vfrD[63:0] <- vfrA[63:0] NAND vfrB[63:0]",
1633 
        "None", ORVDX64I,},
1634 
 
1635 
{"lv.nor", "Vector Not Or",
1636 
        "The contents of vector/floating-point register vfrA are combined with the contents "
1637 
        "of vector/floating-point register vfrB in a bit-wise logical NOR operation. The "
1638 
        "result is placed into vector/floating-point register vfrD.",
1639 
        "",
1640 
        "vfrD[63:0] <- vfrA[63:0] NOR vfrB[63:0]",
1641 
        "None", ORVDX64I,},
1642 
 
1643 
{"lv.or", "Vector Or",
1644 
        "The contents of vector/floating-point register vfrA are combined with the contents "
1645 
        "of vector/floating-point register vfrB in a bit-wise logical OR operation. The "
1646 
        "result is placed into vector/floating-point register vfrD.",
1647 
        "",
1648 
        "vfrD[63:0] <- vfrA[63:0] OR vfrB[63:0]",
1649 
        "None", ORVDX64I,},
1650 
 
1651 
{"lv.xor", "Vector Exclusive Or",
1652 
        "The contents of vector/floating-point register vfrA are combined with the contents "
1653 
        "of vector/floating-point register vfrB in a bit-wise logical XOR operation. The "
1654 
        "result is placed into vector/floating-point register vfrD.",
1655 
        "",
1656 
        "vfrD[63:0] <- vfrA[63:0] XOR vfrB[63:0]",
1657 
        "None", ORVDX64I,},
1658 
 
1659 
{"lv.add.b", "Vector Byte Elements Add Signed",
1660 
        "The byte elements of vector/floating-point register vfrA are added to the byte elements "
1661 
        "of vector/floating-point register vfrB to form the result elements. Result "
1662 
        "elements are placed into vector/floating-point register vfrD.",
1663 
        "",
1664 
        "vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\"
1665 
        "vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\"
1666 
        "vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\"
1667 
        "vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\"
1668 
        "vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\"
1669 
        "vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\"
1670 
        "vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\"
1671 
        "vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]",
1672 
        "None", ORVDX64I,},
1673 
 
1674 
{"lv.add.h", "Vector Half-Word Elements Add Signed",
1675 
        "The half-word elements of vector/floating-point register vfrA are added to the "
1676 
        "half-word elements of vector/floating-point register vfrB to form the result "
1677 
        "elements. Result elements are placed into vector/floating-point "
1678 
        "register vfrD.",
1679 
        "",
1680 
        "vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\"
1681 
        "vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\"
1682 
        "vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\"
1683 
        "vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\",
1684 
        "None", ORVDX64I,},
1685 
 
1686 
{"lv.sub.b", "Vector Byte Elements Subtract Signed",
1687 
        "The byte elements of vector/floating-point register vfrB are subtracted from the "
1688 
        "byte elements of vector/floating-point register vfrA to form the result elements. "
1689 
        "Result elements are placed into vector/floating-point register vfrD.",
1690 
        "",
1691 
        "vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\"
1692 
        "vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\"
1693 
        "vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\"
1694 
        "vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\"
1695 
        "vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\"
1696 
        "vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\"
1697 
        "vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\"
1698 
        "vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]",
1699 
        "None", ORVDX64I,},
1700 
 
1701 
{"lv.sub.h", "Vector Half-Word Elements Subtract Signed",
1702 
        "The half-word elements of vector/floating-point register vfrB are subtracted from the "
1703 
        "half-word elements of vector/floating-point register vfrA to form the result "
1704 
        "elements. Result elements are placed into vector/floating-point "
1705 
        "register vfrD.",
1706 
        "",
1707 
        "vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\"
1708 
        "vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\"
1709 
        "vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\"
1710 
        "vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\",
1711 
        "None", ORVDX64I,},
1712 
 
1713 
{"lv.adds.b", "Vector Byte Elements Add Signed Saturated",
1714 
        "The byte elements of vector/floating-point register vfrA are added to the byte elements "
1715 
        "of vector/floating-point register vfrB to form the result elements. If the result "
1716 
        " exceeds min/max value for the destination data type, it is saturated to min/max value "
1717 
        " and placed into vector/floating-point register vfrD.",
1718 
        "",
1719 
        "vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\"
1720 
        "vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\"
1721 
        "vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\"
1722 
        "vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\"
1723 
        "vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\"
1724 
        "vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\"
1725 
        "vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\"
1726 
        "vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])",
1727 
        "None", ORVDX64I,},
1728 
 
1729 
{"lv.adds.h", "Vector Half-Word Elements Add Signed Saturated",
1730 
        "The half-word elements of vector/floating-point register vfrA are added to the "
1731 
        "half-word elements of vector/floating-point register vfrB to form the result "
1732 
        "elements. If the result exceeds min/max value for the destination data type, "
1733 
        "it is saturated to min/max value and placed into vector/floating-point register vfrD.",
1734 
        "",
1735 
        "vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\"
1736 
        "vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\"
1737 
        "vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\"
1738 
        "vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])",
1739 
        "None", ORVDX64I,},
1740 
 
1741 
{"lv.subs.b", "Vector Byte Elements Subtract Signed Saturated",
1742 
        "The byte elements of vector/floating-point register vfrB are subtracted from the byte elements "
1743 
        "of vector/floating-point register vfrA to form the result elements. If the result "
1744 
        "exceeds min/max value for the destination data type, it is saturated to min/max value "
1745 
        "and placed into vector/floating-point register vfrD.",
1746 
        "",
1747 
        "vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\"
1748 
        "vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\"
1749 
        "vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\"
1750 
        "vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\"
1751 
        "vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\"
1752 
        "vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\"
1753 
        "vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\"
1754 
        "vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])",
1755 
        "None", ORVDX64I,},
1756 
 
1757 
{"lv.subs.h", "Vector Half-Word Elements Subtract Signed Saturated",
1758 
        "The half-word elements of vector/floating-point register vfrB are subtracted from the "
1759 
        "half-word elements of vector/floating-point register vfrA to form the result "
1760 
        "elements. If the result exceeds min/max value for the destination data type, "
1761 
        "it is saturated to min/max value and placed into vector/floating-point register vfrD.",
1762 
        "",
1763 
        "vfrD[15:0] <- sat16s(vfrA[15:0] - vfrB[15:0])\\"
1764 
        "vfrD[31:16] <- sat16s(vfrA[31:16] - vfrB[31:16])\\"
1765 
        "vfrD[47:32] <- sat16s(vfrA[47:32] - vfrB[47:32])\\"
1766 
        "vfrD[63:48] <- sat16s(vfrA[63:48] - vfrB[63:48])",
1767 
        "None", ORVDX64I,},
1768 
 
1769 
{"lv.addu.b", "Vector Byte Elements Add Unsigned",
1770 
        "The unsigned byte elements of vector/floating-point register vfrA are added to "
1771 
        "the unsigned byte elements of vector/floating-point register vfrB to form the "
1772 
        "result elements. Result elements are placed into vector/floating-point register vfrD.",
1773 
        "",
1774 
        "vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\"
1775 
        "vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\"
1776 
        "vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\"
1777 
        "vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\"
1778 
        "vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\"
1779 
        "vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\"
1780 
        "vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\"
1781 
        "vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]",
1782 
        "None", ORVDX64I,},
1783 
 
1784 
{"lv.addu.h", "Vector Half-Word Elements Add Unsigned",
1785 
        "The unsigned half-word elements of vector/floating-point register vfrA are added to the "
1786 
        "unsigned half-word elements of vector/floating-point register vfrB to form the result "
1787 
        "elements. Result elements are placed into vector/floating-point "
1788 
        "register vfrD.",
1789 
        "",
1790 
        "vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\"
1791 
        "vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\"
1792 
        "vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\"
1793 
        "vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\",
1794 
        "None", ORVDX64I,},
1795 
 
1796 
{"lv.subu.b", "Vector Byte Elements Subtract Unsigned",
1797 
        "The unsigned byte elements of vector/floating-point register vfrB are subtracted from the "
1798 
        "unsigned byte elements of vector/floating-point register vfrA to form the result elements. "
1799 
        "Result elements are placed into vector/floating-point register vfrD.",
1800 
        "",
1801 
        "vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\"
1802 
        "vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\"
1803 
        "vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\"
1804 
        "vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\"
1805 
        "vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\"
1806 
        "vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\"
1807 
        "vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\"
1808 
        "vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]",
1809 
        "None", ORVDX64I,},
1810 
 
1811 
{"lv.subu.h", "Vector Half-Word Elements Subtract Unsigned",
1812 
        "The unsigned half-word elements of vector/floating-point register vfrB are subtracted from the "
1813 
        "unsigned half-word elements of vector/floating-point register vfrA to form the result "
1814 
        "elements. Result elements are placed into vector/floating-point "
1815 
        "register vfrD.",
1816 
        "",
1817 
        "vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\"
1818 
        "vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\"
1819 
        "vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\"
1820 
        "vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\",
1821 
        "None", ORVDX64I,},
1822 
 
1823 
{"lv.addus.b", "Vector Byte Elements Add Unsigned Saturated",
1824 
        "The unsigned byte elements of vector/floating-point register vfrA are added to the "
1825 
        "unsigned byte elements of vector/floating-point register vfrB to form the result "
1826 
        "elements. If the result exceeds min/max value for the destination data type, "
1827 
        "it is saturated to min/max value and placed into vector/floating-point register vfrD.",
1828 
        "",
1829 
        "vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\"
1830 
        "vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\"
1831 
        "vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\"
1832 
        "vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\"
1833 
        "vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\"
1834 
        "vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\"
1835 
        "vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\"
1836 
        "vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])",
1837 
        "None", ORVDX64I,},
1838 
 
1839 
{"lv.addus.h", "Vector Half-Word Elements Add Unsigned Saturated",
1840 
        "The unsigned half-word elements of vector/floating-point register vfrA are added to the "
1841 
        "unsigned half-word elements of vector/floating-point register vfrB to form the result "
1842 
        "elements. If the result exceeds min/max value for the destination data type, "
1843 
        "it is saturated to min/max value and placed into vector/floating-point register vfrD.",
1844 
        "",
1845 
        "vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\"
1846 
        "vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\"
1847 
        "vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\"
1848 
        "vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])",
1849 
        "None", ORVDX64I,},
1850 
 
1851 
{"lv.subus.b", "Vector Byte Elements Subtract Unsigned Saturated",
1852 
        "The unsigned byte elements of vector/floating-point register vfrB are subtracted from "
1853 
        "the unsigned byte elements of vector/floating-point register vfrA to form the result "
1854 
        "elements. If the result exceeds min/max value for the destination data type, it is "
1855 
        "saturated to min/max value and placed into vector/floating-point register vfrD.",
1856 
        "",
1857 
        "vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\"
1858 
        "vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\"
1859 
        "vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\"
1860 
        "vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\"
1861 
        "vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\"
1862 
        "vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\"
1863 
        "vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\"
1864 
        "vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])",
1865 
        "None", ORVDX64I,},
1866 
 
1867 
{"lv.subus.h", "Vector Half-Word Elements Subtract Unsigned Saturated",
1868 
        "The unsigned half-word elements of vector/floating-point register vfrB are subtracted "
1869 
        "from the unsigned half-word elements of vector/floating-point register vfrA to form "
1870 
        "the result elements. If the result exceeds min/max value for the destination data type, "
1871 
        "it is saturated to min/max value and placed into vector/floating-point register vfrD.",
1872 
        "",
1873 
        "vfrD[15:0] <- sat16u(vfrA[15:0] - vfrB[15:0])\\"
1874 
        "vfrD[31:16] <- sat16u(vfrA[31:16] - vfrB[31:16])\\"
1875 
        "vfrD[47:32] <- sat16u(vfrA[47:32] - vfrB[47:32])\\"
1876 
        "vfrD[63:48] <- sat16u(vfrA[63:48] - vfrB[63:48])",
1877 
        "None", ORVDX64I,},
1878 
 
1879 
{"lv.avg.b", "Vector Byte Elements Average",
1880 
        "The byte elements of vector/floating-point register vfrA are added to the byte elements "
1881 
        "of vector/floating-point register vfrB and the sum is shifted right by one to form the "
1882 
        "result elements. Result elements are placed into vector/floating-point register vfrD.",
1883 
        "",
1884 
        "vfrD[7:0] <- (vfrA[7:0] + vfrB[7:0]) >> 1\\"
1885 
        "vfrD[15:8] <- (vfrA[15:8] + vfrB[15:8]) >> 1\\"
1886 
        "vfrD[23:16] <- (vfrA[23:16] + vfrB[23:16]) >> 1\\"
1887 
        "vfrD[31:24] <- (vfrA[31:24] + vfrB[31:24]) >> 1\\"
1888 
        "vfrD[39:32] <- (vfrA[39:32] + vfrB[39:32]) >> 1\\"
1889 
        "vfrD[47:40] <- (vfrA[47:40] + vfrB[47:40]) >> 1\\"
1890 
        "vfrD[55:48] <- (vfrA[55:48] + vfrB[55:48]) >> 1\\"
1891 
        "vfrD[63:56] <- (vfrA[63:56] + vfrB[63:56]) >> 1",
1892 
        "None", ORVDX64I,},
1893 
 
1894 
{"lv.avg.h", "Vector Half-Word Elements Average",
1895 
        "The half-word elements of vector/floating-point register vfrA are added to the "
1896 
        "half-word elements of vector/floating-point register vfrB and the sum is shifted "
1897 
        "right by one to form the result elements. Result elements are placed into "
1898 
        "vector/floating-point register vfrD.",
1899 
        "",
1900 
        "vfrD[15:0] <- (vfrA[15:0] + vfrB[15:0]) >> 1\\"
1901 
        "vfrD[31:16] <- (vfrA[31:16] + vfrB[31:16]) >> 1\\"
1902 
        "vfrD[47:32] <- (vfrA[47:32] + vfrB[47:32]) >> 1\\"
1903 
        "vfrD[63:48] <- (vfrA[63:48] + vfrB[63:48]) >> 1\\",
1904 
        "None", ORVDX64I,},
1905 
 
1906 
{"lv.max.b", "Vector Byte Elements Maximum",
1907 
        "The byte elements of vector/floating-point register vfrA are compared to the byte elements "
1908 
        "of vector/floating-point register vfrB and larger elements are selected to form the "
1909 
        "result elements. Result elements are placed into vector/floating-point register vfrD.",
1910 
        "",
1911 
        "vfrD[7:0] <- vfrA[7:0] > vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\"
1912 
        "vfrD[15:8] <- vfrA[15:8] > vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\"
1913 
        "vfrD[23:16] <- vfrA[23:16] > vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\"
1914 
        "vfrD[31:24] <- vfrA[31:24] > vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\"
1915 
        "vfrD[39:32] <- vfrA[39:32] > vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\"
1916 
        "vfrD[47:40] <- vfrA[47:40] > vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\"
1917 
        "vfrD[55:48] <- vfrA[55:48] > vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\"
1918 
        "vfrD[63:56] <- vfrA[63:56] > vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]",
1919 
        "None", ORVDX64I,},
1920 
 
1921 
{"lv.max.h", "Vector Half-Word Elements Maximum",
1922 
        "The half-word elements of vector/floating-point register vfrA are compared to the "
1923 
        "half-word elements of vector/floating-point register vfrB and larger elements "
1924 
        "are selected to form the result elements. Result elements are placed into "
1925 
        "vector/floating-point register vfrD.",
1926 
        "",
1927 
        "vfrD[15:0] <- vfrA[15:0] > vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\"
1928 
        "vfrD[31:16] <- vfrA[31:16] > vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\"
1929 
        "vfrD[47:32] <- vfrA[47:32] > vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\"
1930 
        "vfrD[63:48] <- vfrA[63:48] > vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\",
1931 
        "None", ORVDX64I,},
1932 
 
1933 
{"lv.min.b", "Vector Byte Elements Minimum",
1934 
        "The byte elements of vector/floating-point register vfrA are compared to the byte elements "
1935 
        "of vector/floating-point register vfrB and smaller elements are selected to form the "
1936 
        "result elements. Result elements are placed into vector/floating-point register vfrD.",
1937 
        "",
1938 
        "vfrD[7:0] <- vfrA[7:0] < vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\"
1939 
        "vfrD[15:8] <- vfrA[15:8] < vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\"
1940 
        "vfrD[23:16] <- vfrA[23:16] < vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\"
1941 
        "vfrD[31:24] <- vfrA[31:24] < vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\"
1942 
        "vfrD[39:32] <- vfrA[39:32] < vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\"
1943 
        "vfrD[47:40] <- vfrA[47:40] < vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\"
1944 
        "vfrD[55:48] <- vfrA[55:48] < vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\"
1945 
        "vfrD[63:56] <- vfrA[63:56] < vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]",
1946 
        "None", ORVDX64I,},
1947 
 
1948 
{"lv.min.h", "Vector Half-Word Elements Minimum",
1949 
        "The half-word elements of vector/floating-point register vfrA are compared to the "
1950 
        "half-word elements of vector/floating-point register vfrB and smaller elements "
1951 
        "are selected to form the result elements. Result elements are placed into "
1952 
        "vector/floating-point register vfrD.",
1953 
        "",
1954 
        "vfrD[15:0] <- vfrA[15:0] < vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\"
1955 
        "vfrD[31:16] <- vfrA[31:16] < vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\"
1956 
        "vfrD[47:32] <- vfrA[47:32] < vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\"
1957 
        "vfrD[63:48] <- vfrA[63:48] < vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\",
1958 
        "None", ORVDX64I,},
1959 
 
1960 
{"lv.sll.b", "Vector Byte Elements Shift Left Logical",
1961 
        "The contents of byte elements of vector/floating-point register vfrA are "
1962 
        "shifted left by the number of bits specified in lower 3 bits in each byte element "
1963 
        "of vector/floating-point register vfrB, inserting zeros into the low-order bits "
1964 
        "elements. Result elements are placed into vector/floating-point register vfrD.",
1965 
        "",
1966 
        "vfrD[7:0] <- vfrA[7:0] << vfrB[2:0]\\"
1967 
        "vfrD[15:8] <- vfrA[15:8] << vfrB[10:8]\\"
1968 
        "vfrD[23:16] <- vfrA[23:16] << vfrB[18:16]\\"
1969 
        "vfrD[31:24] <- vfrA[31:24] << vfrB[26:24]\\"
1970 
        "vfrD[39:32] <- vfrA[39:32] << vfrB[34:32]\\"
1971 
        "vfrD[47:40] <- vfrA[47:40] << vfrB[42:40]\\"
1972 
        "vfrD[55:48] <- vfrA[55:48] << vfrB[50:48]\\"
1973 
        "vfrD[63:56] <- vfrA[63:56] << vfrB[58:56]",
1974 
        "None", ORVDX64I,},
1975 
 
1976 
{"lv.sll.h", "Vector Half-Word Elements Shift Left Logical",
1977 
        "The contents of half-word elements of vector/floating-point register vfrA are "
1978 
        "shifted left by the number of bits specified in lower 4 bits in each half-word element "
1979 
        "of vector/floating-point register vfrB, inserting zeros into the low-order bits "
1980 
        "elements. Result elements are placed into vector/floating-point register vfrD.",
1981 
        "",
1982 
        "vfrD[15:0] <- vfrA[15:0] << vfrB[3:0]\\"
1983 
        "vfrD[31:16] <- vfrA[31:16] << vfrB[19:16]\\"
1984 
        "vfrD[47:32] <- vfrA[47:32] << vfrB[35:32]\\"
1985 
        "vfrD[63:48] <- vfrA[63:48] << vfrB[51:48]\\",
1986 
        "None", ORVDX64I,},
1987 
 
1988 
{"lv.srl.b", "Vector Byte Elements Shift Right Logical",
1989 
        "The contents of byte elements of vector/floating-point register vfrA are "
1990 
        "shifted right by the number of bits specified in lower 3 bits in each byte element "
1991 
        "of vector/floating-point register vfrB, inserting zeros into the high-order bits "
1992 
        "elements. Result elements are placed into vector/floating-point register vfrD.",
1993 
        "",
1994 
        "vfrD[7:0] <- vfrA[7:0] >> vfrB[2:0]\\"
1995 
        "vfrD[15:8] <- vfrA[15:8] >> vfrB[10:8]\\"
1996 
        "vfrD[23:16] <- vfrA[23:16] >> vfrB[18:16]\\"
1997 
        "vfrD[31:24] <- vfrA[31:24] >> vfrB[26:24]\\"
1998 
        "vfrD[39:32] <- vfrA[39:32] >> vfrB[34:32]\\"
1999 
        "vfrD[47:40] <- vfrA[47:40] >> vfrB[42:40]\\"
2000 
        "vfrD[55:48] <- vfrA[55:48] >> vfrB[50:48]\\"
2001 
        "vfrD[63:56] <- vfrA[63:56] >> vfrB[58:56]",
2002 
        "None", ORVDX64I,},
2003 
 
2004 
{"lv.srl.h", "Vector Half-Word Elements Shift Right Logical",
2005 
        "The contents of half-word elements of vector/floating-point register vfrA are "
2006 
        "shifted right by the number of bits specified in lower 4 bits in each half-word element "
2007 
        "of vector/floating-point register vfrB, inserting zeros into the low-order bits of "
2008 
        "elements. Result elements are placed into vector/floating-point register vfrD.",
2009 
        "",
2010 
        "vfrD[15:0] <- vfrA[15:0] >> vfrB[3:0]\\"
2011 
        "vfrD[31:16] <- vfrA[31:16] >> vfrB[19:16]\\"
2012 
        "vfrD[47:32] <- vfrA[47:32] >> vfrB[35:32]\\"
2013 
        "vfrD[63:48] <- vfrA[63:48] >> vfrB[51:48]\\",
2014 
        "None", ORVDX64I,},
2015 
 
2016 
{"lv.sra.b", "Vector Byte Elements Shift Right Arithmetic",
2017 
        "The contents of byte elements of vector/floating-point register vfrA are "
2018 
        "shifted right by the number of bits specified in lower 3 bits in each byte element "
2019 
        "of vector/floating-point register vfrB, inserting most significat bit of each "
2020 
        "element into the high-order bits. "
2021 
        "Result elements are placed into vector/floating-point register vfrD.",
2022 
        "",
2023 
        "vfrD[7:0] <- vfrA[7:0] sra vfrB[2:0]\\"
2024 
        "vfrD[15:8] <- vfrA[15:8] sra vfrB[10:8]\\"
2025 
        "vfrD[23:16] <- vfrA[23:16] sra vfrB[18:16]\\"
2026 
        "vfrD[31:24] <- vfrA[31:24] sra vfrB[26:24]\\"
2027 
        "vfrD[39:32] <- vfrA[39:32] sra vfrB[34:32]\\"
2028 
        "vfrD[47:40] <- vfrA[47:40] sra vfrB[42:40]\\"
2029 
        "vfrD[55:48] <- vfrA[55:48] sra vfrB[50:48]\\"
2030 
        "vfrD[63:56] <- vfrA[63:56] sra vfrB[58:56]",
2031 
        "None", ORVDX64I,},
2032 
 
2033 
{"lv.sra.h", "Vector Half-Word Elements Shift Right Arithmetic",
2034 
        "The contents of half-word elements of vector/floating-point register vfrA are "
2035 
        "shifted right by the number of bits specified in lower 4 bits in each half-word element "
2036 
        "of vector/floating-point register vfrB, inserting most significant bit of each element "
2037 
        "into the low-order bits. "
2038 
        "Result elements are placed into vector/floating-point register vfrD.",
2039 
        "",
2040 
        "vfrD[15:0] <- vfrA[15:0] sra vfrB[3:0]\\"
2041 
        "vfrD[31:16] <- vfrA[31:16] sra vfrB[19:16]\\"
2042 
        "vfrD[47:32] <- vfrA[47:32] sra vfrB[35:32]\\"
2043 
        "vfrD[63:48] <- vfrA[63:48] sra vfrB[51:48]\\",
2044 
        "None", ORVDX64I,},
2045 
 
2046 
{"lv.rl.b", "Vector Byte Elements Rotate Left",
2047 
        "The contents of byte elements of vector/floating-point register vfrA are "
2048 
        "rotated left by the number of bits specified in lower 3 bits in each byte element "
2049 
        "of vector/floating-point register vfrB. "
2050 
        "Result elements are placed into vector/floating-point register vfrD.",
2051 
        "",
2052 
        "vfrD[7:0] <- vfrA[7:0] rl vfrB[2:0]\\"
2053 
        "vfrD[15:8] <- vfrA[15:8] rl vfrB[10:8]\\"
2054 
        "vfrD[23:16] <- vfrA[23:16] rl vfrB[18:16]\\"
2055 
        "vfrD[31:24] <- vfrA[31:24] rl vfrB[26:24]\\"
2056 
        "vfrD[39:32] <- vfrA[39:32] rl vfrB[34:32]\\"
2057 
        "vfrD[47:40] <- vfrA[47:40] rl vfrB[42:40]\\"
2058 
        "vfrD[55:48] <- vfrA[55:48] rl vfrB[50:48]\\"
2059 
        "vfrD[63:56] <- vfrA[63:56] rl vfrB[58:56]",
2060 
        "None", ORVDX64I,},
2061 
 
2062 
{"lv.rl.h", "Vector Half-Word Elements Rotate Left",
2063 
        "The contents of half-word elements of vector/floating-point register vfrA are "
2064 
        "rotated left by the number of bits specified in lower 4 bits in each half-word element "
2065 
        "of vector/floating-point register vfrB. "
2066 
        "Result elements are placed into vector/floating-point register vfrD.",
2067 
        "",
2068 
        "vfrD[15:0] <- vfrA[15:0] rl vfrB[3:0]\\"
2069 
        "vfrD[31:16] <- vfrA[31:16] rl vfrB[19:16]\\"
2070 
        "vfrD[47:32] <- vfrA[47:32] rl vfrB[35:32]\\"
2071 
        "vfrD[63:48] <- vfrA[63:48] rl vfrB[51:48]\\",
2072 
        "None", ORVDX64I,},
2073 
 
2074 
{"lv.sll", "Vector Shift Left Logical",
2075 
        "The contents of vector/floating-point register vfrA are "
2076 
        "shifted left by the number of bits specified in lower 4 bits in each byte element "
2077 
        "of vector/floating-point register vfrB, inserting zeros into the low-order bits of "
2078 
        "vfrD. "
2079 
        "Result elements are placed into vector/floating-point register vfrD.",
2080 
        "",
2081 
        "vfrD[63:0] <- vfrA[63:0] << vfrB[2:0]",
2082 
        "None", ORVDX64I,},
2083 
 
2084 
{"lv.srl", "Vector Shift Right Logical",
2085 
        "The contents of vector/floating-point register vfrA are "
2086 
        "shifted right by the number of bits specified in lower 4 bits in each byte element "
2087 
        "of vector/floating-point register vfrB, inserting zeros into the high-order bits of "
2088 
        "vfrD. "
2089 
        "Result elements are placed into vector/floating-point register vfrD.",
2090 
        "",
2091 
        "vfrD[63:0] <- vfrA[63:0] >> vfrB[2:0]",
2092 
        "None", ORVDX64I,},
2093 
 
2094 
{"lv.merge.b", "Vector Byte Elements Merge",
2095 
        "Byte elements of the lower half of the vector/floating-point register vfrA are "
2096 
        "combined with the byte elements of the lower half of vector/floating-point "
2097 
        "register vfrB in such a way that lowest element is from the vfrB, second element "
2098 
        "from the vfrA, third again from the vfrB etc. "
2099 
        "Result elements are placed into vector/floating-point register vfrD.",
2100 
        "",
2101 
        "vfrD[7:0] <- vfrB[7:0]\\"
2102 
        "vfrD[15:8] <- vfrA[15:8]\\"
2103 
        "vfrD[23:16] <- vfrB[23:16]\\"
2104 
        "vfrD[31:24] <- vfrA[31:24]\\"
2105 
        "vfrD[39:32] <- vfrB[39:32]\\"
2106 
        "vfrD[47:40] <- vfrA[47:40]\\"
2107 
        "vfrD[55:48] <- vfrB[55:48]\\"
2108 
        "vfrD[63:56] <- vfrA[63:56]",
2109 
        "None", ORVDX64I,},
2110 
 
2111 
{"lv.merge.h", "Vector Half-Word Elements Merge",
2112 
        "Half-word elements of the lower half of the vector/floating-point register vfrA are "
2113 
        "combined with the byte elements of the lower half of vector/floating-point "
2114 
        "register vfrB in such a way that lowest element is from the vfrB, second element "
2115 
        "from the vfrA, third again from the vfrB etc. "
2116 
        "Result elements are placed into vector/floating-point register vfrD.",
2117 
        "",
2118 
        "vfrD[15:0] <- vfrB[15:0]\\"
2119 
        "vfrD[31:16] <- vfrA[31:16]\\"
2120 
        "vfrD[47:32] <- vfrB[47:32]\\"
2121 
        "vfrD[63:48] <- vfrA[63:48]",
2122 
        "None", ORVDX64I,},
2123 
 
2124 
{"lv.pack.b", "Vector Byte Elements Pack",
2125 
        "Lower half of the byte elements of the vector/floating-point register vfrA are "
2126 
        "truncated and combined with the lower half of the byte truncated elements of the "
2127 
        "vector/floating-point register vfrB in such a way that lowest elements are from "
2128 
        "vfrB and highest element from vfrA. "
2129 
        "Result elements are placed into vector/floating-point register vfrD.",
2130 
        "",
2131 
        "vfrD[3:0] <- vfrB[3:0]\\"
2132 
        "vfrD[7:4] <- vfrB[11:8]\\"
2133 
        "vfrD[11:8] <- vfrB[19:16]\\"
2134 
        "vfrD[15:12] <- vfrB[27:24]\\"
2135 
        "vfrD[19:16] <- vfrB[35:32]\\"
2136 
        "vfrD[23:20] <- vfrB[43:40]\\"
2137 
        "vfrD[27:24] <- vfrB[51:48]\\"
2138 
        "vfrD[31:28] <- vfrB[59:56]\\"
2139 
        "vfrD[35:32] <- vfrA[3:0]\\"
2140 
        "vfrD[39:36] <- vfrA[11:8]\\"
2141 
        "vfrD[43:40] <- vfrA[19:16]\\"
2142 
        "vfrD[47:44] <- vfrA[27:24]\\"
2143 
        "vfrD[51:48] <- vfrA[35:32]\\"
2144 
        "vfrD[55:52] <- vfrA[43:40]\\"
2145 
        "vfrD[59:56] <- vfrA[51:48]\\"
2146 
        "vfrD[63:60] <- vfrA[59:56]",
2147 
        "None", ORVDX64I,},
2148 
 
2149 
{"lv.pack.h", "Vector Half-word Elements Pack",
2150 
        "Lower half of the half-word elements of the vector/floating-point register vfrA are "
2151 
        "truncated and combined with the lower half of the half-word truncated elements of the "
2152 
        "vector/floating-point register vfrB in such a way that lowest elements are from vfrB and highest element "
2153 
        "from vfrA. "
2154 
        "Result elements are placed into vector/floating-point register vfrD.",
2155 
        "",
2156 
        "vfrD[7:0] <- vfrB[15:0]\\"
2157 
        "vfrD[15:8] <- vfrB[31:16]\\"
2158 
        "vfrD[23:16] <- vfrB[47:32]\\"
2159 
        "vfrD[31:24] <- vfrB[63:48]\\"
2160 
        "vfrD[39:32] <- vfrA[15:0]\\"
2161 
        "vfrD[47:40] <- vfrA[31:16]\\"
2162 
        "vfrD[55:48] <- vfrA[47:32]\\"
2163 
        "vfrD[63:56] <- vfrA[63:48]\\",
2164 
        "None", ORVDX64I,},
2165 
 
2166 
{"lv.packs.b", "Vector Byte Elements Pack Signed Saturated",
2167 
        "Lower half of the signed byte elements of the vector/floating-point register vfrA are "
2168 
        "truncated and combined with the lower half of the signed byte truncated elements of "
2169 
        "the vector/floating-point register vfrB in such a way that lowest elements are from "
2170 
        "vfrB and highest element from vfrA. "
2171 
        "If any truncated element exceeds signed 4-bit value, it is saturated. "
2172 
        "Result elements are placed into vector/floating-point register vfrD.",
2173 
        "",
2174 
        "vfrD[3:0] <- sat4s(vfrB[7:0]\\"
2175 
        "vfrD[7:4] <- sat4s(vfrB[15:8]\\"
2176 
        "vfrD[11:8] <- sat4s(vfrB[23:16]\\"
2177 
        "vfrD[15:12] <- sat4s(vfrB[31:24]\\"
2178 
        "vfrD[19:16] <- sat4s(vfrB[39:32]\\"
2179 
        "vfrD[23:20] <- sat4s(vfrB[47:40]\\"
2180 
        "vfrD[27:24] <- sat4s(vfrB[55:48]\\"
2181 
        "vfrD[31:28] <- sat4s(vfrB[63:56]\\"
2182 
        "vfrD[35:32] <- sat4s(vfrA[7:0]\\"
2183 
        "vfrD[39:36] <- sat4s(vfrA[15:8]\\"
2184 
        "vfrD[43:40] <- sat4s(vfrA[23:16]\\"
2185 
        "vfrD[47:44] <- sat4s(vfrA[31:24]\\"
2186 
        "vfrD[51:48] <- sat4s(vfrA[39:32]\\"
2187 
        "vfrD[55:52] <- sat4s(vfrA[47:40]\\"
2188 
        "vfrD[59:56] <- sat4s(vfrA[55:48]\\"
2189 
        "vfrD[63:60] <- sat4s(vfrA[63:56]",
2190 
        "None", ORVDX64I,},
2191 
 
2192 
{"lv.packs.h", "Vector Half-word Elements Pack Signed Saturated",
2193 
        "Lower half of the signed halfpword elements of the vector/floating-point register "
2194 
        "vfrA are truncated and combined with the lower half of the signed half-word "
2195 
        "truncated elements of the vector/floating-point register vfrB in such a way "
2196 
        "that lowest elements are from vfrB and highest element from vfrA. "
2197 
        "If any truncated element exceeds signed 8-bit value, it is saturated. "
2198 
        "Result elements are placed into vector/floating-point register vfrD.",
2199 
        "",
2200 
        "vfrD[7:0] <- sat8s(vfrB[15:0])\\"
2201 
        "vfrD[15:8] <- sat8s(vfrB[31:16])\\"
2202 
        "vfrD[23:16] <- sat8s(vfrB[47:32])\\"
2203 
        "vfrD[31:24] <- sat8s(vfrB[63:48])\\"
2204 
        "vfrD[39:32] <- sat8s(vfrA[15:0])\\"
2205 
        "vfrD[47:40] <- sat8s(vfrA[31:16])\\"
2206 
        "vfrD[55:48] <- sat8s(vfrA[47:32])\\"
2207 
        "vfrD[63:56] <- sat8s(vfrA[63:48])\\",
2208 
        "None", ORVDX64I,},
2209 
 
2210 
{"lv.packus.b", "Vector Byte Elements Pack Unsigned Saturated",
2211 
        "Lower half of the unsigned byte elements of the vector/floating-point register vfrA are "
2212 
        "truncated and combined with the lower half of the unsigned byte truncated elements of "
2213 
        "the vector/floating-point register vfrB in such a way that lowest elements are from "
2214 
        "vfrB and highest element from vfrA. "
2215 
        "If any truncated element exceeds unsigned 4-bit value, it is saturated. "
2216 
        "Result elements are placed into vector/floating-point register vfrD.",
2217 
        "",
2218 
        "vfrD[3:0] <- sat4u(vfrB[7:0]\\"
2219 
        "vfrD[7:4] <- sat4u(vfrB[15:8]\\"
2220 
        "vfrD[11:8] <- sat4u(vfrB[23:16]\\"
2221 
        "vfrD[15:12] <- sat4u(vfrB[31:24]\\"
2222 
        "vfrD[19:16] <- sat4u(vfrB[39:32]\\"
2223 
        "vfrD[23:20] <- sat4u(vfrB[47:40]\\"
2224 
        "vfrD[27:24] <- sat4u(vfrB[55:48]\\"
2225 
        "vfrD[31:28] <- sat4u(vfrB[63:56]\\"
2226 
        "vfrD[35:32] <- sat4u(vfrA[7:0]\\"
2227 
        "vfrD[39:36] <- sat4u(vfrA[15:8]\\"
2228 
        "vfrD[43:40] <- sat4u(vfrA[23:16]\\"
2229 
        "vfrD[47:44] <- sat4u(vfrA[31:24]\\"
2230 
        "vfrD[51:48] <- sat4u(vfrA[39:32]\\"
2231 
        "vfrD[55:52] <- sat4u(vfrA[47:40]\\"
2232 
        "vfrD[59:56] <- sat4u(vfrA[55:48]\\"
2233 
        "vfrD[63:60] <- sat4u(vfrA[63:56]",
2234 
        "None", ORVDX64I,},
2235 
 
2236 
{"lv.packus.h", "Vector Half-word Elements Pack Unsigned Saturated",
2237 
        "Lower half of the unsigned halfpword elements of the vector/floating-point register "
2238 
        "vfrA are truncated and combined with the lower half of the unsigned half-word "
2239 
        "truncated elements of the vector/floating-point register vfrB in such a way "
2240 
        "that lowest elements are from vfrB and highest element from vfrA. "
2241 
        "If any truncated element exceeds unsigned 8-bit value, it is saturated. "
2242 
        "Result elements are placed into vector/floating-point register vfrD.",
2243 
        "",
2244 
        "vfrD[7:0] <- sat8u(vfrB[15:0])\\"
2245 
        "vfrD[15:8] <- sat8u(vfrB[31:16])\\"
2246 
        "vfrD[23:16] <- sat8u(vfrB[47:32])\\"
2247 
        "vfrD[31:24] <- sat8u(vfrB[63:48])\\"
2248 
        "vfrD[39:32] <- sat8u(vfrA[15:0])\\"
2249 
        "vfrD[47:40] <- sat8u(vfrA[31:16])\\"
2250 
        "vfrD[55:48] <- sat8u(vfrA[47:32])\\"
2251 
        "vfrD[63:56] <- sat8u(vfrA[63:48])\\",
2252 
        "None", ORVDX64I,},
2253 
 
2254 
{"lv.unpack.b", "Vector Byte Elements Unpack",
2255 
        "Lower half of 4-bit elements in vector/floating-point register "
2256 
        "vfrA are sign-extended and placed into vector/floating-point register vfrD.",
2257 
        "",
2258 
        "vfrD[7:0] <- exts(vfrA[3:0])\\"
2259 
        "vfrD[15:8] <- exts(vfrA[7:4])\\"
2260 
        "vfrD[23:16] <- exts(vfrA[11:8])\\"
2261 
        "vfrD[31:24] <- exts(vfrA[15:12])\\"
2262 
        "vfrD[39:32] <- exts(vfrA[19:16])\\"
2263 
        "vfrD[47:40] <- exts(vfrA[23:20])\\"
2264 
        "vfrD[55:48] <- exts(vfrA[27:24])\\"
2265 
        "vfrD[63:56] <- exts(vfrA[31:28])",
2266 
        "None", ORVDX64I,},
2267 
 
2268 
{"lv.unpack.h", "Vector Half-Word Elements Unpack",
2269 
        "Lower half of 8-bit elements in vector/floating-point register "
2270 
        "vfrA are sign-extended and placed into vector/floating-point register vfrD.",
2271 
        "",
2272 
        "vfrD[15:0] <- exts(vfrA[7:0])\\"
2273 
        "vfrD[31:16] <- exts(vfrA[15:8])\\"
2274 
        "vfrD[47:32] <- exts(vfrA[23:16])\\"
2275 
        "vfrD[63:48] <- exts(vfrA[31:24])\\",
2276 
        "None", ORVDX64I,},
2277 
 
2278 
{"lv.perm.n", "Vector Nibble Elements Permute",
2279 
        "The 4-bit elements of vector/floating-point register vfrA are "
2280 
        "permuted according to corresponding 4-bit values in vector/floating-point "
2281 
        "register vfrB. "
2282 
        "Result elements are placed into vector/floating-point register vfrD.",
2283 
        "",
2284 
        "vfrD[3:0] <- vfrA[vfrB[3:0]*4+3:vfrB[3:0]*4]\\"
2285 
        "vfrD[7:4] <- vfrA[vfrB[7:4]*4+3:vfrB[7:4]*4]\\"
2286 
        "vfrD[11:8] <- vfrA[vfrB[11:8]*4+3:vfrB[11:8]*4]\\"
2287 
        "vfrD[15:12] <- vfrA[vfrB[15:12]*4+3:vfrB[15:12]*4]\\"
2288 
        "vfrD[19:16] <- vfrA[vfrB[19:16]*4+3:vfrB[19:16]*4]\\"
2289 
        "vfrD[23:20] <- vfrA[vfrB[23:20]*4+3:vfrB[23:20]*4]\\"
2290 
        "vfrD[27:24] <- vfrA[vfrB[27:24]*4+3:vfrB[27:24]*4]\\"
2291 
        "vfrD[31:28] <- vfrA[vfrB[31:28]*4+3:vfrB[31:28]*4]\\"
2292 
        "vfrD[35:32] <- vfrA[vfrB[35:32]*4+3:vfrB[35:32]*4]\\"
2293 
        "vfrD[39:36] <- vfrA[vfrB[39:36]*4+3:vfrB[39:36]*4]\\"
2294 
        "vfrD[43:40] <- vfrA[vfrB[43:40]*4+3:vfrB[43:40]*4]\\"
2295 
        "vfrD[47:44] <- vfrA[vfrB[47:44]*4+3:vfrB[47:44]*4]\\"
2296 
        "vfrD[51:48] <- vfrA[vfrB[51:48]*4+3:vfrB[51:48]*4]\\"
2297 
        "vfrD[55:52] <- vfrA[vfrB[55:52]*4+3:vfrB[55:52]*4]\\"
2298 
        "vfrD[59:56] <- vfrA[vfrB[59:56]*4+3:vfrB[59:56]*4]\\"
2299 
        "vfrD[63:60] <- vfrA[vfrB[63:60]*4+3:vfrB[63:60]*4]",
2300 
        "None", ORVDX64I,},
2301 
 
2302 
{"lv.madds.h", "Vector Half-Word Elements Multiply Add Signed Saturated",
2303 
        "The signed half-word elements of vector/floating-point register vfrA are multiplied "
2304 
        "by the signed half-word elements of vector/floating-point register vfrB to form "
2305 
        "intermediate results. They are added to the signed half-word VMAC elements to "
2306 
        "form the final results that are placed again in VMAC registers. "
2307 
        "Intermediate result is placed into vector/floating-point register vfrD. "
2308 
        "If any of the final results exceeds min/max value, it is saturated.",
2309 
        "",
2310 
        "vfrD[15:0] <- sat32s(vfrA[15:0] * vfrB[15:0] + VMACLO[31:0])\\"
2311 
        "vfrD[31:16] <- sat32s(vfrA[31:16] * vfrB[31:16] + VMACLO[63:32])\\"
2312 
        "vfrD[47:32] <- sat32s(vfrA[47:32] * vfrB[47:32] + VMACHI[31:0])\\"
2313 
        "vfrD[63:48] <- sat32s(vfrA[63:48] * vfrB[63:48] + VMACHI[63:32])\\",
2314 
        "None", ORVDX64I,},
2315 
 
2316 
{"lv.msubs.h", "Vector Half-Word Elements Multiply Subtract Signed Saturated",
2317 
        "The signed half-word elements of vector/floating-point register vfrA are multiplied "
2318 
        "by the signed half-word elements of vector/floating-point register vfrB to form "
2319 
        "intermediate results. They are subtracted from the signed half-word VMAC elements to "
2320 
        "form the final results that are placed again in VMAC registers. "
2321 
        "Intermediate result is placed into vector/floating-point register vfrD. "
2322 
        "If any of the final results exceeds min/max value, it is saturated.",
2323 
        "",
2324 
        "vfrD[15:0] <- sat32s(VMACLO[31:0] - vfrA[15:0] * vfrB[15:0])\\"
2325 
        "vfrD[31:16] <- sat32s(VMACLO[63:32] - vfrA[31:16] * vfrB[31:16])\\"
2326 
        "vfrD[47:32] <- sat32s(VMACHI[31:0] - vfrA[47:32] * vfrB[47:32])\\"
2327 
        "vfrD[63:48] <- sat32s(VMACHI[63:32] - vfrA[63:48] * vfrB[63:48])\\",
2328 
        "None", ORVDX64I,},
2329 
 
2330 95 lampret 
{"lv.muls.h", "Vector Half-Word Elements Multiply Signed Saturated",
2331 
        "The signed half-word elements of vector/floating-point register vfrA are multiplied "
2332 
        "by the signed half-word elements of vector/floating-point register vfrB to form "
2333 
        "the results. "
2334 
        "The result is placed into vector/floating-point register vfrD. "
2335 
        "If any of the final results exceeds min/max value, it is saturated.",
2336 87 lampret 
        "",
2337 95 lampret 
        "vfrD[15:0] <- sat32s(vfrA[15:0] * vfrB[15:0])\\"
2338 
        "vfrD[31:16] <- sat32s(vfrA[31:16] * vfrB[31:16])\\"
2339 
        "vfrD[47:32] <- sat32s(vfrA[47:32] * vfrB[47:32])\\"
2340 
        "vfrD[63:48] <- sat32s(vfrA[63:48] * vfrB[63:48])\\",
2341 
        "None", ORVDX64II,},
2342 87 lampret 
 
2343 95 lampret 
{"lv.cust1", "Reserved for Custom Vector Instructions",
2344 
        "This fake instruction only allocates instruction set space for custom instructions. "
2345 
        "Custom instructions are those that are not defined by the architecture, but instead "
2346 
        "by the implementation itself.",
2347 
        "N/A",
2348 
        "N/A",
2349 
        "N/A", ORVDX64II,},
2350 87 lampret 
 
2351 95 lampret 
{"lv.cust2", "Reserved for Custom Vector Instructions",
2352 
        "This fake instruction only allocates instruction set space for custom instructions. "
2353 
        "Custom instructions are those that are not defined by the architecture, but instead "
2354 
        "by the implementation itself.",
2355 
        "N/A",
2356 
        "N/A",
2357 
        "N/A", ORVDX64II,},
2358 87 lampret 
 
2359 95 lampret 
{"lv.cust3", "Reserved for Custom Vector Instructions",
2360 
        "This fake instruction only allocates instruction set space for custom instructions. "
2361 
        "Custom instructions are those that are not defined by the architecture, but instead "
2362 
        "by the implementation itself.",
2363 
        "N/A",
2364 
        "N/A",
2365 
        "N/A", ORVDX64II,},
2366 
 
2367 
{"lv.cust4", "Reserved for Custom Vector Instructions",
2368 
        "This fake instruction only allocates instruction set space for custom instructions. "
2369 
        "Custom instructions are those that are not defined by the architecture, but instead "
2370 
        "by the implementation itself.",
2371 
        "N/A",
2372 
        "N/A",
2373 
        "N/A", ORVDX64II,},
2374 
 
2375 
/**** L/S for ORFPX/ORVDX ***/
2376 
 
2377 
{"lvf.ld", "Load Vector/Floating-Point Double Word",
2378 
        "The contents of vector/floating-point "
2379 
        "register vfrA is used as effective address. The double word in memory "
2380 
        "addressed by EA is loaded into vector/floating-point register vfrD. ",
2381 
        "N/A",
2382 
        "EA <- vfrA[63:0]\\rD[63:0] <- (EA)[63:0]",
2383 
        "TLB miss\\Page fault\\Bus error", ORFPX64I,},
2384 
 
2385 
{"lvf.lw", "Load Vector/Floating-Point Single Word",
2386 
        "The contents of vector/floating-point "
2387 
        "register vfrA is used as effective address. The double word in memory "
2388 
        "addressed by EA is loaded into vector/floating-point register vfrD. ",
2389 
        "EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
2390 
        "EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
2391 
        "TLB miss\\Page fault\\Bus error", ORFPX32I,},
2392 
 
2393 
{"lvf.sd", "Store Vector/Floating-Point Double Word",
2394 
        "The contents of vector/floating-point "
2395 
        "register vfrA is used as effective address. The double word in vector/floating-point "
2396 
        "register vrfB is stored to memory location addresses by EA. ",
2397 
        "N/A",
2398 
        "EA <- vfrA[63:0]\\rD[63:0] <- (EA)[63:0]",
2399 
        "TLB miss\\Page fault\\Bus error", ORFPX64I,},
2400 
 
2401 
{"lvf.sw", "Store Vector/Floating-Point Single Word",
2402 
        "The contents of vector/floating-point "
2403 
        "register vfrA is used as effective address. The single word in vector/floating-point "
2404 
        "register vrfB is stored to memory location addresses by EA. ",
2405 
        "EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
2406 
        "EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
2407 
        "TLB miss\\Page fault\\Bus error", ORFPX32I,},
2408 
 
2409 87 lampret 
{"", "", "", "", "", "", 0}
2410 
 
2411 14 lampret 
};
2412 
 
2413 
struct or1k_isa_classes {
2414 
        char *title;
2415 
        char *desc;
2416 
        char *table;
2417 
} or1k_isa_classes[] = {
2418 
 
2419 87 lampret 
{ "", "x", "-&-\\", },
2420 
{ "", "x", "ORBIS32 I&Required\\", },
2421 
{ "", "x", "ORBIS32 II&Optional\\", },
2422 
{ "", "x", "ORBIS64 I&Required\\", },
2423 
{ "", "x", "ORBIS64 II&Optional\\", },
2424 
{ "", "x", "ORFPX32 I&Required\\", },
2425 
{ "", "x", "ORFPX32 II&Optional\\", },
2426 
{ "", "x", "ORFPX64 I&Required\\", },
2427 
{ "", "x", "ORFPX64 II&Optional\\", },
2428 
{ "", "x", "ORVDX64 I&Required\\", },
2429 
{ "", "x", "ORVDX64 II&Optional\\", },
2430 
{ "", "x", "&\\", },
2431 14 lampret 
 
2432 
};
2433 87 lampret 
 
2434 
struct or1k_order {
2435 
        char *title;
2436 
        unsigned long classes;
2437 
} or1k_order[] = {
2438 
 
2439 
{ "ORBIS32/64", (1<<ORBIS32I)>>1 | (1<<ORBIS32II)>>1 | (1<<ORBIS64I)>>1 | (1<<ORBIS64II)>>1, },
2440 
{ "ORFPX32/64", (1<<ORFPX32I)>>1 | (1<<ORFPX32II)>>1 | (1<<ORFPX64I)>>1 | (1<<ORFPX64II)>>1, },
2441 
{ "ORVDX64", (1<<ORVDX64I)>>1 | (1<<ORVDX64II)>>1, },
2442 
{ "", 0, },
2443 
 
2444 
};

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