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#ifndef _UART_H_

#define _UART_H_

#define UART_RX         0        /* In:  Receive buffer (DLAB=0) */

#define UART_TX         0        /* Out: Transmit buffer (DLAB=0) */

#define UART_DLL        0        /* Out: Divisor Latch Low (DLAB=1) */

#define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */

#define UART_IER        1       /* Out: Interrupt Enable Register */

#define UART_IIR        2       /* In:  Interrupt ID Register */

#define UART_FCR        2       /* Out: FIFO Control Register */

#define UART_EFR        2       /* I/O: Extended Features Register */

                                /* (DLAB=1, 16C660 only) */

#define UART_LCR        3       /* Out: Line Control Register */

#define UART_MCR        4       /* Out: Modem Control Register */

#define UART_LSR        5       /* In:  Line Status Register */

#define UART_MSR        6       /* In:  Modem Status Register */

#define UART_SCR        7       /* I/O: Scratch Register */

/*

 * These are the definitions for the FIFO Control Register

 * (16650 only)

 */

#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */

#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */

#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */

#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */

#define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */

#define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */

#define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */

#define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */

#define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */

/* 16650 redefinitions */

#define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */

#define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */

#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */

#define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */

#define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */

#define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */

#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */

#define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */

/*

 * These are the definitions for the Line Control Register

 *

 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting

 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.

 */

#define UART_LCR_DLAB   0x80    /* Divisor latch access bit */

#define UART_LCR_SBC    0x40    /* Set break control */

#define UART_LCR_SPAR   0x20    /* Stick parity (?) */

#define UART_LCR_EPAR   0x10    /* Even parity select */

#define UART_LCR_PARITY 0x08    /* Parity Enable */

#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */

#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */

#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */

#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */

#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */

/*

 * These are the definitions for the Line Status Register

 */

#define UART_LSR_TEMT   0x40    /* Transmitter empty */

#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */

#define UART_LSR_BI     0x10    /* Break interrupt indicator */

#define UART_LSR_FE     0x08    /* Frame error indicator */

#define UART_LSR_PE     0x04    /* Parity error indicator */

#define UART_LSR_OE     0x02    /* Overrun error indicator */

#define UART_LSR_DR     0x01    /* Receiver data ready */

/*

 * These are the definitions for the Interrupt Identification Register

 */

#define UART_IIR_NO_INT 0x01    /* No interrupts pending */

#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */

#define UART_IIR_MSI    0x00    /* Modem status interrupt */

#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */

#define UART_IIR_TOI    0x0c    /* Receive time out interrupt */

#define UART_IIR_RDI    0x04    /* Receiver data interrupt */

#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */

/*

 * These are the definitions for the Interrupt Enable Register

 */

#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */

#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */

#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */

#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */

/*

 * These are the definitions for the Modem Control Register

 */

#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */

#define UART_MCR_OUT2   0x08    /* Out2 complement */

#define UART_MCR_OUT1   0x04    /* Out1 complement */

#define UART_MCR_RTS    0x02    /* RTS complement */

#define UART_MCR_DTR    0x01    /* DTR complement */

/*

 * These are the definitions for the Modem Status Register

 */

#define UART_MSR_DCD    0x80    /* Data Carrier Detect */

#define UART_MSR_RI     0x40    /* Ring Indicator */

#define UART_MSR_DSR    0x20    /* Data Set Ready */

#define UART_MSR_CTS    0x10    /* Clear to Send */

#define UART_MSR_DDCD   0x08    /* Delta DCD */

#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */

#define UART_MSR_DDSR   0x02    /* Delta DSR */

#define UART_MSR_DCTS   0x01    /* Delta CTS */

#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */

/*

 * These are the definitions for the Extended Features Register

 * (StarTech 16C660 only, when DLAB=1)

 */

#define UART_EFR_CTS    0x80    /* CTS flow control */

#define UART_EFR_RTS    0x40    /* RTS flow control */

#define UART_EFR_SCD    0x20    /* Special character detect */

#define UART_EFR_ENI    0x10    /* Enhanced Interrupt */

#endif /* _UART_H_ */