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578 |
markom |
/* Target-dependent code for Mitsubishi D10V, for GDB.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Contributed by Martin Hunt, hunt@cygnus.com */
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#include "defs.h"
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#include "frame.h"
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#include "obstack.h"
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#include "symtab.h"
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#include "gdbtypes.h"
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#include "gdbcmd.h"
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#include "gdbcore.h"
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#include "gdb_string.h"
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#include "value.h"
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#include "inferior.h"
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#include "dis-asm.h"
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#include "symfile.h"
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#include "objfiles.h"
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#include "language.h"
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#include "arch-utils.h"
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#include "regcache.h"
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#include "floatformat.h"
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#include "sim-d10v.h"
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#undef XMALLOC
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#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
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struct frame_extra_info
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{
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CORE_ADDR return_pc;
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int frameless;
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int size;
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};
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struct gdbarch_tdep
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{
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int a0_regnum;
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int nr_dmap_regs;
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unsigned long (*dmap_register) (int nr);
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unsigned long (*imap_register) (int nr);
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};
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/* These are the addresses the D10V-EVA board maps data and
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instruction memory to. */
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#define DMEM_START 0x2000000
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#define IMEM_START 0x1000000
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#define STACK_START 0x0007ffe
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/* d10v register names. */
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enum
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{
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R0_REGNUM = 0,
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LR_REGNUM = 13,
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PSW_REGNUM = 16,
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NR_IMAP_REGS = 2,
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NR_A_REGS = 2
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};
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#define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
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#define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
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/* d10v calling convention. */
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#define ARG1_REGNUM R0_REGNUM
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#define ARGN_REGNUM 3
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#define RET1_REGNUM R0_REGNUM
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/* Local functions */
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extern void _initialize_d10v_tdep (void);
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static void d10v_eva_prepare_to_trace (void);
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static void d10v_eva_get_trace_data (void);
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static int prologue_find_regs (unsigned short op, struct frame_info *fi,
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CORE_ADDR addr);
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static void d10v_frame_init_saved_regs (struct frame_info *);
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static void do_d10v_pop_frame (struct frame_info *fi);
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static int
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d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame)
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{
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return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START);
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}
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static CORE_ADDR
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d10v_stack_align (CORE_ADDR len)
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{
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return (len + 1) & ~1;
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}
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/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
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EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
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and TYPE is the type (which is known to be struct, union or array).
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The d10v returns anything less than 8 bytes in size in
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registers. */
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static int
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d10v_use_struct_convention (int gcc_p, struct type *type)
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{
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return (TYPE_LENGTH (type) > 8);
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}
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static unsigned char *
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d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
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{
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static unsigned char breakpoint[] =
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{0x2f, 0x90, 0x5e, 0x00};
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*lenptr = sizeof (breakpoint);
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return breakpoint;
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}
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/* Map the REG_NR onto an ascii name. Return NULL or an empty string
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when the reg_nr isn't valid. */
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enum ts2_regnums
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{
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TS2_IMAP0_REGNUM = 32,
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TS2_DMAP_REGNUM = 34,
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TS2_NR_DMAP_REGS = 1,
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TS2_A0_REGNUM = 35
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};
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static char *
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d10v_ts2_register_name (int reg_nr)
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{
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static char *register_names[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
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"rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
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"imap0", "imap1", "dmap", "a0", "a1"
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};
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if (reg_nr < 0)
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return NULL;
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if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
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return NULL;
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return register_names[reg_nr];
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}
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enum ts3_regnums
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{
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TS3_IMAP0_REGNUM = 36,
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TS3_DMAP0_REGNUM = 38,
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TS3_NR_DMAP_REGS = 4,
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TS3_A0_REGNUM = 32
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};
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static char *
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d10v_ts3_register_name (int reg_nr)
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{
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static char *register_names[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
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"rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
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"a0", "a1",
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"spi", "spu",
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"imap0", "imap1",
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"dmap0", "dmap1", "dmap2", "dmap3"
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};
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if (reg_nr < 0)
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return NULL;
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if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
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return NULL;
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return register_names[reg_nr];
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}
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/* Access the DMAP/IMAP registers in a target independent way.
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Divide the D10V's 64k data space into four 16k segments:
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0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
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0xc000 -- 0xffff.
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On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
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0x7fff) always map to the on-chip data RAM, and the fourth always
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maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
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unified memory or instruction memory, under the control of the
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single DMAP register.
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On the TS3, there are four DMAP registers, each of which controls
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one of the segments. */
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static unsigned long
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d10v_ts2_dmap_register (int reg_nr)
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{
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switch (reg_nr)
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{
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case 0:
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case 1:
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return 0x2000;
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case 2:
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return read_register (TS2_DMAP_REGNUM);
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default:
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return 0;
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}
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}
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static unsigned long
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d10v_ts3_dmap_register (int reg_nr)
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{
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return read_register (TS3_DMAP0_REGNUM + reg_nr);
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}
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static unsigned long
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d10v_dmap_register (int reg_nr)
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{
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return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
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}
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static unsigned long
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d10v_ts2_imap_register (int reg_nr)
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{
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return read_register (TS2_IMAP0_REGNUM + reg_nr);
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}
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static unsigned long
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d10v_ts3_imap_register (int reg_nr)
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{
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return read_register (TS3_IMAP0_REGNUM + reg_nr);
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}
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static unsigned long
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d10v_imap_register (int reg_nr)
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{
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return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
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}
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/* MAP GDB's internal register numbering (determined by the layout fo
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the REGISTER_BYTE array) onto the simulator's register
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numbering. */
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static int
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d10v_ts2_register_sim_regno (int nr)
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{
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if (nr >= TS2_IMAP0_REGNUM
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&& nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
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return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
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if (nr == TS2_DMAP_REGNUM)
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return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
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if (nr >= TS2_A0_REGNUM
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&& nr < TS2_A0_REGNUM + NR_A_REGS)
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return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
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return nr;
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}
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static int
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d10v_ts3_register_sim_regno (int nr)
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{
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if (nr >= TS3_IMAP0_REGNUM
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&& nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
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return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
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if (nr >= TS3_DMAP0_REGNUM
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&& nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
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return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
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if (nr >= TS3_A0_REGNUM
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&& nr < TS3_A0_REGNUM + NR_A_REGS)
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return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
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return nr;
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}
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288 |
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289 |
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/* Index within `registers' of the first byte of the space for
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290 |
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register REG_NR. */
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291 |
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292 |
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static int
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293 |
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d10v_register_byte (int reg_nr)
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294 |
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{
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295 |
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if (reg_nr < A0_REGNUM)
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296 |
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return (reg_nr * 2);
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297 |
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else if (reg_nr < (A0_REGNUM + NR_A_REGS))
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298 |
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return (A0_REGNUM * 2
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299 |
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+ (reg_nr - A0_REGNUM) * 8);
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300 |
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else
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301 |
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return (A0_REGNUM * 2
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302 |
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+ NR_A_REGS * 8
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303 |
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+ (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
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304 |
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}
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305 |
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306 |
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/* Number of bytes of storage in the actual machine representation for
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307 |
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register REG_NR. */
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308 |
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309 |
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static int
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310 |
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d10v_register_raw_size (int reg_nr)
|
311 |
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{
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312 |
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if (reg_nr < A0_REGNUM)
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313 |
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return 2;
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314 |
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else if (reg_nr < (A0_REGNUM + NR_A_REGS))
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315 |
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return 8;
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316 |
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else
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317 |
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return 2;
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318 |
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}
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319 |
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|
320 |
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/* Number of bytes of storage in the program's representation
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321 |
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for register N. */
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322 |
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323 |
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static int
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324 |
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d10v_register_virtual_size (int reg_nr)
|
325 |
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{
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326 |
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return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr));
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327 |
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}
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328 |
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329 |
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/* Return the GDB type object for the "standard" data type
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330 |
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of data in register N. */
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331 |
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332 |
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static struct type *
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333 |
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d10v_register_virtual_type (int reg_nr)
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334 |
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{
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335 |
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if (reg_nr >= A0_REGNUM
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336 |
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&& reg_nr < (A0_REGNUM + NR_A_REGS))
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337 |
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return builtin_type_int64;
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338 |
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else if (reg_nr == PC_REGNUM
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339 |
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|| reg_nr == SP_REGNUM)
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340 |
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return builtin_type_int32;
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341 |
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else
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342 |
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return builtin_type_int16;
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343 |
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}
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344 |
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345 |
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/* convert $pc and $sp to/from virtual addresses */
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346 |
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static int
|
347 |
|
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d10v_register_convertible (int nr)
|
348 |
|
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{
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349 |
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return ((nr) == PC_REGNUM || (nr) == SP_REGNUM);
|
350 |
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}
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351 |
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352 |
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static void
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353 |
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d10v_register_convert_to_virtual (int regnum, struct type *type, char *from,
|
354 |
|
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char *to)
|
355 |
|
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{
|
356 |
|
|
ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum));
|
357 |
|
|
if (regnum == PC_REGNUM)
|
358 |
|
|
x = (x << 2) | IMEM_START;
|
359 |
|
|
else
|
360 |
|
|
x |= DMEM_START;
|
361 |
|
|
store_unsigned_integer (to, TYPE_LENGTH (type), x);
|
362 |
|
|
}
|
363 |
|
|
|
364 |
|
|
static void
|
365 |
|
|
d10v_register_convert_to_raw (struct type *type, int regnum, char *from,
|
366 |
|
|
char *to)
|
367 |
|
|
{
|
368 |
|
|
ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type));
|
369 |
|
|
x &= 0x3ffff;
|
370 |
|
|
if (regnum == PC_REGNUM)
|
371 |
|
|
x >>= 2;
|
372 |
|
|
store_unsigned_integer (to, 2, x);
|
373 |
|
|
}
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
static CORE_ADDR
|
377 |
|
|
d10v_make_daddr (CORE_ADDR x)
|
378 |
|
|
{
|
379 |
|
|
return ((x) | DMEM_START);
|
380 |
|
|
}
|
381 |
|
|
|
382 |
|
|
static CORE_ADDR
|
383 |
|
|
d10v_make_iaddr (CORE_ADDR x)
|
384 |
|
|
{
|
385 |
|
|
return (((x) << 2) | IMEM_START);
|
386 |
|
|
}
|
387 |
|
|
|
388 |
|
|
static int
|
389 |
|
|
d10v_daddr_p (CORE_ADDR x)
|
390 |
|
|
{
|
391 |
|
|
return (((x) & 0x3000000) == DMEM_START);
|
392 |
|
|
}
|
393 |
|
|
|
394 |
|
|
static int
|
395 |
|
|
d10v_iaddr_p (CORE_ADDR x)
|
396 |
|
|
{
|
397 |
|
|
return (((x) & 0x3000000) == IMEM_START);
|
398 |
|
|
}
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
static CORE_ADDR
|
402 |
|
|
d10v_convert_iaddr_to_raw (CORE_ADDR x)
|
403 |
|
|
{
|
404 |
|
|
return (((x) >> 2) & 0xffff);
|
405 |
|
|
}
|
406 |
|
|
|
407 |
|
|
static CORE_ADDR
|
408 |
|
|
d10v_convert_daddr_to_raw (CORE_ADDR x)
|
409 |
|
|
{
|
410 |
|
|
return ((x) & 0xffff);
|
411 |
|
|
}
|
412 |
|
|
|
413 |
|
|
/* Store the address of the place in which to copy the structure the
|
414 |
|
|
subroutine will return. This is called from call_function.
|
415 |
|
|
|
416 |
|
|
We store structs through a pointer passed in the first Argument
|
417 |
|
|
register. */
|
418 |
|
|
|
419 |
|
|
static void
|
420 |
|
|
d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
|
421 |
|
|
{
|
422 |
|
|
write_register (ARG1_REGNUM, (addr));
|
423 |
|
|
}
|
424 |
|
|
|
425 |
|
|
/* Write into appropriate registers a function return value
|
426 |
|
|
of type TYPE, given in virtual format.
|
427 |
|
|
|
428 |
|
|
Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
|
429 |
|
|
|
430 |
|
|
static void
|
431 |
|
|
d10v_store_return_value (struct type *type, char *valbuf)
|
432 |
|
|
{
|
433 |
|
|
write_register_bytes (REGISTER_BYTE (RET1_REGNUM),
|
434 |
|
|
valbuf,
|
435 |
|
|
TYPE_LENGTH (type));
|
436 |
|
|
}
|
437 |
|
|
|
438 |
|
|
/* Extract from an array REGBUF containing the (raw) register state
|
439 |
|
|
the address in which a function should return its structure value,
|
440 |
|
|
as a CORE_ADDR (or an expression that can be used as one). */
|
441 |
|
|
|
442 |
|
|
static CORE_ADDR
|
443 |
|
|
d10v_extract_struct_value_address (char *regbuf)
|
444 |
|
|
{
|
445 |
|
|
return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM),
|
446 |
|
|
REGISTER_RAW_SIZE (ARG1_REGNUM))
|
447 |
|
|
| DMEM_START);
|
448 |
|
|
}
|
449 |
|
|
|
450 |
|
|
static CORE_ADDR
|
451 |
|
|
d10v_frame_saved_pc (struct frame_info *frame)
|
452 |
|
|
{
|
453 |
|
|
return ((frame)->extra_info->return_pc);
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
/* Immediately after a function call, return the saved pc. We can't
|
457 |
|
|
use frame->return_pc beause that is determined by reading R13 off
|
458 |
|
|
the stack and that may not be written yet. */
|
459 |
|
|
|
460 |
|
|
static CORE_ADDR
|
461 |
|
|
d10v_saved_pc_after_call (struct frame_info *frame)
|
462 |
|
|
{
|
463 |
|
|
return ((read_register (LR_REGNUM) << 2)
|
464 |
|
|
| IMEM_START);
|
465 |
|
|
}
|
466 |
|
|
|
467 |
|
|
/* Discard from the stack the innermost frame, restoring all saved
|
468 |
|
|
registers. */
|
469 |
|
|
|
470 |
|
|
static void
|
471 |
|
|
d10v_pop_frame (void)
|
472 |
|
|
{
|
473 |
|
|
generic_pop_current_frame (do_d10v_pop_frame);
|
474 |
|
|
}
|
475 |
|
|
|
476 |
|
|
static void
|
477 |
|
|
do_d10v_pop_frame (struct frame_info *fi)
|
478 |
|
|
{
|
479 |
|
|
CORE_ADDR fp;
|
480 |
|
|
int regnum;
|
481 |
|
|
char raw_buffer[8];
|
482 |
|
|
|
483 |
|
|
fp = FRAME_FP (fi);
|
484 |
|
|
/* fill out fsr with the address of where each */
|
485 |
|
|
/* register was stored in the frame */
|
486 |
|
|
d10v_frame_init_saved_regs (fi);
|
487 |
|
|
|
488 |
|
|
/* now update the current registers with the old values */
|
489 |
|
|
for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
|
490 |
|
|
{
|
491 |
|
|
if (fi->saved_regs[regnum])
|
492 |
|
|
{
|
493 |
|
|
read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
|
494 |
|
|
write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
|
495 |
|
|
}
|
496 |
|
|
}
|
497 |
|
|
for (regnum = 0; regnum < SP_REGNUM; regnum++)
|
498 |
|
|
{
|
499 |
|
|
if (fi->saved_regs[regnum])
|
500 |
|
|
{
|
501 |
|
|
write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
|
502 |
|
|
}
|
503 |
|
|
}
|
504 |
|
|
if (fi->saved_regs[PSW_REGNUM])
|
505 |
|
|
{
|
506 |
|
|
write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
|
507 |
|
|
}
|
508 |
|
|
|
509 |
|
|
write_register (PC_REGNUM, read_register (LR_REGNUM));
|
510 |
|
|
write_register (SP_REGNUM, fp + fi->extra_info->size);
|
511 |
|
|
target_store_registers (-1);
|
512 |
|
|
flush_cached_frames ();
|
513 |
|
|
}
|
514 |
|
|
|
515 |
|
|
static int
|
516 |
|
|
check_prologue (unsigned short op)
|
517 |
|
|
{
|
518 |
|
|
/* st rn, @-sp */
|
519 |
|
|
if ((op & 0x7E1F) == 0x6C1F)
|
520 |
|
|
return 1;
|
521 |
|
|
|
522 |
|
|
/* st2w rn, @-sp */
|
523 |
|
|
if ((op & 0x7E3F) == 0x6E1F)
|
524 |
|
|
return 1;
|
525 |
|
|
|
526 |
|
|
/* subi sp, n */
|
527 |
|
|
if ((op & 0x7FE1) == 0x01E1)
|
528 |
|
|
return 1;
|
529 |
|
|
|
530 |
|
|
/* mv r11, sp */
|
531 |
|
|
if (op == 0x417E)
|
532 |
|
|
return 1;
|
533 |
|
|
|
534 |
|
|
/* nop */
|
535 |
|
|
if (op == 0x5E00)
|
536 |
|
|
return 1;
|
537 |
|
|
|
538 |
|
|
/* st rn, @sp */
|
539 |
|
|
if ((op & 0x7E1F) == 0x681E)
|
540 |
|
|
return 1;
|
541 |
|
|
|
542 |
|
|
/* st2w rn, @sp */
|
543 |
|
|
if ((op & 0x7E3F) == 0x3A1E)
|
544 |
|
|
return 1;
|
545 |
|
|
|
546 |
|
|
return 0;
|
547 |
|
|
}
|
548 |
|
|
|
549 |
|
|
static CORE_ADDR
|
550 |
|
|
d10v_skip_prologue (CORE_ADDR pc)
|
551 |
|
|
{
|
552 |
|
|
unsigned long op;
|
553 |
|
|
unsigned short op1, op2;
|
554 |
|
|
CORE_ADDR func_addr, func_end;
|
555 |
|
|
struct symtab_and_line sal;
|
556 |
|
|
|
557 |
|
|
/* If we have line debugging information, then the end of the */
|
558 |
|
|
/* prologue should the first assembly instruction of the first source line */
|
559 |
|
|
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
|
560 |
|
|
{
|
561 |
|
|
sal = find_pc_line (func_addr, 0);
|
562 |
|
|
if (sal.end && sal.end < func_end)
|
563 |
|
|
return sal.end;
|
564 |
|
|
}
|
565 |
|
|
|
566 |
|
|
if (target_read_memory (pc, (char *) &op, 4))
|
567 |
|
|
return pc; /* Can't access it -- assume no prologue. */
|
568 |
|
|
|
569 |
|
|
while (1)
|
570 |
|
|
{
|
571 |
|
|
op = (unsigned long) read_memory_integer (pc, 4);
|
572 |
|
|
if ((op & 0xC0000000) == 0xC0000000)
|
573 |
|
|
{
|
574 |
|
|
/* long instruction */
|
575 |
|
|
if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
|
576 |
|
|
((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
|
577 |
|
|
((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
|
578 |
|
|
break;
|
579 |
|
|
}
|
580 |
|
|
else
|
581 |
|
|
{
|
582 |
|
|
/* short instructions */
|
583 |
|
|
if ((op & 0xC0000000) == 0x80000000)
|
584 |
|
|
{
|
585 |
|
|
op2 = (op & 0x3FFF8000) >> 15;
|
586 |
|
|
op1 = op & 0x7FFF;
|
587 |
|
|
}
|
588 |
|
|
else
|
589 |
|
|
{
|
590 |
|
|
op1 = (op & 0x3FFF8000) >> 15;
|
591 |
|
|
op2 = op & 0x7FFF;
|
592 |
|
|
}
|
593 |
|
|
if (check_prologue (op1))
|
594 |
|
|
{
|
595 |
|
|
if (!check_prologue (op2))
|
596 |
|
|
{
|
597 |
|
|
/* if the previous opcode was really part of the prologue */
|
598 |
|
|
/* and not just a NOP, then we want to break after both instructions */
|
599 |
|
|
if (op1 != 0x5E00)
|
600 |
|
|
pc += 4;
|
601 |
|
|
break;
|
602 |
|
|
}
|
603 |
|
|
}
|
604 |
|
|
else
|
605 |
|
|
break;
|
606 |
|
|
}
|
607 |
|
|
pc += 4;
|
608 |
|
|
}
|
609 |
|
|
return pc;
|
610 |
|
|
}
|
611 |
|
|
|
612 |
|
|
/* Given a GDB frame, determine the address of the calling function's frame.
|
613 |
|
|
This will be used to create a new GDB frame struct, and then
|
614 |
|
|
INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
|
615 |
|
|
*/
|
616 |
|
|
|
617 |
|
|
static CORE_ADDR
|
618 |
|
|
d10v_frame_chain (struct frame_info *fi)
|
619 |
|
|
{
|
620 |
|
|
d10v_frame_init_saved_regs (fi);
|
621 |
|
|
|
622 |
|
|
if (fi->extra_info->return_pc == IMEM_START
|
623 |
|
|
|| inside_entry_file (fi->extra_info->return_pc))
|
624 |
|
|
return (CORE_ADDR) 0;
|
625 |
|
|
|
626 |
|
|
if (!fi->saved_regs[FP_REGNUM])
|
627 |
|
|
{
|
628 |
|
|
if (!fi->saved_regs[SP_REGNUM]
|
629 |
|
|
|| fi->saved_regs[SP_REGNUM] == STACK_START)
|
630 |
|
|
return (CORE_ADDR) 0;
|
631 |
|
|
|
632 |
|
|
return fi->saved_regs[SP_REGNUM];
|
633 |
|
|
}
|
634 |
|
|
|
635 |
|
|
if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
|
636 |
|
|
REGISTER_RAW_SIZE (FP_REGNUM)))
|
637 |
|
|
return (CORE_ADDR) 0;
|
638 |
|
|
|
639 |
|
|
return d10v_make_daddr (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
|
640 |
|
|
REGISTER_RAW_SIZE (FP_REGNUM)));
|
641 |
|
|
}
|
642 |
|
|
|
643 |
|
|
static int next_addr, uses_frame;
|
644 |
|
|
|
645 |
|
|
static int
|
646 |
|
|
prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr)
|
647 |
|
|
{
|
648 |
|
|
int n;
|
649 |
|
|
|
650 |
|
|
/* st rn, @-sp */
|
651 |
|
|
if ((op & 0x7E1F) == 0x6C1F)
|
652 |
|
|
{
|
653 |
|
|
n = (op & 0x1E0) >> 5;
|
654 |
|
|
next_addr -= 2;
|
655 |
|
|
fi->saved_regs[n] = next_addr;
|
656 |
|
|
return 1;
|
657 |
|
|
}
|
658 |
|
|
|
659 |
|
|
/* st2w rn, @-sp */
|
660 |
|
|
else if ((op & 0x7E3F) == 0x6E1F)
|
661 |
|
|
{
|
662 |
|
|
n = (op & 0x1E0) >> 5;
|
663 |
|
|
next_addr -= 4;
|
664 |
|
|
fi->saved_regs[n] = next_addr;
|
665 |
|
|
fi->saved_regs[n + 1] = next_addr + 2;
|
666 |
|
|
return 1;
|
667 |
|
|
}
|
668 |
|
|
|
669 |
|
|
/* subi sp, n */
|
670 |
|
|
if ((op & 0x7FE1) == 0x01E1)
|
671 |
|
|
{
|
672 |
|
|
n = (op & 0x1E) >> 1;
|
673 |
|
|
if (n == 0)
|
674 |
|
|
n = 16;
|
675 |
|
|
next_addr -= n;
|
676 |
|
|
return 1;
|
677 |
|
|
}
|
678 |
|
|
|
679 |
|
|
/* mv r11, sp */
|
680 |
|
|
if (op == 0x417E)
|
681 |
|
|
{
|
682 |
|
|
uses_frame = 1;
|
683 |
|
|
return 1;
|
684 |
|
|
}
|
685 |
|
|
|
686 |
|
|
/* nop */
|
687 |
|
|
if (op == 0x5E00)
|
688 |
|
|
return 1;
|
689 |
|
|
|
690 |
|
|
/* st rn, @sp */
|
691 |
|
|
if ((op & 0x7E1F) == 0x681E)
|
692 |
|
|
{
|
693 |
|
|
n = (op & 0x1E0) >> 5;
|
694 |
|
|
fi->saved_regs[n] = next_addr;
|
695 |
|
|
return 1;
|
696 |
|
|
}
|
697 |
|
|
|
698 |
|
|
/* st2w rn, @sp */
|
699 |
|
|
if ((op & 0x7E3F) == 0x3A1E)
|
700 |
|
|
{
|
701 |
|
|
n = (op & 0x1E0) >> 5;
|
702 |
|
|
fi->saved_regs[n] = next_addr;
|
703 |
|
|
fi->saved_regs[n + 1] = next_addr + 2;
|
704 |
|
|
return 1;
|
705 |
|
|
}
|
706 |
|
|
|
707 |
|
|
return 0;
|
708 |
|
|
}
|
709 |
|
|
|
710 |
|
|
/* Put here the code to store, into fi->saved_regs, the addresses of
|
711 |
|
|
the saved registers of frame described by FRAME_INFO. This
|
712 |
|
|
includes special registers such as pc and fp saved in special ways
|
713 |
|
|
in the stack frame. sp is even more special: the address we return
|
714 |
|
|
for it IS the sp for the next frame. */
|
715 |
|
|
|
716 |
|
|
static void
|
717 |
|
|
d10v_frame_init_saved_regs (struct frame_info *fi)
|
718 |
|
|
{
|
719 |
|
|
CORE_ADDR fp, pc;
|
720 |
|
|
unsigned long op;
|
721 |
|
|
unsigned short op1, op2;
|
722 |
|
|
int i;
|
723 |
|
|
|
724 |
|
|
fp = fi->frame;
|
725 |
|
|
memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
|
726 |
|
|
next_addr = 0;
|
727 |
|
|
|
728 |
|
|
pc = get_pc_function_start (fi->pc);
|
729 |
|
|
|
730 |
|
|
uses_frame = 0;
|
731 |
|
|
while (1)
|
732 |
|
|
{
|
733 |
|
|
op = (unsigned long) read_memory_integer (pc, 4);
|
734 |
|
|
if ((op & 0xC0000000) == 0xC0000000)
|
735 |
|
|
{
|
736 |
|
|
/* long instruction */
|
737 |
|
|
if ((op & 0x3FFF0000) == 0x01FF0000)
|
738 |
|
|
{
|
739 |
|
|
/* add3 sp,sp,n */
|
740 |
|
|
short n = op & 0xFFFF;
|
741 |
|
|
next_addr += n;
|
742 |
|
|
}
|
743 |
|
|
else if ((op & 0x3F0F0000) == 0x340F0000)
|
744 |
|
|
{
|
745 |
|
|
/* st rn, @(offset,sp) */
|
746 |
|
|
short offset = op & 0xFFFF;
|
747 |
|
|
short n = (op >> 20) & 0xF;
|
748 |
|
|
fi->saved_regs[n] = next_addr + offset;
|
749 |
|
|
}
|
750 |
|
|
else if ((op & 0x3F1F0000) == 0x350F0000)
|
751 |
|
|
{
|
752 |
|
|
/* st2w rn, @(offset,sp) */
|
753 |
|
|
short offset = op & 0xFFFF;
|
754 |
|
|
short n = (op >> 20) & 0xF;
|
755 |
|
|
fi->saved_regs[n] = next_addr + offset;
|
756 |
|
|
fi->saved_regs[n + 1] = next_addr + offset + 2;
|
757 |
|
|
}
|
758 |
|
|
else
|
759 |
|
|
break;
|
760 |
|
|
}
|
761 |
|
|
else
|
762 |
|
|
{
|
763 |
|
|
/* short instructions */
|
764 |
|
|
if ((op & 0xC0000000) == 0x80000000)
|
765 |
|
|
{
|
766 |
|
|
op2 = (op & 0x3FFF8000) >> 15;
|
767 |
|
|
op1 = op & 0x7FFF;
|
768 |
|
|
}
|
769 |
|
|
else
|
770 |
|
|
{
|
771 |
|
|
op1 = (op & 0x3FFF8000) >> 15;
|
772 |
|
|
op2 = op & 0x7FFF;
|
773 |
|
|
}
|
774 |
|
|
if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc))
|
775 |
|
|
break;
|
776 |
|
|
}
|
777 |
|
|
pc += 4;
|
778 |
|
|
}
|
779 |
|
|
|
780 |
|
|
fi->extra_info->size = -next_addr;
|
781 |
|
|
|
782 |
|
|
if (!(fp & 0xffff))
|
783 |
|
|
fp = d10v_make_daddr (read_register (SP_REGNUM));
|
784 |
|
|
|
785 |
|
|
for (i = 0; i < NUM_REGS - 1; i++)
|
786 |
|
|
if (fi->saved_regs[i])
|
787 |
|
|
{
|
788 |
|
|
fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
|
789 |
|
|
}
|
790 |
|
|
|
791 |
|
|
if (fi->saved_regs[LR_REGNUM])
|
792 |
|
|
{
|
793 |
|
|
CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM));
|
794 |
|
|
fi->extra_info->return_pc = d10v_make_iaddr (return_pc);
|
795 |
|
|
}
|
796 |
|
|
else
|
797 |
|
|
{
|
798 |
|
|
fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM));
|
799 |
|
|
}
|
800 |
|
|
|
801 |
|
|
/* th SP is not normally (ever?) saved, but check anyway */
|
802 |
|
|
if (!fi->saved_regs[SP_REGNUM])
|
803 |
|
|
{
|
804 |
|
|
/* if the FP was saved, that means the current FP is valid, */
|
805 |
|
|
/* otherwise, it isn't being used, so we use the SP instead */
|
806 |
|
|
if (uses_frame)
|
807 |
|
|
fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size;
|
808 |
|
|
else
|
809 |
|
|
{
|
810 |
|
|
fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
|
811 |
|
|
fi->extra_info->frameless = 1;
|
812 |
|
|
fi->saved_regs[FP_REGNUM] = 0;
|
813 |
|
|
}
|
814 |
|
|
}
|
815 |
|
|
}
|
816 |
|
|
|
817 |
|
|
static void
|
818 |
|
|
d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
|
819 |
|
|
{
|
820 |
|
|
fi->extra_info = (struct frame_extra_info *)
|
821 |
|
|
frame_obstack_alloc (sizeof (struct frame_extra_info));
|
822 |
|
|
frame_saved_regs_zalloc (fi);
|
823 |
|
|
|
824 |
|
|
fi->extra_info->frameless = 0;
|
825 |
|
|
fi->extra_info->size = 0;
|
826 |
|
|
fi->extra_info->return_pc = 0;
|
827 |
|
|
|
828 |
|
|
/* The call dummy doesn't save any registers on the stack, so we can
|
829 |
|
|
return now. */
|
830 |
|
|
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
|
831 |
|
|
{
|
832 |
|
|
return;
|
833 |
|
|
}
|
834 |
|
|
else
|
835 |
|
|
{
|
836 |
|
|
d10v_frame_init_saved_regs (fi);
|
837 |
|
|
}
|
838 |
|
|
}
|
839 |
|
|
|
840 |
|
|
static void
|
841 |
|
|
show_regs (char *args, int from_tty)
|
842 |
|
|
{
|
843 |
|
|
int a;
|
844 |
|
|
printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
|
845 |
|
|
(long) read_register (PC_REGNUM),
|
846 |
|
|
(long) d10v_make_iaddr (read_register (PC_REGNUM)),
|
847 |
|
|
(long) read_register (PSW_REGNUM),
|
848 |
|
|
(long) read_register (24),
|
849 |
|
|
(long) read_register (25),
|
850 |
|
|
(long) read_register (23));
|
851 |
|
|
printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
|
852 |
|
|
(long) read_register (0),
|
853 |
|
|
(long) read_register (1),
|
854 |
|
|
(long) read_register (2),
|
855 |
|
|
(long) read_register (3),
|
856 |
|
|
(long) read_register (4),
|
857 |
|
|
(long) read_register (5),
|
858 |
|
|
(long) read_register (6),
|
859 |
|
|
(long) read_register (7));
|
860 |
|
|
printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
|
861 |
|
|
(long) read_register (8),
|
862 |
|
|
(long) read_register (9),
|
863 |
|
|
(long) read_register (10),
|
864 |
|
|
(long) read_register (11),
|
865 |
|
|
(long) read_register (12),
|
866 |
|
|
(long) read_register (13),
|
867 |
|
|
(long) read_register (14),
|
868 |
|
|
(long) read_register (15));
|
869 |
|
|
for (a = 0; a < NR_IMAP_REGS; a++)
|
870 |
|
|
{
|
871 |
|
|
if (a > 0)
|
872 |
|
|
printf_filtered (" ");
|
873 |
|
|
printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
|
874 |
|
|
}
|
875 |
|
|
if (NR_DMAP_REGS == 1)
|
876 |
|
|
printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
|
877 |
|
|
else
|
878 |
|
|
{
|
879 |
|
|
for (a = 0; a < NR_DMAP_REGS; a++)
|
880 |
|
|
{
|
881 |
|
|
printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a));
|
882 |
|
|
}
|
883 |
|
|
printf_filtered ("\n");
|
884 |
|
|
}
|
885 |
|
|
printf_filtered ("A0-A%d", NR_A_REGS - 1);
|
886 |
|
|
for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
|
887 |
|
|
{
|
888 |
|
|
char num[MAX_REGISTER_RAW_SIZE];
|
889 |
|
|
int i;
|
890 |
|
|
printf_filtered (" ");
|
891 |
|
|
read_register_gen (a, (char *) &num);
|
892 |
|
|
for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
|
893 |
|
|
{
|
894 |
|
|
printf_filtered ("%02x", (num[i] & 0xff));
|
895 |
|
|
}
|
896 |
|
|
}
|
897 |
|
|
printf_filtered ("\n");
|
898 |
|
|
}
|
899 |
|
|
|
900 |
|
|
static CORE_ADDR
|
901 |
|
|
d10v_read_pc (ptid_t ptid)
|
902 |
|
|
{
|
903 |
|
|
ptid_t save_ptid;
|
904 |
|
|
CORE_ADDR pc;
|
905 |
|
|
CORE_ADDR retval;
|
906 |
|
|
|
907 |
|
|
save_ptid = inferior_ptid;
|
908 |
|
|
inferior_ptid = ptid;
|
909 |
|
|
pc = (int) read_register (PC_REGNUM);
|
910 |
|
|
inferior_ptid = save_ptid;
|
911 |
|
|
retval = d10v_make_iaddr (pc);
|
912 |
|
|
return retval;
|
913 |
|
|
}
|
914 |
|
|
|
915 |
|
|
static void
|
916 |
|
|
d10v_write_pc (CORE_ADDR val, ptid_t ptid)
|
917 |
|
|
{
|
918 |
|
|
ptid_t save_ptid;
|
919 |
|
|
|
920 |
|
|
save_ptid = inferior_ptid;
|
921 |
|
|
inferior_ptid = ptid;
|
922 |
|
|
write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val));
|
923 |
|
|
inferior_ptid = save_ptid;
|
924 |
|
|
}
|
925 |
|
|
|
926 |
|
|
static CORE_ADDR
|
927 |
|
|
d10v_read_sp (void)
|
928 |
|
|
{
|
929 |
|
|
return (d10v_make_daddr (read_register (SP_REGNUM)));
|
930 |
|
|
}
|
931 |
|
|
|
932 |
|
|
static void
|
933 |
|
|
d10v_write_sp (CORE_ADDR val)
|
934 |
|
|
{
|
935 |
|
|
write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val));
|
936 |
|
|
}
|
937 |
|
|
|
938 |
|
|
static void
|
939 |
|
|
d10v_write_fp (CORE_ADDR val)
|
940 |
|
|
{
|
941 |
|
|
write_register (FP_REGNUM, d10v_convert_daddr_to_raw (val));
|
942 |
|
|
}
|
943 |
|
|
|
944 |
|
|
static CORE_ADDR
|
945 |
|
|
d10v_read_fp (void)
|
946 |
|
|
{
|
947 |
|
|
return (d10v_make_daddr (read_register (FP_REGNUM)));
|
948 |
|
|
}
|
949 |
|
|
|
950 |
|
|
/* Function: push_return_address (pc)
|
951 |
|
|
Set up the return address for the inferior function call.
|
952 |
|
|
Needed for targets where we don't actually execute a JSR/BSR instruction */
|
953 |
|
|
|
954 |
|
|
static CORE_ADDR
|
955 |
|
|
d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
|
956 |
|
|
{
|
957 |
|
|
write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
|
958 |
|
|
return sp;
|
959 |
|
|
}
|
960 |
|
|
|
961 |
|
|
|
962 |
|
|
/* When arguments must be pushed onto the stack, they go on in reverse
|
963 |
|
|
order. The below implements a FILO (stack) to do this. */
|
964 |
|
|
|
965 |
|
|
struct stack_item
|
966 |
|
|
{
|
967 |
|
|
int len;
|
968 |
|
|
struct stack_item *prev;
|
969 |
|
|
void *data;
|
970 |
|
|
};
|
971 |
|
|
|
972 |
|
|
static struct stack_item *push_stack_item (struct stack_item *prev,
|
973 |
|
|
void *contents, int len);
|
974 |
|
|
static struct stack_item *
|
975 |
|
|
push_stack_item (struct stack_item *prev, void *contents, int len)
|
976 |
|
|
{
|
977 |
|
|
struct stack_item *si;
|
978 |
|
|
si = xmalloc (sizeof (struct stack_item));
|
979 |
|
|
si->data = xmalloc (len);
|
980 |
|
|
si->len = len;
|
981 |
|
|
si->prev = prev;
|
982 |
|
|
memcpy (si->data, contents, len);
|
983 |
|
|
return si;
|
984 |
|
|
}
|
985 |
|
|
|
986 |
|
|
static struct stack_item *pop_stack_item (struct stack_item *si);
|
987 |
|
|
static struct stack_item *
|
988 |
|
|
pop_stack_item (struct stack_item *si)
|
989 |
|
|
{
|
990 |
|
|
struct stack_item *dead = si;
|
991 |
|
|
si = si->prev;
|
992 |
|
|
xfree (dead->data);
|
993 |
|
|
xfree (dead);
|
994 |
|
|
return si;
|
995 |
|
|
}
|
996 |
|
|
|
997 |
|
|
|
998 |
|
|
static CORE_ADDR
|
999 |
|
|
d10v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp,
|
1000 |
|
|
int struct_return, CORE_ADDR struct_addr)
|
1001 |
|
|
{
|
1002 |
|
|
int i;
|
1003 |
|
|
int regnum = ARG1_REGNUM;
|
1004 |
|
|
struct stack_item *si = NULL;
|
1005 |
|
|
|
1006 |
|
|
/* Fill in registers and arg lists */
|
1007 |
|
|
for (i = 0; i < nargs; i++)
|
1008 |
|
|
{
|
1009 |
|
|
value_ptr arg = args[i];
|
1010 |
|
|
struct type *type = check_typedef (VALUE_TYPE (arg));
|
1011 |
|
|
char *contents = VALUE_CONTENTS (arg);
|
1012 |
|
|
int len = TYPE_LENGTH (type);
|
1013 |
|
|
/* printf ("push: type=%d len=%d\n", type->code, len); */
|
1014 |
|
|
if (TYPE_CODE (type) == TYPE_CODE_PTR)
|
1015 |
|
|
{
|
1016 |
|
|
/* pointers require special handling - first convert and
|
1017 |
|
|
then store */
|
1018 |
|
|
long val = extract_signed_integer (contents, len);
|
1019 |
|
|
len = 2;
|
1020 |
|
|
if (TYPE_TARGET_TYPE (type)
|
1021 |
|
|
&& (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
|
1022 |
|
|
{
|
1023 |
|
|
/* function pointer */
|
1024 |
|
|
val = d10v_convert_iaddr_to_raw (val);
|
1025 |
|
|
}
|
1026 |
|
|
else if (d10v_iaddr_p (val))
|
1027 |
|
|
{
|
1028 |
|
|
/* also function pointer! */
|
1029 |
|
|
val = d10v_convert_daddr_to_raw (val);
|
1030 |
|
|
}
|
1031 |
|
|
else
|
1032 |
|
|
{
|
1033 |
|
|
/* data pointer */
|
1034 |
|
|
val &= 0xFFFF;
|
1035 |
|
|
}
|
1036 |
|
|
if (regnum <= ARGN_REGNUM)
|
1037 |
|
|
write_register (regnum++, val & 0xffff);
|
1038 |
|
|
else
|
1039 |
|
|
{
|
1040 |
|
|
char ptr[2];
|
1041 |
|
|
/* arg will go onto stack */
|
1042 |
|
|
store_address (ptr, 2, val & 0xffff);
|
1043 |
|
|
si = push_stack_item (si, ptr, 2);
|
1044 |
|
|
}
|
1045 |
|
|
}
|
1046 |
|
|
else
|
1047 |
|
|
{
|
1048 |
|
|
int aligned_regnum = (regnum + 1) & ~1;
|
1049 |
|
|
if (len <= 2 && regnum <= ARGN_REGNUM)
|
1050 |
|
|
/* fits in a single register, do not align */
|
1051 |
|
|
{
|
1052 |
|
|
long val = extract_unsigned_integer (contents, len);
|
1053 |
|
|
write_register (regnum++, val);
|
1054 |
|
|
}
|
1055 |
|
|
else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
|
1056 |
|
|
/* value fits in remaining registers, store keeping left
|
1057 |
|
|
aligned */
|
1058 |
|
|
{
|
1059 |
|
|
int b;
|
1060 |
|
|
regnum = aligned_regnum;
|
1061 |
|
|
for (b = 0; b < (len & ~1); b += 2)
|
1062 |
|
|
{
|
1063 |
|
|
long val = extract_unsigned_integer (&contents[b], 2);
|
1064 |
|
|
write_register (regnum++, val);
|
1065 |
|
|
}
|
1066 |
|
|
if (b < len)
|
1067 |
|
|
{
|
1068 |
|
|
long val = extract_unsigned_integer (&contents[b], 1);
|
1069 |
|
|
write_register (regnum++, (val << 8));
|
1070 |
|
|
}
|
1071 |
|
|
}
|
1072 |
|
|
else
|
1073 |
|
|
{
|
1074 |
|
|
/* arg will go onto stack */
|
1075 |
|
|
regnum = ARGN_REGNUM + 1;
|
1076 |
|
|
si = push_stack_item (si, contents, len);
|
1077 |
|
|
}
|
1078 |
|
|
}
|
1079 |
|
|
}
|
1080 |
|
|
|
1081 |
|
|
while (si)
|
1082 |
|
|
{
|
1083 |
|
|
sp = (sp - si->len) & ~1;
|
1084 |
|
|
write_memory (sp, si->data, si->len);
|
1085 |
|
|
si = pop_stack_item (si);
|
1086 |
|
|
}
|
1087 |
|
|
|
1088 |
|
|
return sp;
|
1089 |
|
|
}
|
1090 |
|
|
|
1091 |
|
|
|
1092 |
|
|
/* Given a return value in `regbuf' with a type `valtype',
|
1093 |
|
|
extract and copy its value into `valbuf'. */
|
1094 |
|
|
|
1095 |
|
|
static void
|
1096 |
|
|
d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES],
|
1097 |
|
|
char *valbuf)
|
1098 |
|
|
{
|
1099 |
|
|
int len;
|
1100 |
|
|
/* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
|
1101 |
|
|
if (TYPE_CODE (type) == TYPE_CODE_PTR
|
1102 |
|
|
&& TYPE_TARGET_TYPE (type)
|
1103 |
|
|
&& (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
|
1104 |
|
|
{
|
1105 |
|
|
/* pointer to function */
|
1106 |
|
|
int num;
|
1107 |
|
|
short snum;
|
1108 |
|
|
snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
|
1109 |
|
|
store_address (valbuf, 4, d10v_make_iaddr (snum));
|
1110 |
|
|
}
|
1111 |
|
|
else if (TYPE_CODE (type) == TYPE_CODE_PTR)
|
1112 |
|
|
{
|
1113 |
|
|
/* pointer to data */
|
1114 |
|
|
int num;
|
1115 |
|
|
short snum;
|
1116 |
|
|
snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
|
1117 |
|
|
store_address (valbuf, 4, d10v_make_daddr (snum));
|
1118 |
|
|
}
|
1119 |
|
|
else
|
1120 |
|
|
{
|
1121 |
|
|
len = TYPE_LENGTH (type);
|
1122 |
|
|
if (len == 1)
|
1123 |
|
|
{
|
1124 |
|
|
unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
|
1125 |
|
|
store_unsigned_integer (valbuf, 1, c);
|
1126 |
|
|
}
|
1127 |
|
|
else if ((len & 1) == 0)
|
1128 |
|
|
memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
|
1129 |
|
|
else
|
1130 |
|
|
{
|
1131 |
|
|
/* For return values of odd size, the first byte is in the
|
1132 |
|
|
least significant part of the first register. The
|
1133 |
|
|
remaining bytes in remaining registers. Interestingly,
|
1134 |
|
|
when such values are passed in, the last byte is in the
|
1135 |
|
|
most significant byte of that same register - wierd. */
|
1136 |
|
|
memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
|
1137 |
|
|
}
|
1138 |
|
|
}
|
1139 |
|
|
}
|
1140 |
|
|
|
1141 |
|
|
/* Translate a GDB virtual ADDR/LEN into a format the remote target
|
1142 |
|
|
understands. Returns number of bytes that can be transfered
|
1143 |
|
|
starting at TARG_ADDR. Return ZERO if no bytes can be transfered
|
1144 |
|
|
(segmentation fault). Since the simulator knows all about how the
|
1145 |
|
|
VM system works, we just call that to do the translation. */
|
1146 |
|
|
|
1147 |
|
|
static void
|
1148 |
|
|
remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
|
1149 |
|
|
CORE_ADDR *targ_addr, int *targ_len)
|
1150 |
|
|
{
|
1151 |
|
|
long out_addr;
|
1152 |
|
|
long out_len;
|
1153 |
|
|
out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
|
1154 |
|
|
&out_addr,
|
1155 |
|
|
d10v_dmap_register,
|
1156 |
|
|
d10v_imap_register);
|
1157 |
|
|
*targ_addr = out_addr;
|
1158 |
|
|
*targ_len = out_len;
|
1159 |
|
|
}
|
1160 |
|
|
|
1161 |
|
|
|
1162 |
|
|
/* The following code implements access to, and display of, the D10V's
|
1163 |
|
|
instruction trace buffer. The buffer consists of 64K or more
|
1164 |
|
|
4-byte words of data, of which each words includes an 8-bit count,
|
1165 |
|
|
an 8-bit segment number, and a 16-bit instruction address.
|
1166 |
|
|
|
1167 |
|
|
In theory, the trace buffer is continuously capturing instruction
|
1168 |
|
|
data that the CPU presents on its "debug bus", but in practice, the
|
1169 |
|
|
ROMified GDB stub only enables tracing when it continues or steps
|
1170 |
|
|
the program, and stops tracing when the program stops; so it
|
1171 |
|
|
actually works for GDB to read the buffer counter out of memory and
|
1172 |
|
|
then read each trace word. The counter records where the tracing
|
1173 |
|
|
stops, but there is no record of where it started, so we remember
|
1174 |
|
|
the PC when we resumed and then search backwards in the trace
|
1175 |
|
|
buffer for a word that includes that address. This is not perfect,
|
1176 |
|
|
because you will miss trace data if the resumption PC is the target
|
1177 |
|
|
of a branch. (The value of the buffer counter is semi-random, any
|
1178 |
|
|
trace data from a previous program stop is gone.) */
|
1179 |
|
|
|
1180 |
|
|
/* The address of the last word recorded in the trace buffer. */
|
1181 |
|
|
|
1182 |
|
|
#define DBBC_ADDR (0xd80000)
|
1183 |
|
|
|
1184 |
|
|
/* The base of the trace buffer, at least for the "Board_0". */
|
1185 |
|
|
|
1186 |
|
|
#define TRACE_BUFFER_BASE (0xf40000)
|
1187 |
|
|
|
1188 |
|
|
static void trace_command (char *, int);
|
1189 |
|
|
|
1190 |
|
|
static void untrace_command (char *, int);
|
1191 |
|
|
|
1192 |
|
|
static void trace_info (char *, int);
|
1193 |
|
|
|
1194 |
|
|
static void tdisassemble_command (char *, int);
|
1195 |
|
|
|
1196 |
|
|
static void display_trace (int, int);
|
1197 |
|
|
|
1198 |
|
|
/* True when instruction traces are being collected. */
|
1199 |
|
|
|
1200 |
|
|
static int tracing;
|
1201 |
|
|
|
1202 |
|
|
/* Remembered PC. */
|
1203 |
|
|
|
1204 |
|
|
static CORE_ADDR last_pc;
|
1205 |
|
|
|
1206 |
|
|
/* True when trace output should be displayed whenever program stops. */
|
1207 |
|
|
|
1208 |
|
|
static int trace_display;
|
1209 |
|
|
|
1210 |
|
|
/* True when trace listing should include source lines. */
|
1211 |
|
|
|
1212 |
|
|
static int default_trace_show_source = 1;
|
1213 |
|
|
|
1214 |
|
|
struct trace_buffer
|
1215 |
|
|
{
|
1216 |
|
|
int size;
|
1217 |
|
|
short *counts;
|
1218 |
|
|
CORE_ADDR *addrs;
|
1219 |
|
|
}
|
1220 |
|
|
trace_data;
|
1221 |
|
|
|
1222 |
|
|
static void
|
1223 |
|
|
trace_command (char *args, int from_tty)
|
1224 |
|
|
{
|
1225 |
|
|
/* Clear the host-side trace buffer, allocating space if needed. */
|
1226 |
|
|
trace_data.size = 0;
|
1227 |
|
|
if (trace_data.counts == NULL)
|
1228 |
|
|
trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
|
1229 |
|
|
if (trace_data.addrs == NULL)
|
1230 |
|
|
trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
|
1231 |
|
|
|
1232 |
|
|
tracing = 1;
|
1233 |
|
|
|
1234 |
|
|
printf_filtered ("Tracing is now on.\n");
|
1235 |
|
|
}
|
1236 |
|
|
|
1237 |
|
|
static void
|
1238 |
|
|
untrace_command (char *args, int from_tty)
|
1239 |
|
|
{
|
1240 |
|
|
tracing = 0;
|
1241 |
|
|
|
1242 |
|
|
printf_filtered ("Tracing is now off.\n");
|
1243 |
|
|
}
|
1244 |
|
|
|
1245 |
|
|
static void
|
1246 |
|
|
trace_info (char *args, int from_tty)
|
1247 |
|
|
{
|
1248 |
|
|
int i;
|
1249 |
|
|
|
1250 |
|
|
if (trace_data.size)
|
1251 |
|
|
{
|
1252 |
|
|
printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
|
1253 |
|
|
|
1254 |
|
|
for (i = 0; i < trace_data.size; ++i)
|
1255 |
|
|
{
|
1256 |
|
|
printf_filtered ("%d: %d instruction%s at 0x%s\n",
|
1257 |
|
|
i,
|
1258 |
|
|
trace_data.counts[i],
|
1259 |
|
|
(trace_data.counts[i] == 1 ? "" : "s"),
|
1260 |
|
|
paddr_nz (trace_data.addrs[i]));
|
1261 |
|
|
}
|
1262 |
|
|
}
|
1263 |
|
|
else
|
1264 |
|
|
printf_filtered ("No entries in trace buffer.\n");
|
1265 |
|
|
|
1266 |
|
|
printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
|
1267 |
|
|
}
|
1268 |
|
|
|
1269 |
|
|
/* Print the instruction at address MEMADDR in debugged memory,
|
1270 |
|
|
on STREAM. Returns length of the instruction, in bytes. */
|
1271 |
|
|
|
1272 |
|
|
static int
|
1273 |
|
|
print_insn (CORE_ADDR memaddr, struct ui_file *stream)
|
1274 |
|
|
{
|
1275 |
|
|
/* If there's no disassembler, something is very wrong. */
|
1276 |
|
|
if (tm_print_insn == NULL)
|
1277 |
|
|
internal_error (__FILE__, __LINE__,
|
1278 |
|
|
"print_insn: no disassembler");
|
1279 |
|
|
|
1280 |
|
|
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
|
1281 |
|
|
tm_print_insn_info.endian = BFD_ENDIAN_BIG;
|
1282 |
|
|
else
|
1283 |
|
|
tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
|
1284 |
|
|
return (*tm_print_insn) (memaddr, &tm_print_insn_info);
|
1285 |
|
|
}
|
1286 |
|
|
|
1287 |
|
|
static void
|
1288 |
|
|
d10v_eva_prepare_to_trace (void)
|
1289 |
|
|
{
|
1290 |
|
|
if (!tracing)
|
1291 |
|
|
return;
|
1292 |
|
|
|
1293 |
|
|
last_pc = read_register (PC_REGNUM);
|
1294 |
|
|
}
|
1295 |
|
|
|
1296 |
|
|
/* Collect trace data from the target board and format it into a form
|
1297 |
|
|
more useful for display. */
|
1298 |
|
|
|
1299 |
|
|
static void
|
1300 |
|
|
d10v_eva_get_trace_data (void)
|
1301 |
|
|
{
|
1302 |
|
|
int count, i, j, oldsize;
|
1303 |
|
|
int trace_addr, trace_seg, trace_cnt, next_cnt;
|
1304 |
|
|
unsigned int last_trace, trace_word, next_word;
|
1305 |
|
|
unsigned int *tmpspace;
|
1306 |
|
|
|
1307 |
|
|
if (!tracing)
|
1308 |
|
|
return;
|
1309 |
|
|
|
1310 |
|
|
tmpspace = xmalloc (65536 * sizeof (unsigned int));
|
1311 |
|
|
|
1312 |
|
|
last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
|
1313 |
|
|
|
1314 |
|
|
/* Collect buffer contents from the target, stopping when we reach
|
1315 |
|
|
the word recorded when execution resumed. */
|
1316 |
|
|
|
1317 |
|
|
count = 0;
|
1318 |
|
|
while (last_trace > 0)
|
1319 |
|
|
{
|
1320 |
|
|
QUIT;
|
1321 |
|
|
trace_word =
|
1322 |
|
|
read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
|
1323 |
|
|
trace_addr = trace_word & 0xffff;
|
1324 |
|
|
last_trace -= 4;
|
1325 |
|
|
/* Ignore an apparently nonsensical entry. */
|
1326 |
|
|
if (trace_addr == 0xffd5)
|
1327 |
|
|
continue;
|
1328 |
|
|
tmpspace[count++] = trace_word;
|
1329 |
|
|
if (trace_addr == last_pc)
|
1330 |
|
|
break;
|
1331 |
|
|
if (count > 65535)
|
1332 |
|
|
break;
|
1333 |
|
|
}
|
1334 |
|
|
|
1335 |
|
|
/* Move the data to the host-side trace buffer, adjusting counts to
|
1336 |
|
|
include the last instruction executed and transforming the address
|
1337 |
|
|
into something that GDB likes. */
|
1338 |
|
|
|
1339 |
|
|
for (i = 0; i < count; ++i)
|
1340 |
|
|
{
|
1341 |
|
|
trace_word = tmpspace[i];
|
1342 |
|
|
next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
|
1343 |
|
|
trace_addr = trace_word & 0xffff;
|
1344 |
|
|
next_cnt = (next_word >> 24) & 0xff;
|
1345 |
|
|
j = trace_data.size + count - i - 1;
|
1346 |
|
|
trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
|
1347 |
|
|
trace_data.counts[j] = next_cnt + 1;
|
1348 |
|
|
}
|
1349 |
|
|
|
1350 |
|
|
oldsize = trace_data.size;
|
1351 |
|
|
trace_data.size += count;
|
1352 |
|
|
|
1353 |
|
|
xfree (tmpspace);
|
1354 |
|
|
|
1355 |
|
|
if (trace_display)
|
1356 |
|
|
display_trace (oldsize, trace_data.size);
|
1357 |
|
|
}
|
1358 |
|
|
|
1359 |
|
|
static void
|
1360 |
|
|
tdisassemble_command (char *arg, int from_tty)
|
1361 |
|
|
{
|
1362 |
|
|
int i, count;
|
1363 |
|
|
CORE_ADDR low, high;
|
1364 |
|
|
char *space_index;
|
1365 |
|
|
|
1366 |
|
|
if (!arg)
|
1367 |
|
|
{
|
1368 |
|
|
low = 0;
|
1369 |
|
|
high = trace_data.size;
|
1370 |
|
|
}
|
1371 |
|
|
else if (!(space_index = (char *) strchr (arg, ' ')))
|
1372 |
|
|
{
|
1373 |
|
|
low = parse_and_eval_address (arg);
|
1374 |
|
|
high = low + 5;
|
1375 |
|
|
}
|
1376 |
|
|
else
|
1377 |
|
|
{
|
1378 |
|
|
/* Two arguments. */
|
1379 |
|
|
*space_index = '\0';
|
1380 |
|
|
low = parse_and_eval_address (arg);
|
1381 |
|
|
high = parse_and_eval_address (space_index + 1);
|
1382 |
|
|
if (high < low)
|
1383 |
|
|
high = low;
|
1384 |
|
|
}
|
1385 |
|
|
|
1386 |
|
|
printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
|
1387 |
|
|
|
1388 |
|
|
display_trace (low, high);
|
1389 |
|
|
|
1390 |
|
|
printf_filtered ("End of trace dump.\n");
|
1391 |
|
|
gdb_flush (gdb_stdout);
|
1392 |
|
|
}
|
1393 |
|
|
|
1394 |
|
|
static void
|
1395 |
|
|
display_trace (int low, int high)
|
1396 |
|
|
{
|
1397 |
|
|
int i, count, trace_show_source, first, suppress;
|
1398 |
|
|
CORE_ADDR next_address;
|
1399 |
|
|
|
1400 |
|
|
trace_show_source = default_trace_show_source;
|
1401 |
|
|
if (!have_full_symbols () && !have_partial_symbols ())
|
1402 |
|
|
{
|
1403 |
|
|
trace_show_source = 0;
|
1404 |
|
|
printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
|
1405 |
|
|
printf_filtered ("Trace will not display any source.\n");
|
1406 |
|
|
}
|
1407 |
|
|
|
1408 |
|
|
first = 1;
|
1409 |
|
|
suppress = 0;
|
1410 |
|
|
for (i = low; i < high; ++i)
|
1411 |
|
|
{
|
1412 |
|
|
next_address = trace_data.addrs[i];
|
1413 |
|
|
count = trace_data.counts[i];
|
1414 |
|
|
while (count-- > 0)
|
1415 |
|
|
{
|
1416 |
|
|
QUIT;
|
1417 |
|
|
if (trace_show_source)
|
1418 |
|
|
{
|
1419 |
|
|
struct symtab_and_line sal, sal_prev;
|
1420 |
|
|
|
1421 |
|
|
sal_prev = find_pc_line (next_address - 4, 0);
|
1422 |
|
|
sal = find_pc_line (next_address, 0);
|
1423 |
|
|
|
1424 |
|
|
if (sal.symtab)
|
1425 |
|
|
{
|
1426 |
|
|
if (first || sal.line != sal_prev.line)
|
1427 |
|
|
print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
|
1428 |
|
|
suppress = 0;
|
1429 |
|
|
}
|
1430 |
|
|
else
|
1431 |
|
|
{
|
1432 |
|
|
if (!suppress)
|
1433 |
|
|
/* FIXME-32x64--assumes sal.pc fits in long. */
|
1434 |
|
|
printf_filtered ("No source file for address %s.\n",
|
1435 |
|
|
local_hex_string ((unsigned long) sal.pc));
|
1436 |
|
|
suppress = 1;
|
1437 |
|
|
}
|
1438 |
|
|
}
|
1439 |
|
|
first = 0;
|
1440 |
|
|
print_address (next_address, gdb_stdout);
|
1441 |
|
|
printf_filtered (":");
|
1442 |
|
|
printf_filtered ("\t");
|
1443 |
|
|
wrap_here (" ");
|
1444 |
|
|
next_address = next_address + print_insn (next_address, gdb_stdout);
|
1445 |
|
|
printf_filtered ("\n");
|
1446 |
|
|
gdb_flush (gdb_stdout);
|
1447 |
|
|
}
|
1448 |
|
|
}
|
1449 |
|
|
}
|
1450 |
|
|
|
1451 |
|
|
|
1452 |
|
|
static gdbarch_init_ftype d10v_gdbarch_init;
|
1453 |
|
|
|
1454 |
|
|
static struct gdbarch *
|
1455 |
|
|
d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
1456 |
|
|
{
|
1457 |
|
|
static LONGEST d10v_call_dummy_words[] =
|
1458 |
|
|
{0};
|
1459 |
|
|
struct gdbarch *gdbarch;
|
1460 |
|
|
int d10v_num_regs;
|
1461 |
|
|
struct gdbarch_tdep *tdep;
|
1462 |
|
|
gdbarch_register_name_ftype *d10v_register_name;
|
1463 |
|
|
gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
|
1464 |
|
|
|
1465 |
|
|
/* Find a candidate among the list of pre-declared architectures. */
|
1466 |
|
|
arches = gdbarch_list_lookup_by_info (arches, &info);
|
1467 |
|
|
if (arches != NULL)
|
1468 |
|
|
return arches->gdbarch;
|
1469 |
|
|
|
1470 |
|
|
/* None found, create a new architecture from the information
|
1471 |
|
|
provided. */
|
1472 |
|
|
tdep = XMALLOC (struct gdbarch_tdep);
|
1473 |
|
|
gdbarch = gdbarch_alloc (&info, tdep);
|
1474 |
|
|
|
1475 |
|
|
switch (info.bfd_arch_info->mach)
|
1476 |
|
|
{
|
1477 |
|
|
case bfd_mach_d10v_ts2:
|
1478 |
|
|
d10v_num_regs = 37;
|
1479 |
|
|
d10v_register_name = d10v_ts2_register_name;
|
1480 |
|
|
d10v_register_sim_regno = d10v_ts2_register_sim_regno;
|
1481 |
|
|
tdep->a0_regnum = TS2_A0_REGNUM;
|
1482 |
|
|
tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
|
1483 |
|
|
tdep->dmap_register = d10v_ts2_dmap_register;
|
1484 |
|
|
tdep->imap_register = d10v_ts2_imap_register;
|
1485 |
|
|
break;
|
1486 |
|
|
default:
|
1487 |
|
|
case bfd_mach_d10v_ts3:
|
1488 |
|
|
d10v_num_regs = 42;
|
1489 |
|
|
d10v_register_name = d10v_ts3_register_name;
|
1490 |
|
|
d10v_register_sim_regno = d10v_ts3_register_sim_regno;
|
1491 |
|
|
tdep->a0_regnum = TS3_A0_REGNUM;
|
1492 |
|
|
tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
|
1493 |
|
|
tdep->dmap_register = d10v_ts3_dmap_register;
|
1494 |
|
|
tdep->imap_register = d10v_ts3_imap_register;
|
1495 |
|
|
break;
|
1496 |
|
|
}
|
1497 |
|
|
|
1498 |
|
|
set_gdbarch_read_pc (gdbarch, d10v_read_pc);
|
1499 |
|
|
set_gdbarch_write_pc (gdbarch, d10v_write_pc);
|
1500 |
|
|
set_gdbarch_read_fp (gdbarch, d10v_read_fp);
|
1501 |
|
|
set_gdbarch_write_fp (gdbarch, d10v_write_fp);
|
1502 |
|
|
set_gdbarch_read_sp (gdbarch, d10v_read_sp);
|
1503 |
|
|
set_gdbarch_write_sp (gdbarch, d10v_write_sp);
|
1504 |
|
|
|
1505 |
|
|
set_gdbarch_num_regs (gdbarch, d10v_num_regs);
|
1506 |
|
|
set_gdbarch_sp_regnum (gdbarch, 15);
|
1507 |
|
|
set_gdbarch_fp_regnum (gdbarch, 11);
|
1508 |
|
|
set_gdbarch_pc_regnum (gdbarch, 18);
|
1509 |
|
|
set_gdbarch_register_name (gdbarch, d10v_register_name);
|
1510 |
|
|
set_gdbarch_register_size (gdbarch, 2);
|
1511 |
|
|
set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
|
1512 |
|
|
set_gdbarch_register_byte (gdbarch, d10v_register_byte);
|
1513 |
|
|
set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
|
1514 |
|
|
set_gdbarch_max_register_raw_size (gdbarch, 8);
|
1515 |
|
|
set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size);
|
1516 |
|
|
set_gdbarch_max_register_virtual_size (gdbarch, 8);
|
1517 |
|
|
set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
|
1518 |
|
|
|
1519 |
|
|
set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
1520 |
|
|
set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
|
1521 |
|
|
set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
|
1522 |
|
|
set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
1523 |
|
|
set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
1524 |
|
|
/* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
|
1525 |
|
|
double'' is 64 bits. */
|
1526 |
|
|
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
1527 |
|
|
set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
1528 |
|
|
set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
|
1529 |
|
|
switch (info.byte_order)
|
1530 |
|
|
{
|
1531 |
|
|
case BIG_ENDIAN:
|
1532 |
|
|
set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
|
1533 |
|
|
set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big);
|
1534 |
|
|
set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
|
1535 |
|
|
break;
|
1536 |
|
|
case LITTLE_ENDIAN:
|
1537 |
|
|
set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
|
1538 |
|
|
set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
|
1539 |
|
|
set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
|
1540 |
|
|
break;
|
1541 |
|
|
default:
|
1542 |
|
|
internal_error (__FILE__, __LINE__,
|
1543 |
|
|
"d10v_gdbarch_init: bad byte order for float format");
|
1544 |
|
|
}
|
1545 |
|
|
|
1546 |
|
|
set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
|
1547 |
|
|
set_gdbarch_call_dummy_length (gdbarch, 0);
|
1548 |
|
|
set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
|
1549 |
|
|
set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
|
1550 |
|
|
set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
|
1551 |
|
|
set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
|
1552 |
|
|
set_gdbarch_call_dummy_start_offset (gdbarch, 0);
|
1553 |
|
|
set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
|
1554 |
|
|
set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
|
1555 |
|
|
set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
|
1556 |
|
|
set_gdbarch_call_dummy_p (gdbarch, 1);
|
1557 |
|
|
set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
|
1558 |
|
|
set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
|
1559 |
|
|
set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
|
1560 |
|
|
|
1561 |
|
|
set_gdbarch_register_convertible (gdbarch, d10v_register_convertible);
|
1562 |
|
|
set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual);
|
1563 |
|
|
set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw);
|
1564 |
|
|
|
1565 |
|
|
set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
|
1566 |
|
|
set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
|
1567 |
|
|
set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
|
1568 |
|
|
set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
|
1569 |
|
|
|
1570 |
|
|
set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr);
|
1571 |
|
|
set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr);
|
1572 |
|
|
set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p);
|
1573 |
|
|
set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p);
|
1574 |
|
|
set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw);
|
1575 |
|
|
set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw);
|
1576 |
|
|
|
1577 |
|
|
set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
|
1578 |
|
|
set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
|
1579 |
|
|
set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
|
1580 |
|
|
set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
|
1581 |
|
|
|
1582 |
|
|
set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
|
1583 |
|
|
set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
|
1584 |
|
|
|
1585 |
|
|
set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
|
1586 |
|
|
|
1587 |
|
|
set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
|
1588 |
|
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
1589 |
|
|
set_gdbarch_decr_pc_after_break (gdbarch, 4);
|
1590 |
|
|
set_gdbarch_function_start_offset (gdbarch, 0);
|
1591 |
|
|
set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
|
1592 |
|
|
|
1593 |
|
|
set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
|
1594 |
|
|
|
1595 |
|
|
set_gdbarch_frame_args_skip (gdbarch, 0);
|
1596 |
|
|
set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
|
1597 |
|
|
set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
|
1598 |
|
|
set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
|
1599 |
|
|
set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
|
1600 |
|
|
set_gdbarch_frame_args_address (gdbarch, default_frame_address);
|
1601 |
|
|
set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
|
1602 |
|
|
set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
|
1603 |
|
|
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
|
1604 |
|
|
set_gdbarch_stack_align (gdbarch, d10v_stack_align);
|
1605 |
|
|
|
1606 |
|
|
set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno);
|
1607 |
|
|
set_gdbarch_extra_stack_alignment_needed (gdbarch, 0);
|
1608 |
|
|
|
1609 |
|
|
return gdbarch;
|
1610 |
|
|
}
|
1611 |
|
|
|
1612 |
|
|
|
1613 |
|
|
extern void (*target_resume_hook) (void);
|
1614 |
|
|
extern void (*target_wait_loop_hook) (void);
|
1615 |
|
|
|
1616 |
|
|
void
|
1617 |
|
|
_initialize_d10v_tdep (void)
|
1618 |
|
|
{
|
1619 |
|
|
register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
|
1620 |
|
|
|
1621 |
|
|
tm_print_insn = print_insn_d10v;
|
1622 |
|
|
|
1623 |
|
|
target_resume_hook = d10v_eva_prepare_to_trace;
|
1624 |
|
|
target_wait_loop_hook = d10v_eva_get_trace_data;
|
1625 |
|
|
|
1626 |
|
|
add_com ("regs", class_vars, show_regs, "Print all registers");
|
1627 |
|
|
|
1628 |
|
|
add_com ("itrace", class_support, trace_command,
|
1629 |
|
|
"Enable tracing of instruction execution.");
|
1630 |
|
|
|
1631 |
|
|
add_com ("iuntrace", class_support, untrace_command,
|
1632 |
|
|
"Disable tracing of instruction execution.");
|
1633 |
|
|
|
1634 |
|
|
add_com ("itdisassemble", class_vars, tdisassemble_command,
|
1635 |
|
|
"Disassemble the trace buffer.\n\
|
1636 |
|
|
Two optional arguments specify a range of trace buffer entries\n\
|
1637 |
|
|
as reported by info trace (NOT addresses!).");
|
1638 |
|
|
|
1639 |
|
|
add_info ("itrace", trace_info,
|
1640 |
|
|
"Display info about the trace data buffer.");
|
1641 |
|
|
|
1642 |
|
|
add_show_from_set (add_set_cmd ("itracedisplay", no_class,
|
1643 |
|
|
var_integer, (char *) &trace_display,
|
1644 |
|
|
"Set automatic display of trace.\n", &setlist),
|
1645 |
|
|
&showlist);
|
1646 |
|
|
add_show_from_set (add_set_cmd ("itracesource", no_class,
|
1647 |
|
|
var_integer, (char *) &default_trace_show_source,
|
1648 |
|
|
"Set display of source code with trace.\n", &setlist),
|
1649 |
|
|
&showlist);
|
1650 |
|
|
|
1651 |
|
|
}
|