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1 578 markom
/* Intel x86 (a.k.a. ia32) native-dependent code.
2
   Copyright (C) 2001 Free Software Foundation, Inc.
3
 
4
   This file is part of GDB.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 59 Temple Place - Suite 330,
19
   Boston, MA 02111-1307, USA.  */
20
 
21
#include "defs.h"
22
#include "breakpoint.h"
23
#include "command.h"
24
#include "gdbcmd.h"
25
 
26
/* Support for hardware watchpoints and breakpoints using the x86
27
   debug registers.
28
 
29
   This provides several functions for inserting and removing
30
   hardware-assisted breakpoints and watchpoints, testing if
31
   one or more of the watchpoints triggered and at what address,
32
   checking whether a given region can be watched, etc.
33
 
34
   A target which wants to use these functions should define
35
   several macros, such as `target_insert_watchpoint' and
36
   `target_stopped_data_address', listed in target.h, to call
37
   the appropriate functions below.  It should also define
38
   I386_USE_GENERIC_WATCHPOINTS in its tm.h file.
39
 
40
   In addition, each target should provide several low-level
41
   macros that will be called to insert watchpoints and hardware
42
   breakpoints into the inferior, remove them, and check their
43
   status.  These macros are:
44
 
45
      I386_DR_LOW_SET_CONTROL  -- set the debug control (DR7)
46
                                  register to a given value
47
 
48
      I386_DR_LOW_SET_ADDR     -- put an address into one debug
49
                                  register
50
 
51
      I386_DR_LOW_RESET_ADDR   -- reset the address stored in
52
                                  one debug register
53
 
54
      I386_DR_LOW_GET_STATUS   -- return the value of the debug
55
                                  status (DR6) register.
56
 
57
   The functions below implement debug registers sharing by
58
   reference counts, and allow to watch regions up to 16 bytes
59
   long.  */
60
 
61
#ifdef I386_USE_GENERIC_WATCHPOINTS
62
 
63
/* Debug registers' indices.  */
64
#define DR_NADDR                4  /* the number of debug address registers */
65
#define DR_STATUS               6  /* index of debug status register (DR6) */
66
#define DR_CONTROL              7  /* index of debug control register (DR7) */
67
 
68
/* DR7 Debug Control register fields.  */
69
 
70
/* How many bits to skip in DR7 to get to R/W and LEN fields.  */
71
#define DR_CONTROL_SHIFT        16
72
/* How many bits in DR7 per R/W and LEN field for each watchpoint.  */
73
#define DR_CONTROL_SIZE         4
74
 
75
/* Watchpoint/breakpoint read/write fields in DR7.  */
76
#define DR_RW_EXECUTE           (0x0) /* break on instruction execution */
77
#define DR_RW_WRITE             (0x1) /* break on data writes */
78
#define DR_RW_READ              (0x3) /* break on data reads or writes */
79
 
80
/* This is here for completeness.  No platform supports this
81
   functionality yet (as of Mar-2001).  Note that the DE flag in the
82
   CR4 register needs to be set to support this.  */
83
#ifndef DR_RW_IORW
84
#define DR_RW_IORW              (0x2) /* break on I/O reads or writes */
85
#endif
86
 
87
/* Watchpoint/breakpoint length fields in DR7.  The 2-bit left shift
88
   is so we could OR this with the read/write field defined above.  */
89
#define DR_LEN_1                (0x0 << 2) /* 1-byte region watch or breakpt */
90
#define DR_LEN_2                (0x1 << 2) /* 2-byte region watch */
91
#define DR_LEN_4                (0x3 << 2) /* 4-byte region watch */
92
 
93
/* Local and Global Enable flags in DR7.
94
 
95
   When the Local Enable flag is set, the breakpoint/watchpoint is
96
   enabled only for the current task; the processor automatically
97
   clears this flag on every task switch.  When the Global Enable
98
   flag is set, the breakpoint/watchpoint is enabled for all tasks;
99
   the processor never clears this flag.
100
 
101
   Currently, all watchpoint are locally enabled.  If you need to
102
   enable them globally, read the comment which pertains to this in
103
   i386_insert_aligned_watchpoint below.  */
104
#define DR_LOCAL_ENABLE_SHIFT   0   /* extra shift to the local enable bit */
105
#define DR_GLOBAL_ENABLE_SHIFT  1   /* extra shift to the global enable bit */
106
#define DR_ENABLE_SIZE          2   /* 2 enable bits per debug register */
107
 
108
/* Local and global exact breakpoint enable flags (a.k.a. slowdown
109
   flags).  These are only required on i386, to allow detection of the
110
   exact instruction which caused a watchpoint to break; i486 and
111
   later processors do that automatically.  We set these flags for
112
   back compatibility.  */
113
#define DR_LOCAL_SLOWDOWN       (0x100)
114
#define DR_GLOBAL_SLOWDOWN      (0x200)
115
 
116
/* Fields reserved by Intel.  This includes the GD (General Detect
117
   Enable) flag, which causes a debug exception to be generated when a
118
   MOV instruction accesses one of the debug registers.
119
 
120
   FIXME: My Intel manual says we should use 0xF800, not 0xFC00.  */
121
#define DR_CONTROL_RESERVED     (0xFC00)
122
 
123
/* Auxiliary helper macros.  */
124
 
125
/* A value that masks all fields in DR7 that are reserved by Intel.  */
126
#define I386_DR_CONTROL_MASK            (~DR_CONTROL_RESERVED)
127
 
128
/* The I'th debug register is vacant if its Local and Global Enable
129
   bits are reset in the Debug Control register.  */
130
#define I386_DR_VACANT(i) \
131
  ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
132
 
133
/* Locally enable the break/watchpoint in the I'th debug register.  */
134
#define I386_DR_LOCAL_ENABLE(i) \
135
  dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
136
 
137
/* Globally enable the break/watchpoint in the I'th debug register.  */
138
#define I386_DR_GLOBAL_ENABLE(i) \
139
  dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
140
 
141
/* Disable the break/watchpoint in the I'th debug register.  */
142
#define I386_DR_DISABLE(i) \
143
  dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
144
 
145
/* Set in DR7 the RW and LEN fields for the I'th debug register.  */
146
#define I386_DR_SET_RW_LEN(i,rwlen) \
147
  do { \
148
    dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i)));   \
149
    dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
150
  } while (0)
151
 
152
/* Get from DR7 the RW and LEN fields for the I'th debug register.  */
153
#define I386_DR_GET_RW_LEN(i) \
154
  ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
155
 
156
/* Did the watchpoint whose address is in the I'th register break?  */
157
#define I386_DR_WATCH_HIT(i)    (dr_status_mirror & (1 << (i)))
158
 
159
/* A macro to loop over all debug registers.  */
160
#define ALL_DEBUG_REGISTERS(i)  for (i = 0; i < DR_NADDR; i++)
161
 
162
/* Mirror the inferior's DRi registers.  We keep the status and
163
   control registers separated because they don't hold addresses.  */
164
static CORE_ADDR dr_mirror[DR_NADDR];
165
static unsigned  dr_status_mirror, dr_control_mirror;
166
 
167
/* Reference counts for each debug register.  */
168
static int       dr_ref_count[DR_NADDR];
169
 
170
/* Whether or not to print the mirrored debug registers.  */
171
static int       maint_show_dr;
172
 
173
/* Types of operations supported by i386_handle_nonaligned_watchpoint.  */
174
typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
175
 
176
/* Internal functions.  */
177
 
178
/* Return the value of a 4-bit field for DR7 suitable for watching a
179
   region of LEN bytes for accesses of type TYPE.  LEN is assumed
180
   to have the value of 1, 2, or 4.  */
181
static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
182
 
183
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
184
   according to the length of the region to watch.  LEN_RW_BITS is the
185
   value of the bit-field from DR7 which describes the length and
186
   access type of the region to be watched by this watchpoint.  Return
187
 
188
static int i386_insert_aligned_watchpoint (CORE_ADDR addr,
189
                                           unsigned len_rw_bits);
190
 
191
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
192
   according to the length of the region to watch.  LEN_RW_BITS is the
193
   value of the bits from DR7 which describes the length and access
194
   type of the region watched by this watchpoint.  Return 0 on
195
   success, -1 on failure.  */
196
static int i386_remove_aligned_watchpoint (CORE_ADDR addr,
197
                                           unsigned len_rw_bits);
198
 
199
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
200
   number of debug registers required to watch a region at address
201
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
202
   successful insertion or removal, a positive number when queried
203
   about the number of registers, or -1 on failure.  If WHAT is not
204
   a valid value, bombs through internal_error.  */
205
static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what,
206
                                              CORE_ADDR addr, int len,
207
                                              enum target_hw_bp_type type);
208
 
209
/* Implementation.  */
210
 
211
/* Clear the reference counts and forget everything we knew about
212
   the debug registers.  */
213
void
214
i386_cleanup_dregs (void)
215
{
216
  int i;
217
 
218
  ALL_DEBUG_REGISTERS(i)
219
    {
220
      dr_mirror[i] = 0;
221
      dr_ref_count[i] = 0;
222
    }
223
  dr_control_mirror = 0;
224
  dr_status_mirror  = 0;
225
}
226
 
227
/* Print the values of the mirrored debug registers.
228
   This is called when maint_show_dr is non-zero.  To set that
229
   up, type "maint show-debug-regs" at GDB's prompt.  */
230
static void
231
i386_show_dr (const char *func, CORE_ADDR addr,
232
              int len, enum target_hw_bp_type type)
233
{
234
  int i;
235
 
236
  puts_unfiltered (func);
237
  if (addr || len)
238
    printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
239
                       /* This code is for ia32, so casting CORE_ADDR
240
                          to unsigned long should be okay.  */
241
                       (unsigned long)addr, len,
242
                       type == hw_write ? "data-write"
243
                       : (type == hw_read ? "data-read"
244
                          : (type == hw_access ? "data-read/write"
245
                             : (type == hw_execute ? "instruction-execute"
246
                                /* FIXME: if/when I/O read/write
247
                                   watchpoints are supported, add them
248
                                   here.  */
249
                                : "??unknown??"))));
250
  puts_unfiltered (":\n");
251
  printf_unfiltered ("\tCONTROL (DR7): %08x          STATUS (DR6): %08x\n",
252
                     dr_control_mirror, dr_status_mirror);
253
  ALL_DEBUG_REGISTERS(i)
254
    {
255
      printf_unfiltered ("\tDR%d: addr=%08lx, ref.count=%d  DR%d: addr=%08lx, ref.count=%d\n",
256
                         i, dr_mirror[i], dr_ref_count[i],
257
                         i+1, dr_mirror[i+1], dr_ref_count[i+1]);
258
      i++;
259
    }
260
}
261
 
262
/* Return the value of a 4-bit field for DR7 suitable for watching a
263
   region of LEN bytes for accesses of type TYPE.  LEN is assumed
264
   to have the value of 1, 2, or 4.  */
265
static unsigned
266
i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
267
{
268
  unsigned rw;
269
 
270
  switch (type)
271
    {
272
      case hw_execute:
273
        rw = DR_RW_EXECUTE;
274
        break;
275
      case hw_write:
276
        rw = DR_RW_WRITE;
277
        break;
278
      case hw_read:      /* x86 doesn't support data-read watchpoints */
279
      case hw_access:
280
        rw = DR_RW_READ;
281
        break;
282
#if 0
283
      case hw_io_access: /* not yet supported */
284
        rw = DR_RW_IORW;
285
        break;
286
#endif
287
      default:
288
        internal_error (__FILE__, __LINE__, "\
289
Invalid hw breakpoint type %d in i386_length_and_rw_bits.\n", (int)type);
290
    }
291
 
292
  switch (len)
293
    {
294
      case 4:
295
        return (DR_LEN_4 | rw);
296
      case 2:
297
        return (DR_LEN_2 | rw);
298
      case 1:
299
        return (DR_LEN_1 | rw);
300
      default:
301
        internal_error (__FILE__, __LINE__, "\
302
Invalid hw breakpoint length %d in i386_length_and_rw_bits.\n", len);
303
    }
304
}
305
 
306
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
307
   according to the length of the region to watch.  LEN_RW_BITS is the
308
   value of the bits from DR7 which describes the length and access
309
   type of the region to be watched by this watchpoint.  Return 0 on
310
   success, -1 on failure.  */
311
static int
312
i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
313
{
314
  int i;
315
 
316
  /* First, look for an occupied debug register with the same address
317
     and the same RW and LEN definitions.  If we find one, we can
318
     reuse it for this watchpoint as well (and save a register).  */
319
  ALL_DEBUG_REGISTERS(i)
320
    {
321
      if (!I386_DR_VACANT (i)
322
          && dr_mirror[i] == addr
323
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
324
        {
325
          dr_ref_count[i]++;
326
          return 0;
327
        }
328
    }
329
 
330
  /* Next, look for a vacant debug register.  */
331
  ALL_DEBUG_REGISTERS(i)
332
    {
333
      if (I386_DR_VACANT (i))
334
        break;
335
    }
336
 
337
  /* No more debug registers!  */
338
  if (i >= DR_NADDR)
339
    return -1;
340
 
341
  /* Now set up the register I to watch our region.  */
342
 
343
  /* Record the info in our local mirrored array.  */
344
  dr_mirror[i] = addr;
345
  dr_ref_count[i] = 1;
346
  I386_DR_SET_RW_LEN (i, len_rw_bits);
347
  /* Note: we only enable the watchpoint locally, i.e. in the current
348
     task.  Currently, no x86 target allows or supports global
349
     watchpoints; however, if any target would want that in the
350
     future, GDB should probably provide a command to control whether
351
     to enable watchpoints globally or locally, and the code below
352
     should use global or local enable and slow-down flags as
353
     appropriate.  */
354
  I386_DR_LOCAL_ENABLE (i);
355
  dr_control_mirror |= DR_LOCAL_SLOWDOWN;
356
  dr_control_mirror &= I386_DR_CONTROL_MASK;
357
 
358
  /* Finally, actually pass the info to the inferior.  */
359
  I386_DR_LOW_SET_ADDR (i, addr);
360
  I386_DR_LOW_SET_CONTROL (dr_control_mirror);
361
 
362
  return 0;
363
}
364
 
365
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
366
   according to the length of the region to watch.  LEN_RW_BITS is the
367
   value of the bits from DR7 which describes the length and access
368
   type of the region watched by this watchpoint.  Return 0 on
369
   success, -1 on failure.  */
370
static int
371
i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
372
{
373
  int i, retval = -1;
374
 
375
  ALL_DEBUG_REGISTERS(i)
376
    {
377
      if (!I386_DR_VACANT (i)
378
          && dr_mirror[i] == addr
379
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
380
        {
381
          if (--dr_ref_count[i] == 0) /* no longer in use? */
382
            {
383
              /* Reset our mirror.  */
384
              dr_mirror[i] = 0;
385
              I386_DR_DISABLE (i);
386
              /* Reset it in the inferior.  */
387
              I386_DR_LOW_SET_CONTROL (dr_control_mirror);
388
              I386_DR_LOW_RESET_ADDR (i);
389
            }
390
          retval = 0;
391
        }
392
    }
393
 
394
  return retval;
395
}
396
 
397
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
398
   number of debug registers required to watch a region at address
399
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
400
   successful insertion or removal, a positive number when queried
401
   about the number of registers, or -1 on failure.  If WHAT is not
402
   a valid value, bombs through internal_error.  */
403
static int
404
i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len,
405
                                   enum target_hw_bp_type type)
406
{
407
  int align;
408
  int size;
409
  int rv = 0, status = 0;
410
 
411
  static int size_try_array[4][4] =
412
  {
413
    { 1, 1, 1, 1 },             /* trying size one */
414
    { 2, 1, 2, 1 },             /* trying size two */
415
    { 2, 1, 2, 1 },             /* trying size three */
416
    { 4, 1, 2, 1 }              /* trying size four */
417
  };
418
 
419
  while (len > 0)
420
    {
421
      align = addr % 4;
422
      /* Four is the maximum length an x86 debug register can watch.  */
423
      size = size_try_array[len > 4 ? 3 : len - 1][align];
424
      if (what == WP_COUNT)
425
        /* size_try_array[] is defined so that each iteration through
426
           the loop is guaranteed to produce an address and a size
427
           that can be watched with a single debug register.  Thus,
428
           for counting the registers required to watch a region, we
429
           simply need to increment the count on each iteration.  */
430
        rv++;
431
      else
432
        {
433
          unsigned len_rw = i386_length_and_rw_bits (size, type);
434
 
435
          if (what == WP_INSERT)
436
            status = i386_insert_aligned_watchpoint (addr, len_rw);
437
          else if (what == WP_REMOVE)
438
            status = i386_remove_aligned_watchpoint (addr, len_rw);
439
          else
440
            internal_error (__FILE__, __LINE__, "\
441
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
442
                            (int)what);
443
          /* We keep the loop going even after a failure, because some
444
             of the other aligned watchpoints might still succeed
445
             (e.g. if they watch addresses that are already watched,
446
             in which case we just increment the reference counts of
447
             occupied debug registers).  If we break out of the loop
448
             too early, we could cause those addresses watched by
449
             other watchpoints to be disabled when breakpoint.c reacts
450
             to our failure to insert this watchpoint and tries to
451
             remove it.  */
452
          if (status)
453
            rv = status;
454
        }
455
      addr += size;
456
      len -= size;
457
    }
458
  return rv;
459
}
460
 
461
/* Insert a watchpoint to watch a memory region which starts at
462
   address ADDR and whose length is LEN bytes.  Watch memory accesses
463
   of the type TYPE.  Return 0 on success, -1 on failure.  */
464
int
465
i386_insert_watchpoint (CORE_ADDR addr, int len, int type)
466
{
467
  int retval;
468
 
469
  if (len == 3 || len > 4 || addr % len != 0)
470
    retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type);
471
  else
472
    {
473
      unsigned len_rw = i386_length_and_rw_bits (len, type);
474
 
475
      retval = i386_insert_aligned_watchpoint (addr, len_rw);
476
    }
477
 
478
  if (maint_show_dr)
479
    i386_show_dr ("insert_watchpoint", addr, len, type);
480
 
481
  return retval;
482
}
483
 
484
/* Remove a watchpoint that watched the memory region which starts at
485
   address ADDR, whose length is LEN bytes, and for accesses of the
486
   type TYPE.  Return 0 on success, -1 on failure.  */
487
int
488
i386_remove_watchpoint (CORE_ADDR addr, int len, int type)
489
{
490
  int retval;
491
 
492
  if (len == 3 || len > 4 || addr % len != 0)
493
    retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type);
494
  else
495
    {
496
      unsigned len_rw = i386_length_and_rw_bits (len, type);
497
 
498
      retval = i386_remove_aligned_watchpoint (addr, len_rw);
499
    }
500
 
501
  if (maint_show_dr)
502
    i386_show_dr ("remove_watchpoint", addr, len, type);
503
 
504
  return retval;
505
}
506
 
507
/* Return non-zero if we can watch a memory region that starts at
508
   address ADDR and whose length is LEN bytes.  */
509
int
510
i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
511
{
512
  /* Compute how many aligned watchpoints we would need to cover this
513
     region.  */
514
  int nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len,
515
                                                 hw_write);
516
 
517
  return nregs <= DR_NADDR ? 1 : 0;
518
}
519
 
520
/* If the inferior has some watchpoint that triggered, return the
521
   address associated with that watchpoint.  Otherwise, return
522
   zero.  */
523
CORE_ADDR
524
i386_stopped_data_address (void)
525
{
526
  int i;
527
  CORE_ADDR ret = 0;
528
 
529
  dr_status_mirror = I386_DR_LOW_GET_STATUS ();
530
 
531
  ALL_DEBUG_REGISTERS(i)
532
    {
533
      if (I386_DR_WATCH_HIT (i)
534
          /* This second condition makes sure DRi is set up for a data
535
             watchpoint, not a hardware breakpoint.  The reason is
536
             that GDB doesn't call the target_stopped_data_address
537
             method except for data watchpoints.  In other words, I'm
538
             being paranoiac.  */
539
          && I386_DR_GET_RW_LEN (i) != 0)
540
        {
541
          ret = dr_mirror[i];
542
          if (maint_show_dr)
543
            i386_show_dr ("watchpoint_hit", ret, -1, hw_write);
544
        }
545
    }
546
  if (maint_show_dr && ret == 0)
547
    i386_show_dr ("stopped_data_addr", 0, 0, hw_write);
548
 
549
  return ret;
550
}
551
 
552
/* Return non-zero if the inferior has some break/watchpoint that
553
   triggered.  */
554
int
555
i386_stopped_by_hwbp (void)
556
{
557
  int i;
558
 
559
  dr_status_mirror = I386_DR_LOW_GET_STATUS ();
560
  if (maint_show_dr)
561
    i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute);
562
 
563
  ALL_DEBUG_REGISTERS(i)
564
    {
565
      if (I386_DR_WATCH_HIT (i))
566
        return 1;
567
    }
568
 
569
  return 0;
570
}
571
 
572
/* Insert a hardware-assisted breakpoint at address ADDR.  SHADOW is
573
   unused.  Return 0 on success, EBUSY on failure.  */
574
int
575
i386_insert_hw_breakpoint (CORE_ADDR addr, void *shadow)
576
{
577
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
578
  int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0;
579
 
580
  if (maint_show_dr)
581
    i386_show_dr ("insert_hwbp", addr, 1, hw_execute);
582
 
583
  return retval;
584
}
585
 
586
/* Remove a hardware-assisted breakpoint at address ADDR.  SHADOW is
587
   unused.  Return 0 on success, -1 on failure.  */
588
int
589
i386_remove_hw_breakpoint (CORE_ADDR addr, void *shadow)
590
{
591
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
592
  int retval = i386_remove_aligned_watchpoint (addr, len_rw);
593
 
594
  if (maint_show_dr)
595
    i386_show_dr ("remove_hwbp", addr, 1, hw_execute);
596
 
597
  return retval;
598
}
599
 
600
#endif /* I386_USE_GENERIC_WATCHPOINTS */
601
 
602
 
603
void
604
_initialize_i386_nat (void)
605
{
606
#ifdef I386_USE_GENERIC_WATCHPOINTS
607
  /* A maintenance command to enable printing the internal DRi mirror
608
     variables.  */
609
  add_set_cmd ("show-debug-regs", class_maintenance,
610
               var_boolean, (char *) &maint_show_dr,
611
               "\
612
Set whether to show variables that mirror the x86 debug registers.\n\
613
Use \"on\" to enable, \"off\" to disable.\n\
614
If enabled, the debug registers values are shown when GDB inserts\n\
615
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
616
triggers a breakpoint or watchpoint.", &maintenancelist);
617
#endif
618
}

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