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/* Intel x86 (a.k.a. ia32) native-dependent code.
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Copyright (C) 2001 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "breakpoint.h"
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#include "command.h"
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#include "gdbcmd.h"
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/* Support for hardware watchpoints and breakpoints using the x86
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debug registers.
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This provides several functions for inserting and removing
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hardware-assisted breakpoints and watchpoints, testing if
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one or more of the watchpoints triggered and at what address,
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checking whether a given region can be watched, etc.
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A target which wants to use these functions should define
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several macros, such as `target_insert_watchpoint' and
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`target_stopped_data_address', listed in target.h, to call
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the appropriate functions below. It should also define
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I386_USE_GENERIC_WATCHPOINTS in its tm.h file.
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In addition, each target should provide several low-level
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macros that will be called to insert watchpoints and hardware
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breakpoints into the inferior, remove them, and check their
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status. These macros are:
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I386_DR_LOW_SET_CONTROL -- set the debug control (DR7)
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register to a given value
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I386_DR_LOW_SET_ADDR -- put an address into one debug
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register
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I386_DR_LOW_RESET_ADDR -- reset the address stored in
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one debug register
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I386_DR_LOW_GET_STATUS -- return the value of the debug
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status (DR6) register.
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The functions below implement debug registers sharing by
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reference counts, and allow to watch regions up to 16 bytes
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long. */
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#ifdef I386_USE_GENERIC_WATCHPOINTS
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/* Debug registers' indices. */
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#define DR_NADDR 4 /* the number of debug address registers */
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#define DR_STATUS 6 /* index of debug status register (DR6) */
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#define DR_CONTROL 7 /* index of debug control register (DR7) */
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/* DR7 Debug Control register fields. */
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/* How many bits to skip in DR7 to get to R/W and LEN fields. */
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#define DR_CONTROL_SHIFT 16
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/* How many bits in DR7 per R/W and LEN field for each watchpoint. */
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#define DR_CONTROL_SIZE 4
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/* Watchpoint/breakpoint read/write fields in DR7. */
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#define DR_RW_EXECUTE (0x0) /* break on instruction execution */
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#define DR_RW_WRITE (0x1) /* break on data writes */
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#define DR_RW_READ (0x3) /* break on data reads or writes */
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/* This is here for completeness. No platform supports this
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functionality yet (as of Mar-2001). Note that the DE flag in the
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CR4 register needs to be set to support this. */
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#ifndef DR_RW_IORW
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#define DR_RW_IORW (0x2) /* break on I/O reads or writes */
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#endif
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/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
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is so we could OR this with the read/write field defined above. */
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#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpt */
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#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch */
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#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch */
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/* Local and Global Enable flags in DR7.
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When the Local Enable flag is set, the breakpoint/watchpoint is
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enabled only for the current task; the processor automatically
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clears this flag on every task switch. When the Global Enable
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flag is set, the breakpoint/watchpoint is enabled for all tasks;
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the processor never clears this flag.
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Currently, all watchpoint are locally enabled. If you need to
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enable them globally, read the comment which pertains to this in
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i386_insert_aligned_watchpoint below. */
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#define DR_LOCAL_ENABLE_SHIFT 0 /* extra shift to the local enable bit */
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#define DR_GLOBAL_ENABLE_SHIFT 1 /* extra shift to the global enable bit */
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#define DR_ENABLE_SIZE 2 /* 2 enable bits per debug register */
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/* Local and global exact breakpoint enable flags (a.k.a. slowdown
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flags). These are only required on i386, to allow detection of the
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exact instruction which caused a watchpoint to break; i486 and
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later processors do that automatically. We set these flags for
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back compatibility. */
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#define DR_LOCAL_SLOWDOWN (0x100)
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#define DR_GLOBAL_SLOWDOWN (0x200)
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/* Fields reserved by Intel. This includes the GD (General Detect
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Enable) flag, which causes a debug exception to be generated when a
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MOV instruction accesses one of the debug registers.
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FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
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#define DR_CONTROL_RESERVED (0xFC00)
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/* Auxiliary helper macros. */
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/* A value that masks all fields in DR7 that are reserved by Intel. */
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#define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
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/* The I'th debug register is vacant if its Local and Global Enable
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bits are reset in the Debug Control register. */
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#define I386_DR_VACANT(i) \
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((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
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/* Locally enable the break/watchpoint in the I'th debug register. */
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#define I386_DR_LOCAL_ENABLE(i) \
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dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
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/* Globally enable the break/watchpoint in the I'th debug register. */
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#define I386_DR_GLOBAL_ENABLE(i) \
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dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
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/* Disable the break/watchpoint in the I'th debug register. */
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#define I386_DR_DISABLE(i) \
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dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
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/* Set in DR7 the RW and LEN fields for the I'th debug register. */
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#define I386_DR_SET_RW_LEN(i,rwlen) \
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do { \
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dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
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dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
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} while (0)
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/* Get from DR7 the RW and LEN fields for the I'th debug register. */
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#define I386_DR_GET_RW_LEN(i) \
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((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
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/* Did the watchpoint whose address is in the I'th register break? */
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#define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i)))
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/* A macro to loop over all debug registers. */
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#define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
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/* Mirror the inferior's DRi registers. We keep the status and
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control registers separated because they don't hold addresses. */
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static CORE_ADDR dr_mirror[DR_NADDR];
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static unsigned dr_status_mirror, dr_control_mirror;
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/* Reference counts for each debug register. */
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static int dr_ref_count[DR_NADDR];
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/* Whether or not to print the mirrored debug registers. */
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static int maint_show_dr;
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/* Types of operations supported by i386_handle_nonaligned_watchpoint. */
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typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
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/* Internal functions. */
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/* Return the value of a 4-bit field for DR7 suitable for watching a
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region of LEN bytes for accesses of type TYPE. LEN is assumed
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to have the value of 1, 2, or 4. */
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static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
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/* Insert a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bit-field from DR7 which describes the length and
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access type of the region to be watched by this watchpoint. Return
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static int i386_insert_aligned_watchpoint (CORE_ADDR addr,
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unsigned len_rw_bits);
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/* Remove a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bits from DR7 which describes the length and access
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type of the region watched by this watchpoint. Return 0 on
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success, -1 on failure. */
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static int i386_remove_aligned_watchpoint (CORE_ADDR addr,
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unsigned len_rw_bits);
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/* Insert or remove a (possibly non-aligned) watchpoint, or count the
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number of debug registers required to watch a region at address
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ADDR whose length is LEN for accesses of type TYPE. Return 0 on
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successful insertion or removal, a positive number when queried
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about the number of registers, or -1 on failure. If WHAT is not
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a valid value, bombs through internal_error. */
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static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what,
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CORE_ADDR addr, int len,
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enum target_hw_bp_type type);
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/* Implementation. */
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/* Clear the reference counts and forget everything we knew about
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the debug registers. */
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void
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i386_cleanup_dregs (void)
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{
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int i;
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ALL_DEBUG_REGISTERS(i)
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{
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dr_mirror[i] = 0;
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dr_ref_count[i] = 0;
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}
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dr_control_mirror = 0;
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dr_status_mirror = 0;
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}
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/* Print the values of the mirrored debug registers.
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This is called when maint_show_dr is non-zero. To set that
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up, type "maint show-debug-regs" at GDB's prompt. */
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static void
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i386_show_dr (const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type)
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{
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int i;
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puts_unfiltered (func);
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if (addr || len)
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printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
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/* This code is for ia32, so casting CORE_ADDR
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to unsigned long should be okay. */
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(unsigned long)addr, len,
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type == hw_write ? "data-write"
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: (type == hw_read ? "data-read"
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: (type == hw_access ? "data-read/write"
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: (type == hw_execute ? "instruction-execute"
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/* FIXME: if/when I/O read/write
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watchpoints are supported, add them
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here. */
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: "??unknown??"))));
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puts_unfiltered (":\n");
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printf_unfiltered ("\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
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dr_control_mirror, dr_status_mirror);
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ALL_DEBUG_REGISTERS(i)
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{
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printf_unfiltered ("\tDR%d: addr=%08lx, ref.count=%d DR%d: addr=%08lx, ref.count=%d\n",
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i, dr_mirror[i], dr_ref_count[i],
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i+1, dr_mirror[i+1], dr_ref_count[i+1]);
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i++;
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}
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}
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/* Return the value of a 4-bit field for DR7 suitable for watching a
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region of LEN bytes for accesses of type TYPE. LEN is assumed
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to have the value of 1, 2, or 4. */
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static unsigned
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i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
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{
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unsigned rw;
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switch (type)
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{
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case hw_execute:
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rw = DR_RW_EXECUTE;
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break;
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case hw_write:
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rw = DR_RW_WRITE;
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break;
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case hw_read: /* x86 doesn't support data-read watchpoints */
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case hw_access:
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rw = DR_RW_READ;
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break;
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#if 0
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case hw_io_access: /* not yet supported */
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rw = DR_RW_IORW;
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break;
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#endif
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default:
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internal_error (__FILE__, __LINE__, "\
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Invalid hw breakpoint type %d in i386_length_and_rw_bits.\n", (int)type);
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}
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switch (len)
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{
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case 4:
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return (DR_LEN_4 | rw);
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case 2:
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return (DR_LEN_2 | rw);
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case 1:
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return (DR_LEN_1 | rw);
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default:
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internal_error (__FILE__, __LINE__, "\
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Invalid hw breakpoint length %d in i386_length_and_rw_bits.\n", len);
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}
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}
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/* Insert a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bits from DR7 which describes the length and access
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309 |
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type of the region to be watched by this watchpoint. Return 0 on
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success, -1 on failure. */
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static int
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i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
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{
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int i;
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/* First, look for an occupied debug register with the same address
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and the same RW and LEN definitions. If we find one, we can
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reuse it for this watchpoint as well (and save a register). */
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ALL_DEBUG_REGISTERS(i)
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{
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if (!I386_DR_VACANT (i)
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&& dr_mirror[i] == addr
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&& I386_DR_GET_RW_LEN (i) == len_rw_bits)
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{
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dr_ref_count[i]++;
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return 0;
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}
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}
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/* Next, look for a vacant debug register. */
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ALL_DEBUG_REGISTERS(i)
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{
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if (I386_DR_VACANT (i))
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break;
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}
|
336 |
|
|
|
337 |
|
|
/* No more debug registers! */
|
338 |
|
|
if (i >= DR_NADDR)
|
339 |
|
|
return -1;
|
340 |
|
|
|
341 |
|
|
/* Now set up the register I to watch our region. */
|
342 |
|
|
|
343 |
|
|
/* Record the info in our local mirrored array. */
|
344 |
|
|
dr_mirror[i] = addr;
|
345 |
|
|
dr_ref_count[i] = 1;
|
346 |
|
|
I386_DR_SET_RW_LEN (i, len_rw_bits);
|
347 |
|
|
/* Note: we only enable the watchpoint locally, i.e. in the current
|
348 |
|
|
task. Currently, no x86 target allows or supports global
|
349 |
|
|
watchpoints; however, if any target would want that in the
|
350 |
|
|
future, GDB should probably provide a command to control whether
|
351 |
|
|
to enable watchpoints globally or locally, and the code below
|
352 |
|
|
should use global or local enable and slow-down flags as
|
353 |
|
|
appropriate. */
|
354 |
|
|
I386_DR_LOCAL_ENABLE (i);
|
355 |
|
|
dr_control_mirror |= DR_LOCAL_SLOWDOWN;
|
356 |
|
|
dr_control_mirror &= I386_DR_CONTROL_MASK;
|
357 |
|
|
|
358 |
|
|
/* Finally, actually pass the info to the inferior. */
|
359 |
|
|
I386_DR_LOW_SET_ADDR (i, addr);
|
360 |
|
|
I386_DR_LOW_SET_CONTROL (dr_control_mirror);
|
361 |
|
|
|
362 |
|
|
return 0;
|
363 |
|
|
}
|
364 |
|
|
|
365 |
|
|
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
|
366 |
|
|
according to the length of the region to watch. LEN_RW_BITS is the
|
367 |
|
|
value of the bits from DR7 which describes the length and access
|
368 |
|
|
type of the region watched by this watchpoint. Return 0 on
|
369 |
|
|
success, -1 on failure. */
|
370 |
|
|
static int
|
371 |
|
|
i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
|
372 |
|
|
{
|
373 |
|
|
int i, retval = -1;
|
374 |
|
|
|
375 |
|
|
ALL_DEBUG_REGISTERS(i)
|
376 |
|
|
{
|
377 |
|
|
if (!I386_DR_VACANT (i)
|
378 |
|
|
&& dr_mirror[i] == addr
|
379 |
|
|
&& I386_DR_GET_RW_LEN (i) == len_rw_bits)
|
380 |
|
|
{
|
381 |
|
|
if (--dr_ref_count[i] == 0) /* no longer in use? */
|
382 |
|
|
{
|
383 |
|
|
/* Reset our mirror. */
|
384 |
|
|
dr_mirror[i] = 0;
|
385 |
|
|
I386_DR_DISABLE (i);
|
386 |
|
|
/* Reset it in the inferior. */
|
387 |
|
|
I386_DR_LOW_SET_CONTROL (dr_control_mirror);
|
388 |
|
|
I386_DR_LOW_RESET_ADDR (i);
|
389 |
|
|
}
|
390 |
|
|
retval = 0;
|
391 |
|
|
}
|
392 |
|
|
}
|
393 |
|
|
|
394 |
|
|
return retval;
|
395 |
|
|
}
|
396 |
|
|
|
397 |
|
|
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
|
398 |
|
|
number of debug registers required to watch a region at address
|
399 |
|
|
ADDR whose length is LEN for accesses of type TYPE. Return 0 on
|
400 |
|
|
successful insertion or removal, a positive number when queried
|
401 |
|
|
about the number of registers, or -1 on failure. If WHAT is not
|
402 |
|
|
a valid value, bombs through internal_error. */
|
403 |
|
|
static int
|
404 |
|
|
i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len,
|
405 |
|
|
enum target_hw_bp_type type)
|
406 |
|
|
{
|
407 |
|
|
int align;
|
408 |
|
|
int size;
|
409 |
|
|
int rv = 0, status = 0;
|
410 |
|
|
|
411 |
|
|
static int size_try_array[4][4] =
|
412 |
|
|
{
|
413 |
|
|
{ 1, 1, 1, 1 }, /* trying size one */
|
414 |
|
|
{ 2, 1, 2, 1 }, /* trying size two */
|
415 |
|
|
{ 2, 1, 2, 1 }, /* trying size three */
|
416 |
|
|
{ 4, 1, 2, 1 } /* trying size four */
|
417 |
|
|
};
|
418 |
|
|
|
419 |
|
|
while (len > 0)
|
420 |
|
|
{
|
421 |
|
|
align = addr % 4;
|
422 |
|
|
/* Four is the maximum length an x86 debug register can watch. */
|
423 |
|
|
size = size_try_array[len > 4 ? 3 : len - 1][align];
|
424 |
|
|
if (what == WP_COUNT)
|
425 |
|
|
/* size_try_array[] is defined so that each iteration through
|
426 |
|
|
the loop is guaranteed to produce an address and a size
|
427 |
|
|
that can be watched with a single debug register. Thus,
|
428 |
|
|
for counting the registers required to watch a region, we
|
429 |
|
|
simply need to increment the count on each iteration. */
|
430 |
|
|
rv++;
|
431 |
|
|
else
|
432 |
|
|
{
|
433 |
|
|
unsigned len_rw = i386_length_and_rw_bits (size, type);
|
434 |
|
|
|
435 |
|
|
if (what == WP_INSERT)
|
436 |
|
|
status = i386_insert_aligned_watchpoint (addr, len_rw);
|
437 |
|
|
else if (what == WP_REMOVE)
|
438 |
|
|
status = i386_remove_aligned_watchpoint (addr, len_rw);
|
439 |
|
|
else
|
440 |
|
|
internal_error (__FILE__, __LINE__, "\
|
441 |
|
|
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
|
442 |
|
|
(int)what);
|
443 |
|
|
/* We keep the loop going even after a failure, because some
|
444 |
|
|
of the other aligned watchpoints might still succeed
|
445 |
|
|
(e.g. if they watch addresses that are already watched,
|
446 |
|
|
in which case we just increment the reference counts of
|
447 |
|
|
occupied debug registers). If we break out of the loop
|
448 |
|
|
too early, we could cause those addresses watched by
|
449 |
|
|
other watchpoints to be disabled when breakpoint.c reacts
|
450 |
|
|
to our failure to insert this watchpoint and tries to
|
451 |
|
|
remove it. */
|
452 |
|
|
if (status)
|
453 |
|
|
rv = status;
|
454 |
|
|
}
|
455 |
|
|
addr += size;
|
456 |
|
|
len -= size;
|
457 |
|
|
}
|
458 |
|
|
return rv;
|
459 |
|
|
}
|
460 |
|
|
|
461 |
|
|
/* Insert a watchpoint to watch a memory region which starts at
|
462 |
|
|
address ADDR and whose length is LEN bytes. Watch memory accesses
|
463 |
|
|
of the type TYPE. Return 0 on success, -1 on failure. */
|
464 |
|
|
int
|
465 |
|
|
i386_insert_watchpoint (CORE_ADDR addr, int len, int type)
|
466 |
|
|
{
|
467 |
|
|
int retval;
|
468 |
|
|
|
469 |
|
|
if (len == 3 || len > 4 || addr % len != 0)
|
470 |
|
|
retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type);
|
471 |
|
|
else
|
472 |
|
|
{
|
473 |
|
|
unsigned len_rw = i386_length_and_rw_bits (len, type);
|
474 |
|
|
|
475 |
|
|
retval = i386_insert_aligned_watchpoint (addr, len_rw);
|
476 |
|
|
}
|
477 |
|
|
|
478 |
|
|
if (maint_show_dr)
|
479 |
|
|
i386_show_dr ("insert_watchpoint", addr, len, type);
|
480 |
|
|
|
481 |
|
|
return retval;
|
482 |
|
|
}
|
483 |
|
|
|
484 |
|
|
/* Remove a watchpoint that watched the memory region which starts at
|
485 |
|
|
address ADDR, whose length is LEN bytes, and for accesses of the
|
486 |
|
|
type TYPE. Return 0 on success, -1 on failure. */
|
487 |
|
|
int
|
488 |
|
|
i386_remove_watchpoint (CORE_ADDR addr, int len, int type)
|
489 |
|
|
{
|
490 |
|
|
int retval;
|
491 |
|
|
|
492 |
|
|
if (len == 3 || len > 4 || addr % len != 0)
|
493 |
|
|
retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type);
|
494 |
|
|
else
|
495 |
|
|
{
|
496 |
|
|
unsigned len_rw = i386_length_and_rw_bits (len, type);
|
497 |
|
|
|
498 |
|
|
retval = i386_remove_aligned_watchpoint (addr, len_rw);
|
499 |
|
|
}
|
500 |
|
|
|
501 |
|
|
if (maint_show_dr)
|
502 |
|
|
i386_show_dr ("remove_watchpoint", addr, len, type);
|
503 |
|
|
|
504 |
|
|
return retval;
|
505 |
|
|
}
|
506 |
|
|
|
507 |
|
|
/* Return non-zero if we can watch a memory region that starts at
|
508 |
|
|
address ADDR and whose length is LEN bytes. */
|
509 |
|
|
int
|
510 |
|
|
i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
|
511 |
|
|
{
|
512 |
|
|
/* Compute how many aligned watchpoints we would need to cover this
|
513 |
|
|
region. */
|
514 |
|
|
int nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len,
|
515 |
|
|
hw_write);
|
516 |
|
|
|
517 |
|
|
return nregs <= DR_NADDR ? 1 : 0;
|
518 |
|
|
}
|
519 |
|
|
|
520 |
|
|
/* If the inferior has some watchpoint that triggered, return the
|
521 |
|
|
address associated with that watchpoint. Otherwise, return
|
522 |
|
|
zero. */
|
523 |
|
|
CORE_ADDR
|
524 |
|
|
i386_stopped_data_address (void)
|
525 |
|
|
{
|
526 |
|
|
int i;
|
527 |
|
|
CORE_ADDR ret = 0;
|
528 |
|
|
|
529 |
|
|
dr_status_mirror = I386_DR_LOW_GET_STATUS ();
|
530 |
|
|
|
531 |
|
|
ALL_DEBUG_REGISTERS(i)
|
532 |
|
|
{
|
533 |
|
|
if (I386_DR_WATCH_HIT (i)
|
534 |
|
|
/* This second condition makes sure DRi is set up for a data
|
535 |
|
|
watchpoint, not a hardware breakpoint. The reason is
|
536 |
|
|
that GDB doesn't call the target_stopped_data_address
|
537 |
|
|
method except for data watchpoints. In other words, I'm
|
538 |
|
|
being paranoiac. */
|
539 |
|
|
&& I386_DR_GET_RW_LEN (i) != 0)
|
540 |
|
|
{
|
541 |
|
|
ret = dr_mirror[i];
|
542 |
|
|
if (maint_show_dr)
|
543 |
|
|
i386_show_dr ("watchpoint_hit", ret, -1, hw_write);
|
544 |
|
|
}
|
545 |
|
|
}
|
546 |
|
|
if (maint_show_dr && ret == 0)
|
547 |
|
|
i386_show_dr ("stopped_data_addr", 0, 0, hw_write);
|
548 |
|
|
|
549 |
|
|
return ret;
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
/* Return non-zero if the inferior has some break/watchpoint that
|
553 |
|
|
triggered. */
|
554 |
|
|
int
|
555 |
|
|
i386_stopped_by_hwbp (void)
|
556 |
|
|
{
|
557 |
|
|
int i;
|
558 |
|
|
|
559 |
|
|
dr_status_mirror = I386_DR_LOW_GET_STATUS ();
|
560 |
|
|
if (maint_show_dr)
|
561 |
|
|
i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute);
|
562 |
|
|
|
563 |
|
|
ALL_DEBUG_REGISTERS(i)
|
564 |
|
|
{
|
565 |
|
|
if (I386_DR_WATCH_HIT (i))
|
566 |
|
|
return 1;
|
567 |
|
|
}
|
568 |
|
|
|
569 |
|
|
return 0;
|
570 |
|
|
}
|
571 |
|
|
|
572 |
|
|
/* Insert a hardware-assisted breakpoint at address ADDR. SHADOW is
|
573 |
|
|
unused. Return 0 on success, EBUSY on failure. */
|
574 |
|
|
int
|
575 |
|
|
i386_insert_hw_breakpoint (CORE_ADDR addr, void *shadow)
|
576 |
|
|
{
|
577 |
|
|
unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
|
578 |
|
|
int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0;
|
579 |
|
|
|
580 |
|
|
if (maint_show_dr)
|
581 |
|
|
i386_show_dr ("insert_hwbp", addr, 1, hw_execute);
|
582 |
|
|
|
583 |
|
|
return retval;
|
584 |
|
|
}
|
585 |
|
|
|
586 |
|
|
/* Remove a hardware-assisted breakpoint at address ADDR. SHADOW is
|
587 |
|
|
unused. Return 0 on success, -1 on failure. */
|
588 |
|
|
int
|
589 |
|
|
i386_remove_hw_breakpoint (CORE_ADDR addr, void *shadow)
|
590 |
|
|
{
|
591 |
|
|
unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
|
592 |
|
|
int retval = i386_remove_aligned_watchpoint (addr, len_rw);
|
593 |
|
|
|
594 |
|
|
if (maint_show_dr)
|
595 |
|
|
i386_show_dr ("remove_hwbp", addr, 1, hw_execute);
|
596 |
|
|
|
597 |
|
|
return retval;
|
598 |
|
|
}
|
599 |
|
|
|
600 |
|
|
#endif /* I386_USE_GENERIC_WATCHPOINTS */
|
601 |
|
|
|
602 |
|
|
|
603 |
|
|
void
|
604 |
|
|
_initialize_i386_nat (void)
|
605 |
|
|
{
|
606 |
|
|
#ifdef I386_USE_GENERIC_WATCHPOINTS
|
607 |
|
|
/* A maintenance command to enable printing the internal DRi mirror
|
608 |
|
|
variables. */
|
609 |
|
|
add_set_cmd ("show-debug-regs", class_maintenance,
|
610 |
|
|
var_boolean, (char *) &maint_show_dr,
|
611 |
|
|
"\
|
612 |
|
|
Set whether to show variables that mirror the x86 debug registers.\n\
|
613 |
|
|
Use \"on\" to enable, \"off\" to disable.\n\
|
614 |
|
|
If enabled, the debug registers values are shown when GDB inserts\n\
|
615 |
|
|
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
|
616 |
|
|
triggers a breakpoint or watchpoint.", &maintenancelist);
|
617 |
|
|
#endif
|
618 |
|
|
}
|