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/* Functions specific to running gdb native on IA-64 running Linux.
   Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
 
   This file is part of GDB.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */
 
#include "defs.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"
#include "regcache.h"
 
#include <signal.h>
#include <sys/ptrace.h>
#include <sys/wait.h>
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
#include <sys/user.h>
 
#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>
 
/* Prototypes for supply_gregset etc. */
#include "gregset.h"
 
/* These must match the order of the register names.
 
   Some sort of lookup table is needed because the offsets associated
   with the registers are all over the board.  */
 
static int u_offsets[] =
  {
    /* general registers */
    -1,         /* gr0 not available; i.e, it's always zero */
    PT_R1,
    PT_R2,
    PT_R3,
    PT_R4,
    PT_R5,
    PT_R6,
    PT_R7,
    PT_R8,
    PT_R9,
    PT_R10,
    PT_R11,
    PT_R12,
    PT_R13,
    PT_R14,
    PT_R15,
    PT_R16,
    PT_R17,
    PT_R18,
    PT_R19,
    PT_R20,
    PT_R21,
    PT_R22,
    PT_R23,
    PT_R24,
    PT_R25,
    PT_R26,
    PT_R27,
    PT_R28,
    PT_R29,
    PT_R30,
    PT_R31,
    /* gr32 through gr127 not directly available via the ptrace interface */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    /* Floating point registers */
    -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
    PT_F2,
    PT_F3,
    PT_F4,
    PT_F5,
    PT_F6,
    PT_F7,
    PT_F8,
    PT_F9,
    PT_F10,
    PT_F11,
    PT_F12,
    PT_F13,
    PT_F14,
    PT_F15,
    PT_F16,
    PT_F17,
    PT_F18,
    PT_F19,
    PT_F20,
    PT_F21,
    PT_F22,
    PT_F23,
    PT_F24,
    PT_F25,
    PT_F26,
    PT_F27,
    PT_F28,
    PT_F29,
    PT_F30,
    PT_F31,
    PT_F32,
    PT_F33,
    PT_F34,
    PT_F35,
    PT_F36,
    PT_F37,
    PT_F38,
    PT_F39,
    PT_F40,
    PT_F41,
    PT_F42,
    PT_F43,
    PT_F44,
    PT_F45,
    PT_F46,
    PT_F47,
    PT_F48,
    PT_F49,
    PT_F50,
    PT_F51,
    PT_F52,
    PT_F53,
    PT_F54,
    PT_F55,
    PT_F56,
    PT_F57,
    PT_F58,
    PT_F59,
    PT_F60,
    PT_F61,
    PT_F62,
    PT_F63,
    PT_F64,
    PT_F65,
    PT_F66,
    PT_F67,
    PT_F68,
    PT_F69,
    PT_F70,
    PT_F71,
    PT_F72,
    PT_F73,
    PT_F74,
    PT_F75,
    PT_F76,
    PT_F77,
    PT_F78,
    PT_F79,
    PT_F80,
    PT_F81,
    PT_F82,
    PT_F83,
    PT_F84,
    PT_F85,
    PT_F86,
    PT_F87,
    PT_F88,
    PT_F89,
    PT_F90,
    PT_F91,
    PT_F92,
    PT_F93,
    PT_F94,
    PT_F95,
    PT_F96,
    PT_F97,
    PT_F98,
    PT_F99,
    PT_F100,
    PT_F101,
    PT_F102,
    PT_F103,
    PT_F104,
    PT_F105,
    PT_F106,
    PT_F107,
    PT_F108,
    PT_F109,
    PT_F110,
    PT_F111,
    PT_F112,
    PT_F113,
    PT_F114,
    PT_F115,
    PT_F116,
    PT_F117,
    PT_F118,
    PT_F119,
    PT_F120,
    PT_F121,
    PT_F122,
    PT_F123,
    PT_F124,
    PT_F125,
    PT_F126,
    PT_F127,
    /* predicate registers - we don't fetch these individually */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* branch registers */
    PT_B0,
    PT_B1,
    PT_B2,
    PT_B3,
    PT_B4,
    PT_B5,
    PT_B6,
    PT_B7,
    /* virtual frame pointer and virtual return address pointer */
    -1, -1,
    /* other registers */
    PT_PR,
    PT_CR_IIP,  /* ip */
    PT_CR_IPSR, /* psr */
    PT_CFM,     /* cfm */
    /* kernel registers not visible via ptrace interface (?) */
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* hole */
    -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_RSC,
    PT_AR_BSP,
    PT_AR_BSPSTORE,
    PT_AR_RNAT,
    -1,
    -1,         /* Not available: FCR, IA32 floating control register */
    -1, -1,
    -1,         /* Not available: EFLAG */
    -1,         /* Not available: CSD */
    -1,         /* Not available: SSD */
    -1,         /* Not available: CFLG */
    -1,         /* Not available: FSR */
    -1,         /* Not available: FIR */
    -1,         /* Not available: FDR */
    -1,
    PT_AR_CCV,
    -1, -1, -1,
    PT_AR_UNAT,
    -1, -1, -1,
    PT_AR_FPSR,
    -1, -1, -1,
    -1,         /* Not available: ITC */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_PFS,
    PT_AR_LC,
    -1,         /* Not available: EC, the Epilog Count register */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1,
    /* nat bits - not fetched directly; instead we obtain these bits from
       either rnat or unat or from memory. */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
  };
 
CORE_ADDR
register_addr (int regno, CORE_ADDR blockend)
{
  CORE_ADDR addr;
 
  if (regno < 0 || regno >= NUM_REGS)
    error ("Invalid register number %d.", regno);
 
  if (u_offsets[regno] == -1)
    addr = 0;
  else
    addr = (CORE_ADDR) u_offsets[regno];
 
  return addr;
}
 
int ia64_cannot_fetch_register (regno)
     int regno;
{
  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
}
 
int ia64_cannot_store_register (regno)
     int regno;
{
  /* Rationale behind not permitting stores to bspstore...
 
     The IA-64 architecture provides bspstore and bsp which refer
     memory locations in the RSE's backing store.  bspstore is the
     next location which will be written when the RSE needs to write
     to memory.  bsp is the address at which r32 in the current frame
     would be found if it were written to the backing store.
 
     The IA-64 architecture provides read-only access to bsp and
     read/write access to bspstore (but only when the RSE is in
     the enforced lazy mode).  It should be noted that stores
     to bspstore also affect the value of bsp.  Changing bspstore
     does not affect the number of dirty entries between bspstore
     and bsp, so changing bspstore by N words will also cause bsp
     to be changed by (roughly) N as well.  (It could be N-1 or N+1
     depending upon where the NaT collection bits fall.)
 
     OTOH, the linux kernel provides read/write access to bsp (and
     currently read/write access to bspstore as well).  But it
     is definitely the case that if you change one, the other
     will change at the same time.  It is more useful to gdb to
     be able to change bsp.  So in order to prevent strange and
     undesirable things from happening when a dummy stack frame
     is popped (after calling an inferior function), we allow
     bspstore to be read, but not written.  (Note that popping
     a (generic) dummy stack frame causes all registers that
     were previously read from the inferior process to be written
     back.)  */
 
  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
         || regno == IA64_BSPSTORE_REGNUM;
}
 
void
supply_gregset (gregset_t *gregsetp)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;
 
  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
    }
 
  /* FIXME: NAT collection bits are at index 32; gotta deal with these
     somehow... */
 
  supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
 
  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
    }
 
  supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
  supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
  supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
  supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
  supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
  supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
  supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
  supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
  supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
  supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
  supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
  supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
  supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
}
 
void
fill_gregset (gregset_t *gregsetp, int regno)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;
 
#define COPY_REG(_idx_,_regi_) \
  if ((regno == -1) || regno == _regi_) \
    memcpy (regp + _idx_, &registers[REGISTER_BYTE (_regi_)], \
            REGISTER_RAW_SIZE (_regi_))
 
  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      COPY_REG (regi - IA64_GR0_REGNUM, regi);
    }
 
  /* FIXME: NAT collection bits at index 32? */
 
  COPY_REG (33, IA64_PR_REGNUM);
 
  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
    }
 
  COPY_REG (42, IA64_IP_REGNUM);
  COPY_REG (43, IA64_CFM_REGNUM);
  COPY_REG (44, IA64_PSR_REGNUM);
  COPY_REG (45, IA64_RSC_REGNUM);
  COPY_REG (46, IA64_BSP_REGNUM);
  COPY_REG (47, IA64_BSPSTORE_REGNUM);
  COPY_REG (48, IA64_RNAT_REGNUM);
  COPY_REG (49, IA64_CCV_REGNUM);
  COPY_REG (50, IA64_UNAT_REGNUM);
  COPY_REG (51, IA64_FPSR_REGNUM);
  COPY_REG (52, IA64_PFS_REGNUM);
  COPY_REG (53, IA64_LC_REGNUM);
  COPY_REG (54, IA64_EC_REGNUM);
}
 
/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), unpack the register contents and supply them as gdb's
   idea of the current floating point register values. */
 
void
supply_fpregset (fpregset_t *fpregsetp)
{
  register int regi;
  char *from;
 
  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
      supply_register (regi, from);
    }
}
 
/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), update the register specified by REGNO from gdb's idea
   of the current floating point register set.  If REGNO is -1, update
   them all. */
 
void
fill_fpregset (fpregset_t *fpregsetp, int regno)
{
  int regi;
  char *to;
  char *from;
 
  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      if ((regno == -1) || (regno == regi))
        {
          from = (char *) &registers[REGISTER_BYTE (regi)];
          to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
          memcpy (to, from, REGISTER_RAW_SIZE (regi));
        }
    }
}
 
#define IA64_PSR_DB (1UL << 24)
#define IA64_PSR_DD (1UL << 39)
 
static void
enable_watchpoints_in_psr (ptid_t ptid)
{
  CORE_ADDR psr;
 
  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  if (!(psr & IA64_PSR_DB))
    {
      psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
                                   watchpoints and breakpoints. */
      write_register_pid (IA64_PSR_REGNUM, psr, ptid);
    }
}
 
static long
fetch_debug_register (ptid_t ptid, int idx)
{
  long val;
  int tid;
 
  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);
 
  val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);
 
  return val;
}
 
static void
store_debug_register (ptid_t ptid, int idx, long val)
{
  int tid;
 
  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);
 
  (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
}
 
static void
fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    *dbr_addr = fetch_debug_register (ptid, 2 * idx);
  if (dbr_mask)
    *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
}
 
static void
store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    store_debug_register (ptid, 2 * idx, *dbr_addr);
  if (dbr_mask)
    store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
}
 
static int
is_power_of_2 (int val)
{
  int i, onecount;
 
  onecount = 0;
  for (i = 0; i < 8 * sizeof (val); i++)
    if (val & (1 << i))
      onecount++;
 
  return onecount <= 1;
}
 
int
ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;
 
  if (len <= 0 || !is_power_of_2 (len))
    return -1;
 
  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) == 0)
        {
          /* Exit loop if both r and w bits clear */
          break;
        }
    }
 
  if (idx == max_watchpoints)
    return -1;
 
  dbr_addr = (long) addr;
  dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
  dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
  switch (rw)
    {
    case hw_write:
      dbr_mask |= (1L << 62);                   /* Set w bit */
      break;
    case hw_read:
      dbr_mask |= (1L << 63);                   /* Set r bit */
      break;
    case hw_access:
      dbr_mask |= (3L << 62);                   /* Set both r and w bits */
      break;
    default:
      return -1;
    }
 
  store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
  enable_watchpoints_in_psr (ptid);
 
  return 0;
}
 
int
ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;
 
  if (len <= 0 || !is_power_of_2 (len))
    return -1;
 
  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
        {
          dbr_addr = 0;
          dbr_mask = 0;
          store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
          return 0;
        }
    }
  return -1;
}
 
CORE_ADDR
ia64_linux_stopped_by_watchpoint (ptid_t ptid)
{
  CORE_ADDR psr;
  int tid;
  struct siginfo siginfo;
 
  tid = TIDGET(ptid);
  if (tid == 0)
    tid = PIDGET (ptid);
 
  errno = 0;
  ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);
 
  if (errno != 0 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
    return 0;
 
  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
                           for the next instruction */
  write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 
  return (CORE_ADDR) siginfo.si_addr;
}

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[/] [or1k/] [trunk/] [insight/] [gdb/] [ia64-linux-nat.c] - Blame information for rev 1771

Line No.	Rev	Author	Line
1	578	markom	`/* Functions specific to running gdb native on IA-64 running Linux.`
2			`Copyright 1999, 2000, 2001 Free Software Foundation, Inc.`
3
4			`This file is part of GDB.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 59 Temple Place - Suite 330,`
19			`Boston, MA 02111-1307, USA. */`
20
21			`#include "defs.h"`
22			`#include "inferior.h"`
23			`#include "target.h"`
24			`#include "gdbcore.h"`
25			`#include "regcache.h"`
26
27			`#include <signal.h>`
28			`#include <sys/ptrace.h>`
29			`#include <sys/wait.h>`
30			`#ifdef HAVE_SYS_REG_H`
31			`#include <sys/reg.h>`
32			`#endif`
33			`#include <sys/user.h>`
34
35			`#include <asm/ptrace_offsets.h>`
36			`#include <sys/procfs.h>`
37
38			`/* Prototypes for supply_gregset etc. */`
39			`#include "gregset.h"`
40
41			`/* These must match the order of the register names.`
42
43			`Some sort of lookup table is needed because the offsets associated`
44			`with the registers are all over the board. */`
45
46			`static int u_offsets[] =`
47			`{`
48			`/* general registers */`
49			`-1, /* gr0 not available; i.e, it's always zero */`
50			`PT_R1,`
51			`PT_R2,`
52			`PT_R3,`
53			`PT_R4,`
54			`PT_R5,`
55			`PT_R6,`
56			`PT_R7,`
57			`PT_R8,`
58			`PT_R9,`
59			`PT_R10,`
60			`PT_R11,`
61			`PT_R12,`
62			`PT_R13,`
63			`PT_R14,`
64			`PT_R15,`
65			`PT_R16,`
66			`PT_R17,`
67			`PT_R18,`
68			`PT_R19,`
69			`PT_R20,`
70			`PT_R21,`
71			`PT_R22,`
72			`PT_R23,`
73			`PT_R24,`
74			`PT_R25,`
75			`PT_R26,`
76			`PT_R27,`
77			`PT_R28,`
78			`PT_R29,`
79			`PT_R30,`
80			`PT_R31,`
81			`/* gr32 through gr127 not directly available via the ptrace interface */`
82			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
83			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
84			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
85			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
86			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
87			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
88			`/* Floating point registers */`
89			`-1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */`
90			`PT_F2,`
91			`PT_F3,`
92			`PT_F4,`
93			`PT_F5,`
94			`PT_F6,`
95			`PT_F7,`
96			`PT_F8,`
97			`PT_F9,`
98			`PT_F10,`
99			`PT_F11,`
100			`PT_F12,`
101			`PT_F13,`
102			`PT_F14,`
103			`PT_F15,`
104			`PT_F16,`
105			`PT_F17,`
106			`PT_F18,`
107			`PT_F19,`
108			`PT_F20,`
109			`PT_F21,`
110			`PT_F22,`
111			`PT_F23,`
112			`PT_F24,`
113			`PT_F25,`
114			`PT_F26,`
115			`PT_F27,`
116			`PT_F28,`
117			`PT_F29,`
118			`PT_F30,`
119			`PT_F31,`
120			`PT_F32,`
121			`PT_F33,`
122			`PT_F34,`
123			`PT_F35,`
124			`PT_F36,`
125			`PT_F37,`
126			`PT_F38,`
127			`PT_F39,`
128			`PT_F40,`
129			`PT_F41,`
130			`PT_F42,`
131			`PT_F43,`
132			`PT_F44,`
133			`PT_F45,`
134			`PT_F46,`
135			`PT_F47,`
136			`PT_F48,`
137			`PT_F49,`
138			`PT_F50,`
139			`PT_F51,`
140			`PT_F52,`
141			`PT_F53,`
142			`PT_F54,`
143			`PT_F55,`
144			`PT_F56,`
145			`PT_F57,`
146			`PT_F58,`
147			`PT_F59,`
148			`PT_F60,`
149			`PT_F61,`
150			`PT_F62,`
151			`PT_F63,`
152			`PT_F64,`
153			`PT_F65,`
154			`PT_F66,`
155			`PT_F67,`
156			`PT_F68,`
157			`PT_F69,`
158			`PT_F70,`
159			`PT_F71,`
160			`PT_F72,`
161			`PT_F73,`
162			`PT_F74,`
163			`PT_F75,`
164			`PT_F76,`
165			`PT_F77,`
166			`PT_F78,`
167			`PT_F79,`
168			`PT_F80,`
169			`PT_F81,`
170			`PT_F82,`
171			`PT_F83,`
172			`PT_F84,`
173			`PT_F85,`
174			`PT_F86,`
175			`PT_F87,`
176			`PT_F88,`
177			`PT_F89,`
178			`PT_F90,`
179			`PT_F91,`
180			`PT_F92,`
181			`PT_F93,`
182			`PT_F94,`
183			`PT_F95,`
184			`PT_F96,`
185			`PT_F97,`
186			`PT_F98,`
187			`PT_F99,`
188			`PT_F100,`
189			`PT_F101,`
190			`PT_F102,`
191			`PT_F103,`
192			`PT_F104,`
193			`PT_F105,`
194			`PT_F106,`
195			`PT_F107,`
196			`PT_F108,`
197			`PT_F109,`
198			`PT_F110,`
199			`PT_F111,`
200			`PT_F112,`
201			`PT_F113,`
202			`PT_F114,`
203			`PT_F115,`
204			`PT_F116,`
205			`PT_F117,`
206			`PT_F118,`
207			`PT_F119,`
208			`PT_F120,`
209			`PT_F121,`
210			`PT_F122,`
211			`PT_F123,`
212			`PT_F124,`
213			`PT_F125,`
214			`PT_F126,`
215			`PT_F127,`
216			`/* predicate registers - we don't fetch these individually */`
217			`-1, -1, -1, -1, -1, -1, -1, -1,`
218			`-1, -1, -1, -1, -1, -1, -1, -1,`
219			`-1, -1, -1, -1, -1, -1, -1, -1,`
220			`-1, -1, -1, -1, -1, -1, -1, -1,`
221			`-1, -1, -1, -1, -1, -1, -1, -1,`
222			`-1, -1, -1, -1, -1, -1, -1, -1,`
223			`-1, -1, -1, -1, -1, -1, -1, -1,`
224			`-1, -1, -1, -1, -1, -1, -1, -1,`
225			`/* branch registers */`
226			`PT_B0,`
227			`PT_B1,`
228			`PT_B2,`
229			`PT_B3,`
230			`PT_B4,`
231			`PT_B5,`
232			`PT_B6,`
233			`PT_B7,`
234			`/* virtual frame pointer and virtual return address pointer */`
235			`-1, -1,`
236			`/* other registers */`
237			`PT_PR,`
238			`PT_CR_IIP, /* ip */`
239			`PT_CR_IPSR, /* psr */`
240			`PT_CFM, /* cfm */`
241			`/* kernel registers not visible via ptrace interface (?) */`
242			`-1, -1, -1, -1, -1, -1, -1, -1,`
243			`/* hole */`
244			`-1, -1, -1, -1, -1, -1, -1, -1,`
245			`PT_AR_RSC,`
246			`PT_AR_BSP,`
247			`PT_AR_BSPSTORE,`
248			`PT_AR_RNAT,`
249			`-1,`
250			`-1, /* Not available: FCR, IA32 floating control register */`
251			`-1, -1,`
252			`-1, /* Not available: EFLAG */`
253			`-1, /* Not available: CSD */`
254			`-1, /* Not available: SSD */`
255			`-1, /* Not available: CFLG */`
256			`-1, /* Not available: FSR */`
257			`-1, /* Not available: FIR */`
258			`-1, /* Not available: FDR */`
259			`-1,`
260			`PT_AR_CCV,`
261			`-1, -1, -1,`
262			`PT_AR_UNAT,`
263			`-1, -1, -1,`
264			`PT_AR_FPSR,`
265			`-1, -1, -1,`
266			`-1, /* Not available: ITC */`
267			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
268			`-1, -1, -1, -1, -1, -1, -1, -1, -1,`
269			`PT_AR_PFS,`
270			`PT_AR_LC,`
271			`-1, /* Not available: EC, the Epilog Count register */`
272			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
273			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
274			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
275			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
276			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
277			`-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,`
278			`-1,`
279			`/* nat bits - not fetched directly; instead we obtain these bits from`
280			`either rnat or unat or from memory. */`
281			`-1, -1, -1, -1, -1, -1, -1, -1,`
282			`-1, -1, -1, -1, -1, -1, -1, -1,`
283			`-1, -1, -1, -1, -1, -1, -1, -1,`
284			`-1, -1, -1, -1, -1, -1, -1, -1,`
285			`-1, -1, -1, -1, -1, -1, -1, -1,`
286			`-1, -1, -1, -1, -1, -1, -1, -1,`
287			`-1, -1, -1, -1, -1, -1, -1, -1,`
288			`-1, -1, -1, -1, -1, -1, -1, -1,`
289			`-1, -1, -1, -1, -1, -1, -1, -1,`
290			`-1, -1, -1, -1, -1, -1, -1, -1,`
291			`-1, -1, -1, -1, -1, -1, -1, -1,`
292			`-1, -1, -1, -1, -1, -1, -1, -1,`
293			`-1, -1, -1, -1, -1, -1, -1, -1,`
294			`-1, -1, -1, -1, -1, -1, -1, -1,`
295			`-1, -1, -1, -1, -1, -1, -1, -1,`
296			`-1, -1, -1, -1, -1, -1, -1, -1,`
297			`};`
298
299			`CORE_ADDR`
300			`register_addr (int regno, CORE_ADDR blockend)`
301			`{`
302			`CORE_ADDR addr;`
303
304			`if (regno < 0 \|\| regno >= NUM_REGS)`
305			`error ("Invalid register number %d.", regno);`
306
307			`if (u_offsets[regno] == -1)`
308			`addr = 0;`
309			`else`
310			`addr = (CORE_ADDR) u_offsets[regno];`
311
312			`return addr;`
313			`}`
314
315			`int ia64_cannot_fetch_register (regno)`
316			`int regno;`
317			`{`
318			`return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1;`
319			`}`
320
321			`int ia64_cannot_store_register (regno)`
322			`int regno;`
323			`{`
324			`/* Rationale behind not permitting stores to bspstore...`
325
326			`The IA-64 architecture provides bspstore and bsp which refer`
327			`memory locations in the RSE's backing store. bspstore is the`
328			`next location which will be written when the RSE needs to write`
329			`to memory. bsp is the address at which r32 in the current frame`
330			`would be found if it were written to the backing store.`
331
332			`The IA-64 architecture provides read-only access to bsp and`
333			`read/write access to bspstore (but only when the RSE is in`
334			`the enforced lazy mode). It should be noted that stores`
335			`to bspstore also affect the value of bsp. Changing bspstore`
336			`does not affect the number of dirty entries between bspstore`
337			`and bsp, so changing bspstore by N words will also cause bsp`
338			`to be changed by (roughly) N as well. (It could be N-1 or N+1`
339			`depending upon where the NaT collection bits fall.)`
340
341			`OTOH, the linux kernel provides read/write access to bsp (and`
342			`currently read/write access to bspstore as well). But it`
343			`is definitely the case that if you change one, the other`
344			`will change at the same time. It is more useful to gdb to`
345			`be able to change bsp. So in order to prevent strange and`
346			`undesirable things from happening when a dummy stack frame`
347			`is popped (after calling an inferior function), we allow`
348			`bspstore to be read, but not written. (Note that popping`
349			`a (generic) dummy stack frame causes all registers that`
350			`were previously read from the inferior process to be written`
351			`back.) */`
352
353			`return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1`
354			`\|\| regno == IA64_BSPSTORE_REGNUM;`
355			`}`
356
357			`void`
358			`supply_gregset (gregset_t *gregsetp)`
359			`{`
360			`int regi;`
361			`greg_t regp = (greg_t ) gregsetp;`
362
363			`for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)`
364			`{`
365			`supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));`
366			`}`
367
368			`/* FIXME: NAT collection bits are at index 32; gotta deal with these`
369			`somehow... */`
370
371			`supply_register (IA64_PR_REGNUM, (char *) (regp + 33));`
372
373			`for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)`
374			`{`
375			`supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));`
376			`}`
377
378			`supply_register (IA64_IP_REGNUM, (char *) (regp + 42));`
379			`supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));`
380			`supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));`
381			`supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));`
382			`supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));`
383			`supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));`
384			`supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));`
385			`supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));`
386			`supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));`
387			`supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));`
388			`supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));`
389			`supply_register (IA64_LC_REGNUM, (char *) (regp + 53));`
390			`supply_register (IA64_EC_REGNUM, (char *) (regp + 54));`
391			`}`
392
393			`void`
394			`fill_gregset (gregset_t *gregsetp, int regno)`
395			`{`
396			`int regi;`
397			`greg_t regp = (greg_t ) gregsetp;`
398
399			`#define COPY_REG(_idx_,_regi_) \`
400			`if ((regno == -1) \|\| regno == _regi_) \`
401			`memcpy (regp + _idx_, &registers[REGISTER_BYTE (_regi_)], \`
402			`REGISTER_RAW_SIZE (_regi_))`
403
404			`for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)`
405			`{`
406			`COPY_REG (regi - IA64_GR0_REGNUM, regi);`
407			`}`
408
409			`/* FIXME: NAT collection bits at index 32? */`
410
411			`COPY_REG (33, IA64_PR_REGNUM);`
412
413			`for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)`
414			`{`
415			`COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);`
416			`}`
417
418			`COPY_REG (42, IA64_IP_REGNUM);`
419			`COPY_REG (43, IA64_CFM_REGNUM);`
420			`COPY_REG (44, IA64_PSR_REGNUM);`
421			`COPY_REG (45, IA64_RSC_REGNUM);`
422			`COPY_REG (46, IA64_BSP_REGNUM);`
423			`COPY_REG (47, IA64_BSPSTORE_REGNUM);`
424			`COPY_REG (48, IA64_RNAT_REGNUM);`
425			`COPY_REG (49, IA64_CCV_REGNUM);`
426			`COPY_REG (50, IA64_UNAT_REGNUM);`
427			`COPY_REG (51, IA64_FPSR_REGNUM);`
428			`COPY_REG (52, IA64_PFS_REGNUM);`
429			`COPY_REG (53, IA64_LC_REGNUM);`
430			`COPY_REG (54, IA64_EC_REGNUM);`
431			`}`
432
433			`/* Given a pointer to a floating point register set in /proc format`
434			`(fpregset_t *), unpack the register contents and supply them as gdb's`
435			`idea of the current floating point register values. */`
436
437			`void`
438			`supply_fpregset (fpregset_t *fpregsetp)`
439			`{`
440			`register int regi;`
441			`char *from;`
442
443			`for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)`
444			`{`
445			`from = (char ) &((fpregsetp)[regi - IA64_FR0_REGNUM]);`
446			`supply_register (regi, from);`
447			`}`
448			`}`
449
450			`/* Given a pointer to a floating point register set in /proc format`
451			`(fpregset_t *), update the register specified by REGNO from gdb's idea`
452			`of the current floating point register set. If REGNO is -1, update`
453			`them all. */`
454
455			`void`
456			`fill_fpregset (fpregset_t *fpregsetp, int regno)`
457			`{`
458			`int regi;`
459			`char *to;`
460			`char *from;`
461
462			`for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)`
463			`{`
464			`if ((regno == -1) \|\| (regno == regi))`
465			`{`
466			`from = (char *) &registers[REGISTER_BYTE (regi)];`
467			`to = (char ) &((fpregsetp)[regi - IA64_FR0_REGNUM]);`
468			`memcpy (to, from, REGISTER_RAW_SIZE (regi));`
469			`}`
470			`}`
471			`}`
472
473			`#define IA64_PSR_DB (1UL << 24)`
474			`#define IA64_PSR_DD (1UL << 39)`
475
476			`static void`
477			`enable_watchpoints_in_psr (ptid_t ptid)`
478			`{`
479			`CORE_ADDR psr;`
480
481			`psr = read_register_pid (IA64_PSR_REGNUM, ptid);`
482			`if (!(psr & IA64_PSR_DB))`
483			`{`
484			`psr \|= IA64_PSR_DB; /* Set the db bit - this enables hardware`
485			`watchpoints and breakpoints. */`
486			`write_register_pid (IA64_PSR_REGNUM, psr, ptid);`
487			`}`
488			`}`
489
490			`static long`
491			`fetch_debug_register (ptid_t ptid, int idx)`
492			`{`
493			`long val;`
494			`int tid;`
495
496			`tid = TIDGET (ptid);`
497			`if (tid == 0)`
498			`tid = PIDGET (ptid);`
499
500			`val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);`
501
502			`return val;`
503			`}`
504
505			`static void`
506			`store_debug_register (ptid_t ptid, int idx, long val)`
507			`{`
508			`int tid;`
509
510			`tid = TIDGET (ptid);`
511			`if (tid == 0)`
512			`tid = PIDGET (ptid);`
513
514			`(void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);`
515			`}`
516
517			`static void`
518			`fetch_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)`
519			`{`
520			`if (dbr_addr)`
521			`dbr_addr = fetch_debug_register (ptid, 2 idx);`
522			`if (dbr_mask)`
523			`dbr_mask = fetch_debug_register (ptid, 2 idx + 1);`
524			`}`
525
526			`static void`
527			`store_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)`
528			`{`
529			`if (dbr_addr)`
530			`store_debug_register (ptid, 2 * idx, *dbr_addr);`
531			`if (dbr_mask)`
532			`store_debug_register (ptid, 2 * idx + 1, *dbr_mask);`
533			`}`
534
535			`static int`
536			`is_power_of_2 (int val)`
537			`{`
538			`int i, onecount;`
539
540			`onecount = 0;`
541			`for (i = 0; i < 8 * sizeof (val); i++)`
542			`if (val & (1 << i))`
543			`onecount++;`
544
545			`return onecount <= 1;`
546			`}`
547
548			`int`
549			`ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)`
550			`{`
551			`int idx;`
552			`long dbr_addr, dbr_mask;`
553			`int max_watchpoints = 4;`
554
555			`if (len <= 0 \|\| !is_power_of_2 (len))`
556			`return -1;`
557
558			`for (idx = 0; idx < max_watchpoints; idx++)`
559			`{`
560			`fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);`
561			`if ((dbr_mask & (0x3UL << 62)) == 0)`
562			`{`
563			`/* Exit loop if both r and w bits clear */`
564			`break;`
565			`}`
566			`}`
567
568			`if (idx == max_watchpoints)`
569			`return -1;`
570
571			`dbr_addr = (long) addr;`
572			`dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */`
573			`dbr_mask \|= 0x0800000000000000L; /* Only match privilege level 3 */`
574			`switch (rw)`
575			`{`
576			`case hw_write:`
577			`dbr_mask \|= (1L << 62); /* Set w bit */`
578			`break;`
579			`case hw_read:`
580			`dbr_mask \|= (1L << 63); /* Set r bit */`
581			`break;`
582			`case hw_access:`
583			`dbr_mask \|= (3L << 62); /* Set both r and w bits */`
584			`break;`
585			`default:`
586			`return -1;`
587			`}`
588
589			`store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);`
590			`enable_watchpoints_in_psr (ptid);`
591
592			`return 0;`
593			`}`
594
595			`int`
596			`ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)`
597			`{`
598			`int idx;`
599			`long dbr_addr, dbr_mask;`
600			`int max_watchpoints = 4;`
601
602			`if (len <= 0 \|\| !is_power_of_2 (len))`
603			`return -1;`
604
605			`for (idx = 0; idx < max_watchpoints; idx++)`
606			`{`
607			`fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);`
608			`if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)`
609			`{`
610			`dbr_addr = 0;`
611			`dbr_mask = 0;`
612			`store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);`
613			`return 0;`
614			`}`
615			`}`
616			`return -1;`
617			`}`
618
619			`CORE_ADDR`
620			`ia64_linux_stopped_by_watchpoint (ptid_t ptid)`
621			`{`
622			`CORE_ADDR psr;`
623			`int tid;`
624			`struct siginfo siginfo;`
625
626			`tid = TIDGET(ptid);`
627			`if (tid == 0)`
628			`tid = PIDGET (ptid);`
629
630			`errno = 0;`
631			`ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);`
632
633			`if (errno != 0 \|\| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)`
634			`return 0;`
635
636			`psr = read_register_pid (IA64_PSR_REGNUM, ptid);`
637			`psr \|= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint`
638			`for the next instruction */`
639			`write_register_pid (IA64_PSR_REGNUM, psr, ptid);`
640
641			`return (CORE_ADDR) siginfo.si_addr;`
642			`}`