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[/] [or1k/] [trunk/] [insight/] [include/] [opcode/] [or1k.h] - Blame information for rev 578

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1 578 markom 
/* Table of opcodes for the OpenRISC 1000 family.
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   Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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   Contributed by Damjan Lampret <lampret@opencores.org>.
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5 
This file is part of GDB and GAS.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
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21 
struct or32_opcode {
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  /* Name of the instruction.  */
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  char *name;
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  /* A string of characters which describe the operands.
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     Ranges for I..O can be wrong (I change them the time ;-).
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     Valid characters are:
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     ,   Itself.  The character appears in the assembly code.
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     rA  Register operand.
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     rB  Register operand.
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     rC  Register operand.
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     rD  Register operand.
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     I   An immediate operand, range -32768 to 32767.
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     J   An immediate operand, range -65536 to 65535.
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     K   An immediate operand, range -131072 to 131071.
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     L   An immediate operand, range 0 to 31.
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     M   An immediate operand, range -128 to 127.
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     N   An immediate operand, range -8 to 7.
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     O   An immediate operand, unused at the moment. */
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  char *args;
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  /* Opcode and operand encoding. */
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  char *encoding;
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  /* This will go out. */
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  int reloc[5];
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};
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50 
#ifndef CONST
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#define CONST
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#endif /* CONST */
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54 
static CONST struct or32_opcode or32_opcodes[] =
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{
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57 
{ "l.illegal", "",           "0x0 0000 0000 0000 0000 0000 0000 0000", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.j",       "X",          "0x0 00XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.jal",     "X",          "0x0 01XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.bnf",     "X",          "0x0 10XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.bf",      "X",          "0x0 11XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.bfnez",   "X",          "0x0 11XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}}, /* x*/
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{ "l.bfeqz",   "X",          "0x0 10XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}}, /* x*/
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{ "l.jmp",     "X",          "0x0 00XX XXXX XXXX XXXX XXXX XXXX XXXX", {NO_RELOC, NO_RELOC, NO_RELOC}}, /* x*/
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66 
{ "l.load32u", "rA,J(rB)",   "0x1 000J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.load16u", "rA,J(rB)",   "0x1 001J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.load16s", "rA,J(rB)",   "0x1 010J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.load8u",  "rA,J(rB)",   "0x1 011J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.load8s",  "rA,J(rB)",   "0x1 100J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.stor32",  "J(rA),rB",   "0x1 101J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.stor16",  "J(rA),rB",   "0x1 110J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.stor8",   "J(rA),rB",   "0x1 111J AAAA BBBB JJJJ JJJJ JJJJ JJJJ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.addi32s", "rA,rB,K",    "0x2 00KK AAAA BBBB KKKK KKKK KKKK KKKK", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.subi32s", "rA,rB,K",    "0x2 01KK AAAA BBBB KKKK KKKK KKKK KKKK", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.muli32s", "rA,rB,I",    "0x2 1000 AAAA BBBB IIII IIII IIII IIII", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.xori16",  "rA,rB,I",    "0x2 1001 AAAA BBBB IIII IIII IIII IIII", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.immlo16u","rA,lo(I)",   "0x2 1010 AAAA ---- IIII IIII IIII IIII", {NO_RELOC, RELOC_CONST}},
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{ "l.immhi16u","rA,hi(I)",   "0x2 1011 AAAA ---- IIII IIII IIII IIII", {NO_RELOC, RELOC_CONSTH}},
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81 
{ "l.sub32s",  "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x0  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
82 
{ "l.shla32",  "rA,rB,rC,L", "0x2 0xC  AAAA BBBB CCCC 0x1  LLLL L---", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.shra32",  "rA,rB,rC,L", "0x2 0xC  AAAA BBBB CCCC 0x2  LLLL L---", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.shrl32",  "rA,rB,rC,L", "0x2 0xC  AAAA BBBB CCCC 0x3  LLLL L---", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.and32",   "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x4  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.or32",    "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x5  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.xor32",   "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x6  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.mul32s",  "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x7  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.mul32u",  "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x8  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.div32s",  "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0x9  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.div32u",  "rA,rB,rC",   "0x2 0xC  AAAA BBBB CCCC 0xA  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.dcbf",    "J(rA)",      "0x3 0x0  AAAA IIII IIII 0x0  IIII IIII", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.dcbt",    "J(rA)",      "0x3 0x0  AAAA IIII IIII 0x1  IIII IIII", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.dcbi",    "J(rA)",      "0x3 0x0  AAAA IIII IIII 0x2  IIII IIII", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.dcia",    "",           "0x3 0x0  AAAA ---- ---- 0x3  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.dcfa",    "",           "0x3 0x0  AAAA ---- ---- 0x4  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.tlbia",   "",           "0x3 0x0  AAAA ---- ---- 0x5  ---- ----", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.mtsr",    "rS,rA",      "0x3 0x0  AAAA SSSS SSSS 0x6  SSSS SSSS", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "l.mfsr",    "rA,rS",      "0x3 0x0  AAAA SSSS SSSS 0x7  SSSS SSSS", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfeq32",  "rA,rB",      "0x4 0x0  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfne32",  "rA,rB",      "0x4 0x1  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfgt32s", "rA,rB",      "0x4 0x2  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfge32s", "rA,rB",      "0x4 0x3  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sflt32s", "rA,rB",      "0x4 0x4  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfle32s", "rA,rB",      "0x4 0x5  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfgt32u", "rA,rB",      "0x4 0x6  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sfge32u", "rA,rB",      "0x4 0x7  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.sflt32u", "rA,rB",      "0x4 0x8  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
111 
{ "h.sfle32u", "rA,rB",      "0x4 0x9  AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
112 
 
113 
{ "h.mov32",   "rA,rB",      "0x4 0xA  AAAA BBBB                    ", {NO_RELOC, NO_RELOC}},
114 
 
115 
{ "h.ext16s",  "rA",         "0x4 0xB  AAAA -000                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.ext16z",  "rA",         "0x4 0xB  AAAA -001                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.ext8s",   "rA",         "0x4 0xB  AAAA -010                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.ext8z",   "rA",         "0x4 0xB  AAAA -011                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.nop",     "",           "0x4 0xB  ---- -100                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.jalr",    "rA",         "0x4 0xB  AAAA -101                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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122 
{ "h.load32u", "rA,N(rB)",   "0x5 NNNN AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.stor32",  "N(rA),rB",   "0x6 NNNN AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.add32s",  "rA,rB,rD",   "0x7 DDDD AAAA BBBB                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.immch32s","rA,M",       "0x8 MMMM AAAA MMMM                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.jal",     "X",          "0x9 XXXX XXXX XXXX                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.bnf",     "X",          "0xA XXXX XXXX XXXX        ", {NO_RELOC, NO_RELOC, NO_RELOC}},
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{ "h.bf",      "X",          "0xB XXXX XXXX XXXX        ", {NO_RELOC, NO_RELOC, NO_RELOC}},
129 
{ "h.movi32",  "rA,M",       "0xC MMMM AAAA MMMM                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
130 
 
131 
{ "simprintf", "",           "0xE 0000 0000 0001                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
132 
{ "simrdtsc",  "rA",         "0xE 0000 AAAA 0002                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
133 
{ "h.sched",   "Z",          "0xF ZZZZ ZZZZ ZZZZ                    ", {NO_RELOC, NO_RELOC, NO_RELOC}},
134 
 
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{ "", "", "" }    /* Dummy entry, not included in NUM_OPCODES.  This
136 
         lets code examine entry i+1 without checking
137 
         if we've run off the end of the table.  */
138 
};
139 
 
140 
CONST unsigned int num_opcodes = (((sizeof or32_opcodes) / (sizeof or32_opcodes[0])) - 1);

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