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[/] [or1k/] [trunk/] [insight/] [opcodes/] [fr30-desc.c] - Blame information for rev 1765

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1 578 markom 
/* CPU data for fr30.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <ctype.h>
27 
#include <stdio.h>
28 
#include <stdarg.h>
29 
#include "ansidecl.h"
30 
#include "bfd.h"
31 
#include "symcat.h"
32 
#include "fr30-desc.h"
33 
#include "fr30-opc.h"
34 
#include "opintl.h"
35 
#include "libiberty.h"
36 
 
37 
/* Attributes.  */
38 
 
39 
static const CGEN_ATTR_ENTRY bool_attr[] =
40 
{
41 
  { "#f", 0 },
42 
  { "#t", 1 },
43 
  { 0, 0 }
44 
};
45 
 
46 
static const CGEN_ATTR_ENTRY MACH_attr[] =
47 
{
48 
  { "base", MACH_BASE },
49 
  { "fr30", MACH_FR30 },
50 
  { "max", MACH_MAX },
51 
  { 0, 0 }
52 
};
53 
 
54 
static const CGEN_ATTR_ENTRY ISA_attr[] =
55 
{
56 
  { "fr30", ISA_FR30 },
57 
  { "max", ISA_MAX },
58 
  { 0, 0 }
59 
};
60 
 
61 
const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
62 
{
63 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
64 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
68 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
70 
  { 0, 0, 0 }
71 
};
72 
 
73 
const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
74 
{
75 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
76 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78 
  { "PC", &bool_attr[0], &bool_attr[0] },
79 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
80 
  { 0, 0, 0 }
81 
};
82 
 
83 
const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
84 
{
85 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
86 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
91 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
93 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94 
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
95 
  { 0, 0, 0 }
96 
};
97 
 
98 
const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
99 
{
100 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
101 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
102 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
109 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110 
  { "PBB", &bool_attr[0], &bool_attr[0] },
111 
  { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 
  { 0, 0, 0 }
113 
};
114 
 
115 
/* Instruction set variants.  */
116 
 
117 
static const CGEN_ISA fr30_cgen_isa_table[] = {
118 
  { "fr30", 16, 16, 16, 48 },
119 
  { 0, 0, 0, 0, 0 }
120 
};
121 
 
122 
/* Machine variants.  */
123 
 
124 
static const CGEN_MACH fr30_cgen_mach_table[] = {
125 
  { "fr30", "fr30", MACH_FR30 },
126 
  { 0, 0, 0 }
127 
};
128 
 
129 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
130 
{
131 
  { "r0", 0, {0, {0}}, 0, 0 },
132 
  { "r1", 1, {0, {0}}, 0, 0 },
133 
  { "r2", 2, {0, {0}}, 0, 0 },
134 
  { "r3", 3, {0, {0}}, 0, 0 },
135 
  { "r4", 4, {0, {0}}, 0, 0 },
136 
  { "r5", 5, {0, {0}}, 0, 0 },
137 
  { "r6", 6, {0, {0}}, 0, 0 },
138 
  { "r7", 7, {0, {0}}, 0, 0 },
139 
  { "r8", 8, {0, {0}}, 0, 0 },
140 
  { "r9", 9, {0, {0}}, 0, 0 },
141 
  { "r10", 10, {0, {0}}, 0, 0 },
142 
  { "r11", 11, {0, {0}}, 0, 0 },
143 
  { "r12", 12, {0, {0}}, 0, 0 },
144 
  { "r13", 13, {0, {0}}, 0, 0 },
145 
  { "r14", 14, {0, {0}}, 0, 0 },
146 
  { "r15", 15, {0, {0}}, 0, 0 },
147 
  { "ac", 13, {0, {0}}, 0, 0 },
148 
  { "fp", 14, {0, {0}}, 0, 0 },
149 
  { "sp", 15, {0, {0}}, 0, 0 }
150 
};
151 
 
152 
CGEN_KEYWORD fr30_cgen_opval_gr_names =
153 
{
154 
  & fr30_cgen_opval_gr_names_entries[0],
155 
  19,
156 
  0, 0, 0, 0
157 
};
158 
 
159 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
160 
{
161 
  { "cr0", 0, {0, {0}}, 0, 0 },
162 
  { "cr1", 1, {0, {0}}, 0, 0 },
163 
  { "cr2", 2, {0, {0}}, 0, 0 },
164 
  { "cr3", 3, {0, {0}}, 0, 0 },
165 
  { "cr4", 4, {0, {0}}, 0, 0 },
166 
  { "cr5", 5, {0, {0}}, 0, 0 },
167 
  { "cr6", 6, {0, {0}}, 0, 0 },
168 
  { "cr7", 7, {0, {0}}, 0, 0 },
169 
  { "cr8", 8, {0, {0}}, 0, 0 },
170 
  { "cr9", 9, {0, {0}}, 0, 0 },
171 
  { "cr10", 10, {0, {0}}, 0, 0 },
172 
  { "cr11", 11, {0, {0}}, 0, 0 },
173 
  { "cr12", 12, {0, {0}}, 0, 0 },
174 
  { "cr13", 13, {0, {0}}, 0, 0 },
175 
  { "cr14", 14, {0, {0}}, 0, 0 },
176 
  { "cr15", 15, {0, {0}}, 0, 0 }
177 
};
178 
 
179 
CGEN_KEYWORD fr30_cgen_opval_cr_names =
180 
{
181 
  & fr30_cgen_opval_cr_names_entries[0],
182 
  16,
183 
  0, 0, 0, 0
184 
};
185 
 
186 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
187 
{
188 
  { "tbr", 0, {0, {0}}, 0, 0 },
189 
  { "rp", 1, {0, {0}}, 0, 0 },
190 
  { "ssp", 2, {0, {0}}, 0, 0 },
191 
  { "usp", 3, {0, {0}}, 0, 0 },
192 
  { "mdh", 4, {0, {0}}, 0, 0 },
193 
  { "mdl", 5, {0, {0}}, 0, 0 }
194 
};
195 
 
196 
CGEN_KEYWORD fr30_cgen_opval_dr_names =
197 
{
198 
  & fr30_cgen_opval_dr_names_entries[0],
199 
  6,
200 
  0, 0, 0, 0
201 
};
202 
 
203 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
204 
{
205 
  { "ps", 0, {0, {0}}, 0, 0 }
206 
};
207 
 
208 
CGEN_KEYWORD fr30_cgen_opval_h_ps =
209 
{
210 
  & fr30_cgen_opval_h_ps_entries[0],
211 
  1,
212 
  0, 0, 0, 0
213 
};
214 
 
215 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
216 
{
217 
  { "r13", 0, {0, {0}}, 0, 0 }
218 
};
219 
 
220 
CGEN_KEYWORD fr30_cgen_opval_h_r13 =
221 
{
222 
  & fr30_cgen_opval_h_r13_entries[0],
223 
  1,
224 
  0, 0, 0, 0
225 
};
226 
 
227 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
228 
{
229 
  { "r14", 0, {0, {0}}, 0, 0 }
230 
};
231 
 
232 
CGEN_KEYWORD fr30_cgen_opval_h_r14 =
233 
{
234 
  & fr30_cgen_opval_h_r14_entries[0],
235 
  1,
236 
  0, 0, 0, 0
237 
};
238 
 
239 
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
240 
{
241 
  { "r15", 0, {0, {0}}, 0, 0 }
242 
};
243 
 
244 
CGEN_KEYWORD fr30_cgen_opval_h_r15 =
245 
{
246 
  & fr30_cgen_opval_h_r15_entries[0],
247 
  1,
248 
  0, 0, 0, 0
249 
};
250 
 
251 
 
252 
/* The hardware table.  */
253 
 
254 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
255 
#define A(a) (1 << CGEN_HW_##a)
256 
#else
257 
#define A(a) (1 << CGEN_HW_/**/a)
258 
#endif
259 
 
260 
const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
261 
{
262 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
263 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
264 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
265 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
266 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
267 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
268 
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
269 
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
270 
  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
271 
  { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
272 
  { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
273 
  { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
274 
  { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
275 
  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
276 
  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
277 
  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
278 
  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
279 
  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
280 
  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
281 
  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
282 
  { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
283 
  { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
284 
  { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
285 
  { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
286 
  { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
287 
  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
288 
};
289 
 
290 
#undef A
291 
 
292 
 
293 
/* The instruction field table.  */
294 
 
295 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
296 
#define A(a) (1 << CGEN_IFLD_##a)
297 
#else
298 
#define A(a) (1 << CGEN_IFLD_/**/a)
299 
#endif
300 
 
301 
const CGEN_IFLD fr30_cgen_ifld_table[] =
302 
{
303 
  { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
304 
  { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
305 
  { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
306 
  { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
307 
  { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
308 
  { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
309 
  { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
310 
  { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
311 
  { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
312 
  { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
313 
  { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
314 
  { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
315 
  { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
316 
  { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
317 
  { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
318 
  { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
319 
  { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
320 
  { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
321 
  { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
322 
  { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
323 
  { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
324 
  { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
325 
  { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
326 
  { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
327 
  { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
328 
  { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
329 
  { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
330 
  { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
331 
  { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
332 
  { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
333 
  { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
334 
  { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
335 
  { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
336 
  { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
337 
  { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
338 
  { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
339 
  { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
340 
  { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
341 
  { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
342 
  { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
343 
  { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
344 
  { 0, 0, 0, 0, 0, 0, {0, {0}} }
345 
};
346 
 
347 
#undef A
348 
 
349 
 
350 
/* The operand table.  */
351 
 
352 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
353 
#define A(a) (1 << CGEN_OPERAND_##a)
354 
#else
355 
#define A(a) (1 << CGEN_OPERAND_/**/a)
356 
#endif
357 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
358 
#define OPERAND(op) FR30_OPERAND_##op
359 
#else
360 
#define OPERAND(op) FR30_OPERAND_/**/op
361 
#endif
362 
 
363 
const CGEN_OPERAND fr30_cgen_operand_table[] =
364 
{
365 
/* pc: program counter */
366 
  { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
367 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
368 
/* Ri: destination register */
369 
  { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
370 
    { 0, { (1<<MACH_BASE) } }  },
371 
/* Rj: source register */
372 
  { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
373 
    { 0, { (1<<MACH_BASE) } }  },
374 
/* Ric: target register coproc insn */
375 
  { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
376 
    { 0, { (1<<MACH_BASE) } }  },
377 
/* Rjc: source register coproc insn */
378 
  { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
379 
    { 0, { (1<<MACH_BASE) } }  },
380 
/* CRi: coprocessor register */
381 
  { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
382 
    { 0, { (1<<MACH_BASE) } }  },
383 
/* CRj: coprocessor register */
384 
  { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
385 
    { 0, { (1<<MACH_BASE) } }  },
386 
/* Rs1: dedicated register */
387 
  { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
388 
    { 0, { (1<<MACH_BASE) } }  },
389 
/* Rs2: dedicated register */
390 
  { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
391 
    { 0, { (1<<MACH_BASE) } }  },
392 
/* R13: General Register 13 */
393 
  { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
394 
    { 0, { (1<<MACH_BASE) } }  },
395 
/* R14: General Register 14 */
396 
  { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
397 
    { 0, { (1<<MACH_BASE) } }  },
398 
/* R15: General Register 15 */
399 
  { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
400 
    { 0, { (1<<MACH_BASE) } }  },
401 
/* ps: Program Status register */
402 
  { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
403 
    { 0, { (1<<MACH_BASE) } }  },
404 
/* u4: 4  bit unsigned immediate */
405 
  { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
406 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
407 
/* u4c: 4  bit unsigned immediate */
408 
  { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
409 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
410 
/* u8: 8  bit unsigned immediate */
411 
  { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
412 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
413 
/* i8: 8  bit unsigned immediate */
414 
  { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
415 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
416 
/* udisp6: 6  bit unsigned immediate */
417 
  { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
418 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
419 
/* disp8: 8  bit signed   immediate */
420 
  { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
421 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
422 
/* disp9: 9  bit signed   immediate */
423 
  { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
424 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
425 
/* disp10: 10 bit signed   immediate */
426 
  { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
427 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
428 
/* s10: 10 bit signed   immediate */
429 
  { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
430 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
431 
/* u10: 10 bit unsigned immediate */
432 
  { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
433 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
434 
/* i32: 32 bit immediate */
435 
  { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
436 
    { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
437 
/* m4: 4  bit negative immediate */
438 
  { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
439 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
440 
/* i20: 20 bit immediate */
441 
  { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
442 
    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
443 
/* dir8: 8  bit direct address */
444 
  { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
445 
    { 0, { (1<<MACH_BASE) } }  },
446 
/* dir9: 9  bit direct address */
447 
  { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
448 
    { 0, { (1<<MACH_BASE) } }  },
449 
/* dir10: 10 bit direct address */
450 
  { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
451 
    { 0, { (1<<MACH_BASE) } }  },
452 
/* label9: 9  bit pc relative address */
453 
  { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
454 
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
455 
/* label12: 12 bit pc relative address */
456 
  { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
457 
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
458 
/* reglist_low_ld: 8 bit low register mask for ldm */
459 
  { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
460 
    { 0, { (1<<MACH_BASE) } }  },
461 
/* reglist_hi_ld: 8 bit high register mask for ldm */
462 
  { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
463 
    { 0, { (1<<MACH_BASE) } }  },
464 
/* reglist_low_st: 8 bit low register mask for stm */
465 
  { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
466 
    { 0, { (1<<MACH_BASE) } }  },
467 
/* reglist_hi_st: 8 bit high register mask for stm */
468 
  { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
469 
    { 0, { (1<<MACH_BASE) } }  },
470 
/* cc: condition codes */
471 
  { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
472 
    { 0, { (1<<MACH_BASE) } }  },
473 
/* ccc: coprocessor calc */
474 
  { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
475 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
476 
/* nbit: negative   bit */
477 
  { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
478 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
479 
/* vbit: overflow   bit */
480 
  { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
481 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
482 
/* zbit: zero       bit */
483 
  { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
484 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
485 
/* cbit: carry      bit */
486 
  { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
487 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
488 
/* ibit: interrupt  bit */
489 
  { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
490 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
491 
/* sbit: stack      bit */
492 
  { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
493 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
494 
/* tbit: trace trap bit */
495 
  { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
496 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
497 
/* d0bit: division 0 bit */
498 
  { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
499 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
500 
/* d1bit: division 1 bit */
501 
  { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
502 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
503 
/* ccr: condition code bits */
504 
  { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
505 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
506 
/* scr: system condition bits */
507 
  { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
508 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
509 
/* ilm: interrupt level mask */
510 
  { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
511 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
512 
  { 0, 0, 0, 0, 0, {0, {0}} }
513 
};
514 
 
515 
#undef A
516 
 
517 
 
518 
/* The instruction table.  */
519 
 
520 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
521 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
522 
#define A(a) (1 << CGEN_INSN_##a)
523 
#else
524 
#define A(a) (1 << CGEN_INSN_/**/a)
525 
#endif
526 
 
527 
static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
528 
{
529 
  /* Special null first entry.
530 
     A `num' value of zero is thus invalid.
531 
     Also, the special `invalid' insn resides here.  */
532 
  { 0, 0, 0, 0, {0, {0}} },
533 
/* add $Rj,$Ri */
534 
  {
535 
    FR30_INSN_ADD, "add", "add", 16,
536 
    { 0, { (1<<MACH_BASE) } }
537 
  },
538 
/* add $u4,$Ri */
539 
  {
540 
    FR30_INSN_ADDI, "addi", "add", 16,
541 
    { 0, { (1<<MACH_BASE) } }
542 
  },
543 
/* add2 $m4,$Ri */
544 
  {
545 
    FR30_INSN_ADD2, "add2", "add2", 16,
546 
    { 0, { (1<<MACH_BASE) } }
547 
  },
548 
/* addc $Rj,$Ri */
549 
  {
550 
    FR30_INSN_ADDC, "addc", "addc", 16,
551 
    { 0, { (1<<MACH_BASE) } }
552 
  },
553 
/* addn $Rj,$Ri */
554 
  {
555 
    FR30_INSN_ADDN, "addn", "addn", 16,
556 
    { 0, { (1<<MACH_BASE) } }
557 
  },
558 
/* addn $u4,$Ri */
559 
  {
560 
    FR30_INSN_ADDNI, "addni", "addn", 16,
561 
    { 0, { (1<<MACH_BASE) } }
562 
  },
563 
/* addn2 $m4,$Ri */
564 
  {
565 
    FR30_INSN_ADDN2, "addn2", "addn2", 16,
566 
    { 0, { (1<<MACH_BASE) } }
567 
  },
568 
/* sub $Rj,$Ri */
569 
  {
570 
    FR30_INSN_SUB, "sub", "sub", 16,
571 
    { 0, { (1<<MACH_BASE) } }
572 
  },
573 
/* subc $Rj,$Ri */
574 
  {
575 
    FR30_INSN_SUBC, "subc", "subc", 16,
576 
    { 0, { (1<<MACH_BASE) } }
577 
  },
578 
/* subn $Rj,$Ri */
579 
  {
580 
    FR30_INSN_SUBN, "subn", "subn", 16,
581 
    { 0, { (1<<MACH_BASE) } }
582 
  },
583 
/* cmp $Rj,$Ri */
584 
  {
585 
    FR30_INSN_CMP, "cmp", "cmp", 16,
586 
    { 0, { (1<<MACH_BASE) } }
587 
  },
588 
/* cmp $u4,$Ri */
589 
  {
590 
    FR30_INSN_CMPI, "cmpi", "cmp", 16,
591 
    { 0, { (1<<MACH_BASE) } }
592 
  },
593 
/* cmp2 $m4,$Ri */
594 
  {
595 
    FR30_INSN_CMP2, "cmp2", "cmp2", 16,
596 
    { 0, { (1<<MACH_BASE) } }
597 
  },
598 
/* and $Rj,$Ri */
599 
  {
600 
    FR30_INSN_AND, "and", "and", 16,
601 
    { 0, { (1<<MACH_BASE) } }
602 
  },
603 
/* or $Rj,$Ri */
604 
  {
605 
    FR30_INSN_OR, "or", "or", 16,
606 
    { 0, { (1<<MACH_BASE) } }
607 
  },
608 
/* eor $Rj,$Ri */
609 
  {
610 
    FR30_INSN_EOR, "eor", "eor", 16,
611 
    { 0, { (1<<MACH_BASE) } }
612 
  },
613 
/* and $Rj,@$Ri */
614 
  {
615 
    FR30_INSN_ANDM, "andm", "and", 16,
616 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
617 
  },
618 
/* andh $Rj,@$Ri */
619 
  {
620 
    FR30_INSN_ANDH, "andh", "andh", 16,
621 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
622 
  },
623 
/* andb $Rj,@$Ri */
624 
  {
625 
    FR30_INSN_ANDB, "andb", "andb", 16,
626 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
627 
  },
628 
/* or $Rj,@$Ri */
629 
  {
630 
    FR30_INSN_ORM, "orm", "or", 16,
631 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
632 
  },
633 
/* orh $Rj,@$Ri */
634 
  {
635 
    FR30_INSN_ORH, "orh", "orh", 16,
636 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
637 
  },
638 
/* orb $Rj,@$Ri */
639 
  {
640 
    FR30_INSN_ORB, "orb", "orb", 16,
641 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
642 
  },
643 
/* eor $Rj,@$Ri */
644 
  {
645 
    FR30_INSN_EORM, "eorm", "eor", 16,
646 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
647 
  },
648 
/* eorh $Rj,@$Ri */
649 
  {
650 
    FR30_INSN_EORH, "eorh", "eorh", 16,
651 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
652 
  },
653 
/* eorb $Rj,@$Ri */
654 
  {
655 
    FR30_INSN_EORB, "eorb", "eorb", 16,
656 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
657 
  },
658 
/* bandl $u4,@$Ri */
659 
  {
660 
    FR30_INSN_BANDL, "bandl", "bandl", 16,
661 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
662 
  },
663 
/* borl $u4,@$Ri */
664 
  {
665 
    FR30_INSN_BORL, "borl", "borl", 16,
666 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
667 
  },
668 
/* beorl $u4,@$Ri */
669 
  {
670 
    FR30_INSN_BEORL, "beorl", "beorl", 16,
671 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
672 
  },
673 
/* bandh $u4,@$Ri */
674 
  {
675 
    FR30_INSN_BANDH, "bandh", "bandh", 16,
676 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
677 
  },
678 
/* borh $u4,@$Ri */
679 
  {
680 
    FR30_INSN_BORH, "borh", "borh", 16,
681 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
682 
  },
683 
/* beorh $u4,@$Ri */
684 
  {
685 
    FR30_INSN_BEORH, "beorh", "beorh", 16,
686 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
687 
  },
688 
/* btstl $u4,@$Ri */
689 
  {
690 
    FR30_INSN_BTSTL, "btstl", "btstl", 16,
691 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
692 
  },
693 
/* btsth $u4,@$Ri */
694 
  {
695 
    FR30_INSN_BTSTH, "btsth", "btsth", 16,
696 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
697 
  },
698 
/* mul $Rj,$Ri */
699 
  {
700 
    FR30_INSN_MUL, "mul", "mul", 16,
701 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
702 
  },
703 
/* mulu $Rj,$Ri */
704 
  {
705 
    FR30_INSN_MULU, "mulu", "mulu", 16,
706 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
707 
  },
708 
/* mulh $Rj,$Ri */
709 
  {
710 
    FR30_INSN_MULH, "mulh", "mulh", 16,
711 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
712 
  },
713 
/* muluh $Rj,$Ri */
714 
  {
715 
    FR30_INSN_MULUH, "muluh", "muluh", 16,
716 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
717 
  },
718 
/* div0s $Ri */
719 
  {
720 
    FR30_INSN_DIV0S, "div0s", "div0s", 16,
721 
    { 0, { (1<<MACH_BASE) } }
722 
  },
723 
/* div0u $Ri */
724 
  {
725 
    FR30_INSN_DIV0U, "div0u", "div0u", 16,
726 
    { 0, { (1<<MACH_BASE) } }
727 
  },
728 
/* div1 $Ri */
729 
  {
730 
    FR30_INSN_DIV1, "div1", "div1", 16,
731 
    { 0, { (1<<MACH_BASE) } }
732 
  },
733 
/* div2 $Ri */
734 
  {
735 
    FR30_INSN_DIV2, "div2", "div2", 16,
736 
    { 0, { (1<<MACH_BASE) } }
737 
  },
738 
/* div3 */
739 
  {
740 
    FR30_INSN_DIV3, "div3", "div3", 16,
741 
    { 0, { (1<<MACH_BASE) } }
742 
  },
743 
/* div4s */
744 
  {
745 
    FR30_INSN_DIV4S, "div4s", "div4s", 16,
746 
    { 0, { (1<<MACH_BASE) } }
747 
  },
748 
/* lsl $Rj,$Ri */
749 
  {
750 
    FR30_INSN_LSL, "lsl", "lsl", 16,
751 
    { 0, { (1<<MACH_BASE) } }
752 
  },
753 
/* lsl $u4,$Ri */
754 
  {
755 
    FR30_INSN_LSLI, "lsli", "lsl", 16,
756 
    { 0, { (1<<MACH_BASE) } }
757 
  },
758 
/* lsl2 $u4,$Ri */
759 
  {
760 
    FR30_INSN_LSL2, "lsl2", "lsl2", 16,
761 
    { 0, { (1<<MACH_BASE) } }
762 
  },
763 
/* lsr $Rj,$Ri */
764 
  {
765 
    FR30_INSN_LSR, "lsr", "lsr", 16,
766 
    { 0, { (1<<MACH_BASE) } }
767 
  },
768 
/* lsr $u4,$Ri */
769 
  {
770 
    FR30_INSN_LSRI, "lsri", "lsr", 16,
771 
    { 0, { (1<<MACH_BASE) } }
772 
  },
773 
/* lsr2 $u4,$Ri */
774 
  {
775 
    FR30_INSN_LSR2, "lsr2", "lsr2", 16,
776 
    { 0, { (1<<MACH_BASE) } }
777 
  },
778 
/* asr $Rj,$Ri */
779 
  {
780 
    FR30_INSN_ASR, "asr", "asr", 16,
781 
    { 0, { (1<<MACH_BASE) } }
782 
  },
783 
/* asr $u4,$Ri */
784 
  {
785 
    FR30_INSN_ASRI, "asri", "asr", 16,
786 
    { 0, { (1<<MACH_BASE) } }
787 
  },
788 
/* asr2 $u4,$Ri */
789 
  {
790 
    FR30_INSN_ASR2, "asr2", "asr2", 16,
791 
    { 0, { (1<<MACH_BASE) } }
792 
  },
793 
/* ldi:8 $i8,$Ri */
794 
  {
795 
    FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
796 
    { 0, { (1<<MACH_BASE) } }
797 
  },
798 
/* ldi:20 $i20,$Ri */
799 
  {
800 
    FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
801 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
802 
  },
803 
/* ldi:32 $i32,$Ri */
804 
  {
805 
    FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
806 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
807 
  },
808 
/* ld @$Rj,$Ri */
809 
  {
810 
    FR30_INSN_LD, "ld", "ld", 16,
811 
    { 0, { (1<<MACH_BASE) } }
812 
  },
813 
/* lduh @$Rj,$Ri */
814 
  {
815 
    FR30_INSN_LDUH, "lduh", "lduh", 16,
816 
    { 0, { (1<<MACH_BASE) } }
817 
  },
818 
/* ldub @$Rj,$Ri */
819 
  {
820 
    FR30_INSN_LDUB, "ldub", "ldub", 16,
821 
    { 0, { (1<<MACH_BASE) } }
822 
  },
823 
/* ld @($R13,$Rj),$Ri */
824 
  {
825 
    FR30_INSN_LDR13, "ldr13", "ld", 16,
826 
    { 0, { (1<<MACH_BASE) } }
827 
  },
828 
/* lduh @($R13,$Rj),$Ri */
829 
  {
830 
    FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
831 
    { 0, { (1<<MACH_BASE) } }
832 
  },
833 
/* ldub @($R13,$Rj),$Ri */
834 
  {
835 
    FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
836 
    { 0, { (1<<MACH_BASE) } }
837 
  },
838 
/* ld @($R14,$disp10),$Ri */
839 
  {
840 
    FR30_INSN_LDR14, "ldr14", "ld", 16,
841 
    { 0, { (1<<MACH_BASE) } }
842 
  },
843 
/* lduh @($R14,$disp9),$Ri */
844 
  {
845 
    FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
846 
    { 0, { (1<<MACH_BASE) } }
847 
  },
848 
/* ldub @($R14,$disp8),$Ri */
849 
  {
850 
    FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
851 
    { 0, { (1<<MACH_BASE) } }
852 
  },
853 
/* ld @($R15,$udisp6),$Ri */
854 
  {
855 
    FR30_INSN_LDR15, "ldr15", "ld", 16,
856 
    { 0, { (1<<MACH_BASE) } }
857 
  },
858 
/* ld @$R15+,$Ri */
859 
  {
860 
    FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
861 
    { 0, { (1<<MACH_BASE) } }
862 
  },
863 
/* ld @$R15+,$Rs2 */
864 
  {
865 
    FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
866 
    { 0, { (1<<MACH_BASE) } }
867 
  },
868 
/* ld @$R15+,$ps */
869 
  {
870 
    FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
871 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
872 
  },
873 
/* st $Ri,@$Rj */
874 
  {
875 
    FR30_INSN_ST, "st", "st", 16,
876 
    { 0, { (1<<MACH_BASE) } }
877 
  },
878 
/* sth $Ri,@$Rj */
879 
  {
880 
    FR30_INSN_STH, "sth", "sth", 16,
881 
    { 0, { (1<<MACH_BASE) } }
882 
  },
883 
/* stb $Ri,@$Rj */
884 
  {
885 
    FR30_INSN_STB, "stb", "stb", 16,
886 
    { 0, { (1<<MACH_BASE) } }
887 
  },
888 
/* st $Ri,@($R13,$Rj) */
889 
  {
890 
    FR30_INSN_STR13, "str13", "st", 16,
891 
    { 0, { (1<<MACH_BASE) } }
892 
  },
893 
/* sth $Ri,@($R13,$Rj) */
894 
  {
895 
    FR30_INSN_STR13H, "str13h", "sth", 16,
896 
    { 0, { (1<<MACH_BASE) } }
897 
  },
898 
/* stb $Ri,@($R13,$Rj) */
899 
  {
900 
    FR30_INSN_STR13B, "str13b", "stb", 16,
901 
    { 0, { (1<<MACH_BASE) } }
902 
  },
903 
/* st $Ri,@($R14,$disp10) */
904 
  {
905 
    FR30_INSN_STR14, "str14", "st", 16,
906 
    { 0, { (1<<MACH_BASE) } }
907 
  },
908 
/* sth $Ri,@($R14,$disp9) */
909 
  {
910 
    FR30_INSN_STR14H, "str14h", "sth", 16,
911 
    { 0, { (1<<MACH_BASE) } }
912 
  },
913 
/* stb $Ri,@($R14,$disp8) */
914 
  {
915 
    FR30_INSN_STR14B, "str14b", "stb", 16,
916 
    { 0, { (1<<MACH_BASE) } }
917 
  },
918 
/* st $Ri,@($R15,$udisp6) */
919 
  {
920 
    FR30_INSN_STR15, "str15", "st", 16,
921 
    { 0, { (1<<MACH_BASE) } }
922 
  },
923 
/* st $Ri,@-$R15 */
924 
  {
925 
    FR30_INSN_STR15GR, "str15gr", "st", 16,
926 
    { 0, { (1<<MACH_BASE) } }
927 
  },
928 
/* st $Rs2,@-$R15 */
929 
  {
930 
    FR30_INSN_STR15DR, "str15dr", "st", 16,
931 
    { 0, { (1<<MACH_BASE) } }
932 
  },
933 
/* st $ps,@-$R15 */
934 
  {
935 
    FR30_INSN_STR15PS, "str15ps", "st", 16,
936 
    { 0, { (1<<MACH_BASE) } }
937 
  },
938 
/* mov $Rj,$Ri */
939 
  {
940 
    FR30_INSN_MOV, "mov", "mov", 16,
941 
    { 0, { (1<<MACH_BASE) } }
942 
  },
943 
/* mov $Rs1,$Ri */
944 
  {
945 
    FR30_INSN_MOVDR, "movdr", "mov", 16,
946 
    { 0, { (1<<MACH_BASE) } }
947 
  },
948 
/* mov $ps,$Ri */
949 
  {
950 
    FR30_INSN_MOVPS, "movps", "mov", 16,
951 
    { 0, { (1<<MACH_BASE) } }
952 
  },
953 
/* mov $Ri,$Rs1 */
954 
  {
955 
    FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
956 
    { 0, { (1<<MACH_BASE) } }
957 
  },
958 
/* mov $Ri,$ps */
959 
  {
960 
    FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
961 
    { 0, { (1<<MACH_BASE) } }
962 
  },
963 
/* jmp @$Ri */
964 
  {
965 
    FR30_INSN_JMP, "jmp", "jmp", 16,
966 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
967 
  },
968 
/* jmp:d @$Ri */
969 
  {
970 
    FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
971 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
972 
  },
973 
/* call @$Ri */
974 
  {
975 
    FR30_INSN_CALLR, "callr", "call", 16,
976 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
977 
  },
978 
/* call:d @$Ri */
979 
  {
980 
    FR30_INSN_CALLRD, "callrd", "call:d", 16,
981 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
982 
  },
983 
/* call $label12 */
984 
  {
985 
    FR30_INSN_CALL, "call", "call", 16,
986 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
987 
  },
988 
/* call:d $label12 */
989 
  {
990 
    FR30_INSN_CALLD, "calld", "call:d", 16,
991 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
992 
  },
993 
/* ret */
994 
  {
995 
    FR30_INSN_RET, "ret", "ret", 16,
996 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
997 
  },
998 
/* ret:d */
999 
  {
1000 
    FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1001 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1002 
  },
1003 
/* int $u8 */
1004 
  {
1005 
    FR30_INSN_INT, "int", "int", 16,
1006 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1007 
  },
1008 
/* inte */
1009 
  {
1010 
    FR30_INSN_INTE, "inte", "inte", 16,
1011 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1012 
  },
1013 
/* reti */
1014 
  {
1015 
    FR30_INSN_RETI, "reti", "reti", 16,
1016 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1017 
  },
1018 
/* bra:d $label9 */
1019 
  {
1020 
    FR30_INSN_BRAD, "brad", "bra:d", 16,
1021 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1022 
  },
1023 
/* bra $label9 */
1024 
  {
1025 
    FR30_INSN_BRA, "bra", "bra", 16,
1026 
    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1027 
  },
1028 
/* bno:d $label9 */
1029 
  {
1030 
    FR30_INSN_BNOD, "bnod", "bno:d", 16,
1031 
    { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1032 
  },
1033 
/* bno $label9 */
1034 
  {
1035 
    FR30_INSN_BNO, "bno", "bno", 16,
1036 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1037 
  },
1038 
/* beq:d $label9 */
1039 
  {
1040 
    FR30_INSN_BEQD, "beqd", "beq:d", 16,
1041 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1042 
  },
1043 
/* beq $label9 */
1044 
  {
1045 
    FR30_INSN_BEQ, "beq", "beq", 16,
1046 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1047 
  },
1048 
/* bne:d $label9 */
1049 
  {
1050 
    FR30_INSN_BNED, "bned", "bne:d", 16,
1051 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1052 
  },
1053 
/* bne $label9 */
1054 
  {
1055 
    FR30_INSN_BNE, "bne", "bne", 16,
1056 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1057 
  },
1058 
/* bc:d $label9 */
1059 
  {
1060 
    FR30_INSN_BCD, "bcd", "bc:d", 16,
1061 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1062 
  },
1063 
/* bc $label9 */
1064 
  {
1065 
    FR30_INSN_BC, "bc", "bc", 16,
1066 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1067 
  },
1068 
/* bnc:d $label9 */
1069 
  {
1070 
    FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1071 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1072 
  },
1073 
/* bnc $label9 */
1074 
  {
1075 
    FR30_INSN_BNC, "bnc", "bnc", 16,
1076 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1077 
  },
1078 
/* bn:d $label9 */
1079 
  {
1080 
    FR30_INSN_BND, "bnd", "bn:d", 16,
1081 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1082 
  },
1083 
/* bn $label9 */
1084 
  {
1085 
    FR30_INSN_BN, "bn", "bn", 16,
1086 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1087 
  },
1088 
/* bp:d $label9 */
1089 
  {
1090 
    FR30_INSN_BPD, "bpd", "bp:d", 16,
1091 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1092 
  },
1093 
/* bp $label9 */
1094 
  {
1095 
    FR30_INSN_BP, "bp", "bp", 16,
1096 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1097 
  },
1098 
/* bv:d $label9 */
1099 
  {
1100 
    FR30_INSN_BVD, "bvd", "bv:d", 16,
1101 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1102 
  },
1103 
/* bv $label9 */
1104 
  {
1105 
    FR30_INSN_BV, "bv", "bv", 16,
1106 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1107 
  },
1108 
/* bnv:d $label9 */
1109 
  {
1110 
    FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1111 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1112 
  },
1113 
/* bnv $label9 */
1114 
  {
1115 
    FR30_INSN_BNV, "bnv", "bnv", 16,
1116 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1117 
  },
1118 
/* blt:d $label9 */
1119 
  {
1120 
    FR30_INSN_BLTD, "bltd", "blt:d", 16,
1121 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1122 
  },
1123 
/* blt $label9 */
1124 
  {
1125 
    FR30_INSN_BLT, "blt", "blt", 16,
1126 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1127 
  },
1128 
/* bge:d $label9 */
1129 
  {
1130 
    FR30_INSN_BGED, "bged", "bge:d", 16,
1131 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1132 
  },
1133 
/* bge $label9 */
1134 
  {
1135 
    FR30_INSN_BGE, "bge", "bge", 16,
1136 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1137 
  },
1138 
/* ble:d $label9 */
1139 
  {
1140 
    FR30_INSN_BLED, "bled", "ble:d", 16,
1141 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1142 
  },
1143 
/* ble $label9 */
1144 
  {
1145 
    FR30_INSN_BLE, "ble", "ble", 16,
1146 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1147 
  },
1148 
/* bgt:d $label9 */
1149 
  {
1150 
    FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1151 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1152 
  },
1153 
/* bgt $label9 */
1154 
  {
1155 
    FR30_INSN_BGT, "bgt", "bgt", 16,
1156 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1157 
  },
1158 
/* bls:d $label9 */
1159 
  {
1160 
    FR30_INSN_BLSD, "blsd", "bls:d", 16,
1161 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1162 
  },
1163 
/* bls $label9 */
1164 
  {
1165 
    FR30_INSN_BLS, "bls", "bls", 16,
1166 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1167 
  },
1168 
/* bhi:d $label9 */
1169 
  {
1170 
    FR30_INSN_BHID, "bhid", "bhi:d", 16,
1171 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1172 
  },
1173 
/* bhi $label9 */
1174 
  {
1175 
    FR30_INSN_BHI, "bhi", "bhi", 16,
1176 
    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1177 
  },
1178 
/* dmov $R13,@$dir10 */
1179 
  {
1180 
    FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1181 
    { 0, { (1<<MACH_BASE) } }
1182 
  },
1183 
/* dmovh $R13,@$dir9 */
1184 
  {
1185 
    FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1186 
    { 0, { (1<<MACH_BASE) } }
1187 
  },
1188 
/* dmovb $R13,@$dir8 */
1189 
  {
1190 
    FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1191 
    { 0, { (1<<MACH_BASE) } }
1192 
  },
1193 
/* dmov @$R13+,@$dir10 */
1194 
  {
1195 
    FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1196 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1197 
  },
1198 
/* dmovh @$R13+,@$dir9 */
1199 
  {
1200 
    FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1201 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1202 
  },
1203 
/* dmovb @$R13+,@$dir8 */
1204 
  {
1205 
    FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1206 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1207 
  },
1208 
/* dmov @$R15+,@$dir10 */
1209 
  {
1210 
    FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1211 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1212 
  },
1213 
/* dmov @$dir10,$R13 */
1214 
  {
1215 
    FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1216 
    { 0, { (1<<MACH_BASE) } }
1217 
  },
1218 
/* dmovh @$dir9,$R13 */
1219 
  {
1220 
    FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1221 
    { 0, { (1<<MACH_BASE) } }
1222 
  },
1223 
/* dmovb @$dir8,$R13 */
1224 
  {
1225 
    FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1226 
    { 0, { (1<<MACH_BASE) } }
1227 
  },
1228 
/* dmov @$dir10,@$R13+ */
1229 
  {
1230 
    FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1231 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1232 
  },
1233 
/* dmovh @$dir9,@$R13+ */
1234 
  {
1235 
    FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1236 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1237 
  },
1238 
/* dmovb @$dir8,@$R13+ */
1239 
  {
1240 
    FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1241 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1242 
  },
1243 
/* dmov @$dir10,@-$R15 */
1244 
  {
1245 
    FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1246 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1247 
  },
1248 
/* ldres @$Ri+,$u4 */
1249 
  {
1250 
    FR30_INSN_LDRES, "ldres", "ldres", 16,
1251 
    { 0, { (1<<MACH_BASE) } }
1252 
  },
1253 
/* stres $u4,@$Ri+ */
1254 
  {
1255 
    FR30_INSN_STRES, "stres", "stres", 16,
1256 
    { 0, { (1<<MACH_BASE) } }
1257 
  },
1258 
/* copop $u4c,$ccc,$CRj,$CRi */
1259 
  {
1260 
    FR30_INSN_COPOP, "copop", "copop", 32,
1261 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1262 
  },
1263 
/* copld $u4c,$ccc,$Rjc,$CRi */
1264 
  {
1265 
    FR30_INSN_COPLD, "copld", "copld", 32,
1266 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1267 
  },
1268 
/* copst $u4c,$ccc,$CRj,$Ric */
1269 
  {
1270 
    FR30_INSN_COPST, "copst", "copst", 32,
1271 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1272 
  },
1273 
/* copsv $u4c,$ccc,$CRj,$Ric */
1274 
  {
1275 
    FR30_INSN_COPSV, "copsv", "copsv", 32,
1276 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1277 
  },
1278 
/* nop */
1279 
  {
1280 
    FR30_INSN_NOP, "nop", "nop", 16,
1281 
    { 0, { (1<<MACH_BASE) } }
1282 
  },
1283 
/* andccr $u8 */
1284 
  {
1285 
    FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1286 
    { 0, { (1<<MACH_BASE) } }
1287 
  },
1288 
/* orccr $u8 */
1289 
  {
1290 
    FR30_INSN_ORCCR, "orccr", "orccr", 16,
1291 
    { 0, { (1<<MACH_BASE) } }
1292 
  },
1293 
/* stilm $u8 */
1294 
  {
1295 
    FR30_INSN_STILM, "stilm", "stilm", 16,
1296 
    { 0, { (1<<MACH_BASE) } }
1297 
  },
1298 
/* addsp $s10 */
1299 
  {
1300 
    FR30_INSN_ADDSP, "addsp", "addsp", 16,
1301 
    { 0, { (1<<MACH_BASE) } }
1302 
  },
1303 
/* extsb $Ri */
1304 
  {
1305 
    FR30_INSN_EXTSB, "extsb", "extsb", 16,
1306 
    { 0, { (1<<MACH_BASE) } }
1307 
  },
1308 
/* extub $Ri */
1309 
  {
1310 
    FR30_INSN_EXTUB, "extub", "extub", 16,
1311 
    { 0, { (1<<MACH_BASE) } }
1312 
  },
1313 
/* extsh $Ri */
1314 
  {
1315 
    FR30_INSN_EXTSH, "extsh", "extsh", 16,
1316 
    { 0, { (1<<MACH_BASE) } }
1317 
  },
1318 
/* extuh $Ri */
1319 
  {
1320 
    FR30_INSN_EXTUH, "extuh", "extuh", 16,
1321 
    { 0, { (1<<MACH_BASE) } }
1322 
  },
1323 
/* ldm0 ($reglist_low_ld) */
1324 
  {
1325 
    FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1326 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1327 
  },
1328 
/* ldm1 ($reglist_hi_ld) */
1329 
  {
1330 
    FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1331 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1332 
  },
1333 
/* stm0 ($reglist_low_st) */
1334 
  {
1335 
    FR30_INSN_STM0, "stm0", "stm0", 16,
1336 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1337 
  },
1338 
/* stm1 ($reglist_hi_st) */
1339 
  {
1340 
    FR30_INSN_STM1, "stm1", "stm1", 16,
1341 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1342 
  },
1343 
/* enter $u10 */
1344 
  {
1345 
    FR30_INSN_ENTER, "enter", "enter", 16,
1346 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1347 
  },
1348 
/* leave */
1349 
  {
1350 
    FR30_INSN_LEAVE, "leave", "leave", 16,
1351 
    { 0, { (1<<MACH_BASE) } }
1352 
  },
1353 
/* xchb @$Rj,$Ri */
1354 
  {
1355 
    FR30_INSN_XCHB, "xchb", "xchb", 16,
1356 
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1357 
  },
1358 
};
1359 
 
1360 
#undef OP
1361 
#undef A
1362 
 
1363 
/* Initialize anything needed to be done once, before any cpu_open call.  */
1364 
 
1365 
static void
1366 
init_tables ()
1367 
{
1368 
}
1369 
 
1370 
/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
1371 
 
1372 
static const CGEN_MACH *
1373 
lookup_mach_via_bfd_name (table, name)
1374 
     const CGEN_MACH *table;
1375 
     const char *name;
1376 
{
1377 
  while (table->name)
1378 
    {
1379 
      if (strcmp (name, table->bfd_name) == 0)
1380 
        return table;
1381 
      ++table;
1382 
    }
1383 
  abort ();
1384 
}
1385 
 
1386 
/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1387 
 
1388 
static void
1389 
build_hw_table (cd)
1390 
     CGEN_CPU_TABLE *cd;
1391 
{
1392 
  int i;
1393 
  int machs = cd->machs;
1394 
  const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1395 
  /* MAX_HW is only an upper bound on the number of selected entries.
1396 
     However each entry is indexed by it's enum so there can be holes in
1397 
     the table.  */
1398 
  const CGEN_HW_ENTRY **selected =
1399 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1400 
 
1401 
  cd->hw_table.init_entries = init;
1402 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1403 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1404 
  /* ??? For now we just use machs to determine which ones we want.  */
1405 
  for (i = 0; init[i].name != NULL; ++i)
1406 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1407 
        & machs)
1408 
      selected[init[i].type] = &init[i];
1409 
  cd->hw_table.entries = selected;
1410 
  cd->hw_table.num_entries = MAX_HW;
1411 
}
1412 
 
1413 
/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1414 
 
1415 
static void
1416 
build_ifield_table (cd)
1417 
     CGEN_CPU_TABLE *cd;
1418 
{
1419 
  cd->ifld_table = & fr30_cgen_ifld_table[0];
1420 
}
1421 
 
1422 
/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1423 
 
1424 
static void
1425 
build_operand_table (cd)
1426 
     CGEN_CPU_TABLE *cd;
1427 
{
1428 
  int i;
1429 
  int machs = cd->machs;
1430 
  const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1431 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1432 
     However each entry is indexed by it's enum so there can be holes in
1433 
     the table.  */
1434 
  const CGEN_OPERAND **selected =
1435 
    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1436 
 
1437 
  cd->operand_table.init_entries = init;
1438 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1439 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1440 
  /* ??? For now we just use mach to determine which ones we want.  */
1441 
  for (i = 0; init[i].name != NULL; ++i)
1442 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1443 
        & machs)
1444 
      selected[init[i].type] = &init[i];
1445 
  cd->operand_table.entries = selected;
1446 
  cd->operand_table.num_entries = MAX_OPERANDS;
1447 
}
1448 
 
1449 
/* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1450 
   ??? This could leave out insns not supported by the specified mach/isa,
1451 
   but that would cause errors like "foo only supported by bar" to become
1452 
   "unknown insn", so for now we include all insns and require the app to
1453 
   do the checking later.
1454 
   ??? On the other hand, parsing of such insns may require their hardware or
1455 
   operand elements to be in the table [which they mightn't be].  */
1456 
 
1457 
static void
1458 
build_insn_table (cd)
1459 
     CGEN_CPU_TABLE *cd;
1460 
{
1461 
  int i;
1462 
  const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1463 
  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1464 
 
1465 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1466 
  for (i = 0; i < MAX_INSNS; ++i)
1467 
    insns[i].base = &ib[i];
1468 
  cd->insn_table.init_entries = insns;
1469 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1470 
  cd->insn_table.num_init_entries = MAX_INSNS;
1471 
}
1472 
 
1473 
/* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
1474 
 
1475 
static void
1476 
fr30_cgen_rebuild_tables (cd)
1477 
     CGEN_CPU_TABLE *cd;
1478 
{
1479 
  int i,n_isas;
1480 
  unsigned int isas = cd->isas;
1481 
#if 0
1482 
  unsigned int machs = cd->machs;
1483 
#endif
1484 
 
1485 
  cd->int_insn_p = CGEN_INT_INSN_P;
1486 
 
1487 
  /* Data derived from the isa spec.  */
1488 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1489 
  cd->default_insn_bitsize = UNSET;
1490 
  cd->base_insn_bitsize = UNSET;
1491 
  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1492 
  cd->max_insn_bitsize = 0;
1493 
  for (i = 0; i < MAX_ISAS; ++i)
1494 
    if (((1 << i) & isas) != 0)
1495 
      {
1496 
        const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1497 
 
1498 
        /* Default insn sizes of all selected isas must be equal or we set
1499 
           the result to 0, meaning "unknown".  */
1500 
        if (cd->default_insn_bitsize == UNSET)
1501 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1502 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1503 
          ; /* this is ok */
1504 
        else
1505 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1506 
 
1507 
        /* Base insn sizes of all selected isas must be equal or we set
1508 
           the result to 0, meaning "unknown".  */
1509 
        if (cd->base_insn_bitsize == UNSET)
1510 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1511 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1512 
          ; /* this is ok */
1513 
        else
1514 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1515 
 
1516 
        /* Set min,max insn sizes.  */
1517 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1518 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1519 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1520 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1521 
 
1522 
        ++n_isas;
1523 
      }
1524 
 
1525 
#if 0 /* Does nothing?? */
1526 
  /* Data derived from the mach spec.  */
1527 
  for (i = 0; i < MAX_MACHS; ++i)
1528 
    if (((1 << i) & machs) != 0)
1529 
      {
1530 
        const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1531 
 
1532 
        ++n_machs;
1533 
      }
1534 
#endif
1535 
 
1536 
  /* Determine which hw elements are used by MACH.  */
1537 
  build_hw_table (cd);
1538 
 
1539 
  /* Build the ifield table.  */
1540 
  build_ifield_table (cd);
1541 
 
1542 
  /* Determine which operands are used by MACH/ISA.  */
1543 
  build_operand_table (cd);
1544 
 
1545 
  /* Build the instruction table.  */
1546 
  build_insn_table (cd);
1547 
}
1548 
 
1549 
/* Initialize a cpu table and return a descriptor.
1550 
   It's much like opening a file, and must be the first function called.
1551 
   The arguments are a set of (type/value) pairs, terminated with
1552 
   CGEN_CPU_OPEN_END.
1553 
 
1554 
   Currently supported values:
1555 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1556 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1557 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1558 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1559 
   CGEN_CPU_OPEN_END:     terminates arguments
1560 
 
1561 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1562 
   precluded.
1563 
 
1564 
   ??? We only support ISO C stdargs here, not K&R.
1565 
   Laziness, plus experiment to see if anything requires K&R - eventually
1566 
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1567 
 
1568 
CGEN_CPU_DESC
1569 
fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1570 
{
1571 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1572 
  static int init_p;
1573 
  unsigned int isas = 0;  /* 0 = "unspecified" */
1574 
  unsigned int machs = 0; /* 0 = "unspecified" */
1575 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1576 
  va_list ap;
1577 
 
1578 
  if (! init_p)
1579 
    {
1580 
      init_tables ();
1581 
      init_p = 1;
1582 
    }
1583 
 
1584 
  memset (cd, 0, sizeof (*cd));
1585 
 
1586 
  va_start (ap, arg_type);
1587 
  while (arg_type != CGEN_CPU_OPEN_END)
1588 
    {
1589 
      switch (arg_type)
1590 
        {
1591 
        case CGEN_CPU_OPEN_ISAS :
1592 
          isas = va_arg (ap, unsigned int);
1593 
          break;
1594 
        case CGEN_CPU_OPEN_MACHS :
1595 
          machs = va_arg (ap, unsigned int);
1596 
          break;
1597 
        case CGEN_CPU_OPEN_BFDMACH :
1598 
          {
1599 
            const char *name = va_arg (ap, const char *);
1600 
            const CGEN_MACH *mach =
1601 
              lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1602 
 
1603 
            machs |= 1 << mach->num;
1604 
            break;
1605 
          }
1606 
        case CGEN_CPU_OPEN_ENDIAN :
1607 
          endian = va_arg (ap, enum cgen_endian);
1608 
          break;
1609 
        default :
1610 
          fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1611 
                   arg_type);
1612 
          abort (); /* ??? return NULL? */
1613 
        }
1614 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1615 
    }
1616 
  va_end (ap);
1617 
 
1618 
  /* mach unspecified means "all" */
1619 
  if (machs == 0)
1620 
    machs = (1 << MAX_MACHS) - 1;
1621 
  /* base mach is always selected */
1622 
  machs |= 1;
1623 
  /* isa unspecified means "all" */
1624 
  if (isas == 0)
1625 
    isas = (1 << MAX_ISAS) - 1;
1626 
  if (endian == CGEN_ENDIAN_UNKNOWN)
1627 
    {
1628 
      /* ??? If target has only one, could have a default.  */
1629 
      fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1630 
      abort ();
1631 
    }
1632 
 
1633 
  cd->isas = isas;
1634 
  cd->machs = machs;
1635 
  cd->endian = endian;
1636 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
1637 
     The worry here is where both data and insn endian can be independently
1638 
     chosen, in which case this function will need another argument.
1639 
     Actually, will want to allow for more arguments in the future anyway.  */
1640 
  cd->insn_endian = endian;
1641 
 
1642 
  /* Table (re)builder.  */
1643 
  cd->rebuild_tables = fr30_cgen_rebuild_tables;
1644 
  fr30_cgen_rebuild_tables (cd);
1645 
 
1646 
  /* Default to not allowing signed overflow.  */
1647 
  cd->signed_overflow_ok_p = 0;
1648 
 
1649 
  return (CGEN_CPU_DESC) cd;
1650 
}
1651 
 
1652 
/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1653 
   MACH_NAME is the bfd name of the mach.  */
1654 
 
1655 
CGEN_CPU_DESC
1656 
fr30_cgen_cpu_open_1 (mach_name, endian)
1657 
     const char *mach_name;
1658 
     enum cgen_endian endian;
1659 
{
1660 
  return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1661 
                               CGEN_CPU_OPEN_ENDIAN, endian,
1662 
                               CGEN_CPU_OPEN_END);
1663 
}
1664 
 
1665 
/* Close a cpu table.
1666 
   ??? This can live in a machine independent file, but there's currently
1667 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1668 
   place as some simulator ports use this but they don't use libopcodes.  */
1669 
 
1670 
void
1671 
fr30_cgen_cpu_close (cd)
1672 
     CGEN_CPU_DESC cd;
1673 
{
1674 
  if (cd->insn_table.init_entries)
1675 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
1676 
  if (cd->hw_table.entries)
1677 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1678 
  free (cd);
1679 
}
1680 
 

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