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markom |
/* Instruction building/extraction support for fr30. -*- C -*-
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THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
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- the resultant file is machine generated, cgen-ibld.in isn't
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Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <ctype.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "fr30-desc.h"
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#include "fr30-opc.h"
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#include "opintl.h"
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#undef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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static const char * insert_normal
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PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
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static const char * insert_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
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CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
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static int extract_normal
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PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, bfd_vma, long *));
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static int extract_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
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static void put_insn_int_value
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PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
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/* Operand insertion. */
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#if ! CGEN_INT_INSN_P
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/* Subroutine of insert_normal. */
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static CGEN_INLINE void
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insert_1 (cd, value, start, length, word_length, bufp)
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CGEN_CPU_DESC cd;
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unsigned long value;
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int start,length,word_length;
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unsigned char *bufp;
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{
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unsigned long x,mask;
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int shift;
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int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
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x = bfd_get_bits (bufp, word_length, big_p);
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/* Written this way to avoid undefined behaviour. */
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mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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else
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shift = (word_length - (start + length));
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x = (x & ~(mask << shift)) | ((value & mask) << shift);
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bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
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}
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#endif /* ! CGEN_INT_INSN_P */
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/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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START is the starting bit number in the word, architecture origin.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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The result is an error message or NULL if success. */
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/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* ??? This doesn't handle bfd_vma's. Create another function when
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necessary. */
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static const char *
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insert_normal (cd, value, attrs, word_offset, start, length, word_length,
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total_length, buffer)
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CGEN_CPU_DESC cd;
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long value;
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unsigned int attrs;
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unsigned int word_offset, start, length, word_length, total_length;
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CGEN_INSN_BYTES_PTR buffer;
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{
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static char errbuf[100];
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/* Written this way to avoid undefined behaviour. */
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unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
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/* If LENGTH is zero, this operand doesn't contribute to the value. */
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if (length == 0)
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return NULL;
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#if 0
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if (CGEN_INT_INSN_P
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&& word_offset != 0)
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abort ();
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#endif
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if (word_length > 32)
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abort ();
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/* For architectures with insns smaller than the base-insn-bitsize,
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word_length may be too big. */
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if (cd->min_insn_bitsize < cd->base_insn_bitsize)
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{
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if (word_offset == 0
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&& word_length > total_length)
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word_length = total_length;
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}
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/* Ensure VALUE will fit. */
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if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
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{
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unsigned long maxval = mask;
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if ((unsigned long) value > maxval)
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{
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/* xgettext:c-format */
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sprintf (errbuf,
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_("operand out of range (%lu not between 0 and %lu)"),
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value, maxval);
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return errbuf;
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}
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}
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else
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{
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if (! cgen_signed_overflow_ok_p (cd))
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{
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long minval = - (1L << (length - 1));
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long maxval = (1L << (length - 1)) - 1;
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if (value < minval || value > maxval)
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{
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sprintf
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/* xgettext:c-format */
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(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
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value, minval, maxval);
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return errbuf;
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}
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}
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}
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#if CGEN_INT_INSN_P
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{
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int shift;
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if (CGEN_INSN_LSB0_P)
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shift = (word_offset + start + 1) - length;
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else
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shift = total_length - (word_offset + start + length);
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*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
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}
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#else /* ! CGEN_INT_INSN_P */
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{
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unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
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insert_1 (cd, value, start, length, word_length, bufp);
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}
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#endif /* ! CGEN_INT_INSN_P */
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return NULL;
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}
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/* Default insn builder (insert handler).
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The instruction is recorded in CGEN_INT_INSN_P byte order
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(meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
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recorded in host byte order, otherwise BUFFER is an array of bytes and the
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value is recorded in target byte order).
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The result is an error message or NULL if success. */
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static const char *
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insert_insn_normal (cd, insn, fields, buffer, pc)
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CGEN_CPU_DESC cd;
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const CGEN_INSN * insn;
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CGEN_FIELDS * fields;
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CGEN_INSN_BYTES_PTR buffer;
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bfd_vma pc;
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{
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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unsigned long value;
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const CGEN_SYNTAX_CHAR_TYPE * syn;
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CGEN_INIT_INSERT (cd);
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value = CGEN_INSN_BASE_VALUE (insn);
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/* If we're recording insns as numbers (rather than a string of bytes),
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target byte order handling is deferred until later. */
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#if CGEN_INT_INSN_P
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put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
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CGEN_FIELDS_BITSIZE (fields), value);
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#else
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cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
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CGEN_FIELDS_BITSIZE (fields)),
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value);
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#endif /* ! CGEN_INT_INSN_P */
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/* ??? It would be better to scan the format's fields.
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Still need to be able to insert a value based on the operand though;
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e.g. storing a branch displacement that got resolved later.
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Needs more thought first. */
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for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
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{
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const char *errmsg;
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if (CGEN_SYNTAX_CHAR_P (* syn))
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continue;
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errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
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fields, buffer, pc);
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if (errmsg)
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return errmsg;
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}
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return NULL;
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}
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/* Cover function to store an insn value into an integral insn. Must go here
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because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
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static void
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put_insn_int_value (cd, buf, length, insn_length, value)
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CGEN_CPU_DESC cd;
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CGEN_INSN_BYTES_PTR buf;
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int length;
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int insn_length;
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CGEN_INSN_INT value;
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{
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/* For architectures with insns smaller than the base-insn-bitsize,
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length may be too big. */
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if (length > insn_length)
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*buf = value;
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else
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279 |
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{
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280 |
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int shift = insn_length - length;
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281 |
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/* Written this way to avoid undefined behaviour. */
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CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
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*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
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}
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285 |
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}
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286 |
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287 |
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/* Operand extraction. */
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288 |
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289 |
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#if ! CGEN_INT_INSN_P
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290 |
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291 |
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/* Subroutine of extract_normal.
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Ensure sufficient bytes are cached in EX_INFO.
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OFFSET is the offset in bytes from the start of the insn of the value.
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BYTES is the length of the needed value.
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Returns 1 for success, 0 for failure. */
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296 |
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297 |
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static CGEN_INLINE int
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298 |
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fill_cache (cd, ex_info, offset, bytes, pc)
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CGEN_CPU_DESC cd;
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CGEN_EXTRACT_INFO *ex_info;
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301 |
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int offset, bytes;
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302 |
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bfd_vma pc;
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303 |
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{
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304 |
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/* It's doubtful that the middle part has already been fetched so
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we don't optimize that case. kiss. */
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306 |
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int mask;
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307 |
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disassemble_info *info = (disassemble_info *) ex_info->dis_info;
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308 |
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309 |
|
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/* First do a quick check. */
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310 |
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mask = (1 << bytes) - 1;
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if (((ex_info->valid >> offset) & mask) == mask)
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return 1;
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313 |
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|
314 |
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/* Search for the first byte we need to read. */
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315 |
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for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
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316 |
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if (! (mask & ex_info->valid))
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break;
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318 |
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319 |
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if (bytes)
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320 |
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{
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321 |
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int status;
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322 |
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323 |
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pc += offset;
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324 |
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status = (*info->read_memory_func)
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(pc, ex_info->insn_bytes + offset, bytes, info);
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326 |
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327 |
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if (status != 0)
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{
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329 |
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(*info->memory_error_func) (status, pc, info);
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330 |
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return 0;
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}
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332 |
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|
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ex_info->valid |= ((1 << bytes) - 1) << offset;
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}
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335 |
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336 |
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return 1;
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}
|
338 |
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339 |
|
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/* Subroutine of extract_normal. */
|
340 |
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|
341 |
|
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static CGEN_INLINE long
|
342 |
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extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
|
343 |
|
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CGEN_CPU_DESC cd;
|
344 |
|
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CGEN_EXTRACT_INFO *ex_info;
|
345 |
|
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int start,length,word_length;
|
346 |
|
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unsigned char *bufp;
|
347 |
|
|
bfd_vma pc;
|
348 |
|
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{
|
349 |
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unsigned long x;
|
350 |
|
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int shift;
|
351 |
|
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int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
|
352 |
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353 |
|
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x = bfd_get_bits (bufp, word_length, big_p);
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354 |
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355 |
|
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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357 |
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else
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358 |
|
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shift = (word_length - (start + length));
|
359 |
|
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return x >> shift;
|
360 |
|
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}
|
361 |
|
|
|
362 |
|
|
#endif /* ! CGEN_INT_INSN_P */
|
363 |
|
|
|
364 |
|
|
/* Default extraction routine.
|
365 |
|
|
|
366 |
|
|
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
|
367 |
|
|
or sometimes less for cases like the m32r where the base insn size is 32
|
368 |
|
|
but some insns are 16 bits.
|
369 |
|
|
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
|
370 |
|
|
but for generality we take a bitmask of all of them.
|
371 |
|
|
WORD_OFFSET is the offset in bits from the start of the insn of the value.
|
372 |
|
|
WORD_LENGTH is the length of the word in bits in which the value resides.
|
373 |
|
|
START is the starting bit number in the word, architecture origin.
|
374 |
|
|
LENGTH is the length of VALUE in bits.
|
375 |
|
|
TOTAL_LENGTH is the total length of the insn in bits.
|
376 |
|
|
|
377 |
|
|
Returns 1 for success, 0 for failure. */
|
378 |
|
|
|
379 |
|
|
/* ??? The return code isn't properly used. wip. */
|
380 |
|
|
|
381 |
|
|
/* ??? This doesn't handle bfd_vma's. Create another function when
|
382 |
|
|
necessary. */
|
383 |
|
|
|
384 |
|
|
static int
|
385 |
|
|
extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
386 |
|
|
word_length, total_length, pc, valuep)
|
387 |
|
|
CGEN_CPU_DESC cd;
|
388 |
|
|
#if ! CGEN_INT_INSN_P
|
389 |
|
|
CGEN_EXTRACT_INFO *ex_info;
|
390 |
|
|
#else
|
391 |
|
|
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
|
392 |
|
|
#endif
|
393 |
|
|
CGEN_INSN_INT insn_value;
|
394 |
|
|
unsigned int attrs;
|
395 |
|
|
unsigned int word_offset, start, length, word_length, total_length;
|
396 |
|
|
#if ! CGEN_INT_INSN_P
|
397 |
|
|
bfd_vma pc;
|
398 |
|
|
#else
|
399 |
|
|
bfd_vma pc ATTRIBUTE_UNUSED;
|
400 |
|
|
#endif
|
401 |
|
|
long *valuep;
|
402 |
|
|
{
|
403 |
|
|
CGEN_INSN_INT value, mask;
|
404 |
|
|
|
405 |
|
|
/* If LENGTH is zero, this operand doesn't contribute to the value
|
406 |
|
|
so give it a standard value of zero. */
|
407 |
|
|
if (length == 0)
|
408 |
|
|
{
|
409 |
|
|
*valuep = 0;
|
410 |
|
|
return 1;
|
411 |
|
|
}
|
412 |
|
|
|
413 |
|
|
#if 0
|
414 |
|
|
if (CGEN_INT_INSN_P
|
415 |
|
|
&& word_offset != 0)
|
416 |
|
|
abort ();
|
417 |
|
|
#endif
|
418 |
|
|
|
419 |
|
|
if (word_length > 32)
|
420 |
|
|
abort ();
|
421 |
|
|
|
422 |
|
|
/* For architectures with insns smaller than the insn-base-bitsize,
|
423 |
|
|
word_length may be too big. */
|
424 |
|
|
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
|
425 |
|
|
{
|
426 |
|
|
if (word_offset == 0
|
427 |
|
|
&& word_length > total_length)
|
428 |
|
|
word_length = total_length;
|
429 |
|
|
}
|
430 |
|
|
|
431 |
|
|
/* Does the value reside in INSN_VALUE? */
|
432 |
|
|
|
433 |
|
|
if (CGEN_INT_INSN_P || word_offset == 0)
|
434 |
|
|
{
|
435 |
|
|
if (CGEN_INSN_LSB0_P)
|
436 |
|
|
value = insn_value >> ((word_offset + start + 1) - length);
|
437 |
|
|
else
|
438 |
|
|
value = insn_value >> (total_length - ( word_offset + start + length));
|
439 |
|
|
}
|
440 |
|
|
|
441 |
|
|
#if ! CGEN_INT_INSN_P
|
442 |
|
|
|
443 |
|
|
else
|
444 |
|
|
{
|
445 |
|
|
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
|
446 |
|
|
|
447 |
|
|
if (word_length > 32)
|
448 |
|
|
abort ();
|
449 |
|
|
|
450 |
|
|
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
|
451 |
|
|
return 0;
|
452 |
|
|
|
453 |
|
|
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
#endif /* ! CGEN_INT_INSN_P */
|
457 |
|
|
|
458 |
|
|
/* Written this way to avoid undefined behaviour. */
|
459 |
|
|
mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
460 |
|
|
|
461 |
|
|
value &= mask;
|
462 |
|
|
/* sign extend? */
|
463 |
|
|
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
464 |
|
|
&& (value & (1L << (length - 1))))
|
465 |
|
|
value |= ~mask;
|
466 |
|
|
|
467 |
|
|
*valuep = value;
|
468 |
|
|
|
469 |
|
|
return 1;
|
470 |
|
|
}
|
471 |
|
|
|
472 |
|
|
/* Default insn extractor.
|
473 |
|
|
|
474 |
|
|
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
|
475 |
|
|
The extracted fields are stored in FIELDS.
|
476 |
|
|
EX_INFO is used to handle reading variable length insns.
|
477 |
|
|
Return the length of the insn in bits, or 0 if no match,
|
478 |
|
|
or -1 if an error occurs fetching data (memory_error_func will have
|
479 |
|
|
been called). */
|
480 |
|
|
|
481 |
|
|
static int
|
482 |
|
|
extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
|
483 |
|
|
CGEN_CPU_DESC cd;
|
484 |
|
|
const CGEN_INSN *insn;
|
485 |
|
|
CGEN_EXTRACT_INFO *ex_info;
|
486 |
|
|
CGEN_INSN_INT insn_value;
|
487 |
|
|
CGEN_FIELDS *fields;
|
488 |
|
|
bfd_vma pc;
|
489 |
|
|
{
|
490 |
|
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
491 |
|
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
492 |
|
|
|
493 |
|
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
494 |
|
|
|
495 |
|
|
CGEN_INIT_EXTRACT (cd);
|
496 |
|
|
|
497 |
|
|
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
498 |
|
|
{
|
499 |
|
|
int length;
|
500 |
|
|
|
501 |
|
|
if (CGEN_SYNTAX_CHAR_P (*syn))
|
502 |
|
|
continue;
|
503 |
|
|
|
504 |
|
|
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
505 |
|
|
ex_info, insn_value, fields, pc);
|
506 |
|
|
if (length <= 0)
|
507 |
|
|
return length;
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
/* We recognized and successfully extracted this insn. */
|
511 |
|
|
return CGEN_INSN_BITSIZE (insn);
|
512 |
|
|
}
|
513 |
|
|
|
514 |
|
|
/* machine generated code added here */
|
515 |
|
|
|
516 |
|
|
/* Main entry point for operand insertion.
|
517 |
|
|
|
518 |
|
|
This function is basically just a big switch statement. Earlier versions
|
519 |
|
|
used tables to look up the function to use, but
|
520 |
|
|
- if the table contains both assembler and disassembler functions then
|
521 |
|
|
the disassembler contains much of the assembler and vice-versa,
|
522 |
|
|
- there's a lot of inlining possibilities as things grow,
|
523 |
|
|
- using a switch statement avoids the function call overhead.
|
524 |
|
|
|
525 |
|
|
This function could be moved into `parse_insn_normal', but keeping it
|
526 |
|
|
separate makes clear the interface between `parse_insn_normal' and each of
|
527 |
|
|
the handlers. It's also needed by GAS to insert operands that couldn't be
|
528 |
|
|
resolved during parsing.
|
529 |
|
|
*/
|
530 |
|
|
|
531 |
|
|
const char *
|
532 |
|
|
fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
|
533 |
|
|
CGEN_CPU_DESC cd;
|
534 |
|
|
int opindex;
|
535 |
|
|
CGEN_FIELDS * fields;
|
536 |
|
|
CGEN_INSN_BYTES_PTR buffer;
|
537 |
|
|
bfd_vma pc;
|
538 |
|
|
{
|
539 |
|
|
const char * errmsg = NULL;
|
540 |
|
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
541 |
|
|
|
542 |
|
|
switch (opindex)
|
543 |
|
|
{
|
544 |
|
|
case FR30_OPERAND_CRI :
|
545 |
|
|
errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer);
|
546 |
|
|
break;
|
547 |
|
|
case FR30_OPERAND_CRJ :
|
548 |
|
|
errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer);
|
549 |
|
|
break;
|
550 |
|
|
case FR30_OPERAND_R13 :
|
551 |
|
|
break;
|
552 |
|
|
case FR30_OPERAND_R14 :
|
553 |
|
|
break;
|
554 |
|
|
case FR30_OPERAND_R15 :
|
555 |
|
|
break;
|
556 |
|
|
case FR30_OPERAND_RI :
|
557 |
|
|
errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer);
|
558 |
|
|
break;
|
559 |
|
|
case FR30_OPERAND_RIC :
|
560 |
|
|
errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer);
|
561 |
|
|
break;
|
562 |
|
|
case FR30_OPERAND_RJ :
|
563 |
|
|
errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer);
|
564 |
|
|
break;
|
565 |
|
|
case FR30_OPERAND_RJC :
|
566 |
|
|
errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer);
|
567 |
|
|
break;
|
568 |
|
|
case FR30_OPERAND_RS1 :
|
569 |
|
|
errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer);
|
570 |
|
|
break;
|
571 |
|
|
case FR30_OPERAND_RS2 :
|
572 |
|
|
errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer);
|
573 |
|
|
break;
|
574 |
|
|
case FR30_OPERAND_CC :
|
575 |
|
|
errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer);
|
576 |
|
|
break;
|
577 |
|
|
case FR30_OPERAND_CCC :
|
578 |
|
|
errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer);
|
579 |
|
|
break;
|
580 |
|
|
case FR30_OPERAND_DIR10 :
|
581 |
|
|
{
|
582 |
|
|
long value = fields->f_dir10;
|
583 |
|
|
value = ((unsigned int) (value) >> (2));
|
584 |
|
|
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
|
585 |
|
|
}
|
586 |
|
|
break;
|
587 |
|
|
case FR30_OPERAND_DIR8 :
|
588 |
|
|
errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer);
|
589 |
|
|
break;
|
590 |
|
|
case FR30_OPERAND_DIR9 :
|
591 |
|
|
{
|
592 |
|
|
long value = fields->f_dir9;
|
593 |
|
|
value = ((unsigned int) (value) >> (1));
|
594 |
|
|
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
|
595 |
|
|
}
|
596 |
|
|
break;
|
597 |
|
|
case FR30_OPERAND_DISP10 :
|
598 |
|
|
{
|
599 |
|
|
long value = fields->f_disp10;
|
600 |
|
|
value = ((int) (value) >> (2));
|
601 |
|
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
|
602 |
|
|
}
|
603 |
|
|
break;
|
604 |
|
|
case FR30_OPERAND_DISP8 :
|
605 |
|
|
errmsg = insert_normal (cd, fields->f_disp8, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
|
606 |
|
|
break;
|
607 |
|
|
case FR30_OPERAND_DISP9 :
|
608 |
|
|
{
|
609 |
|
|
long value = fields->f_disp9;
|
610 |
|
|
value = ((int) (value) >> (1));
|
611 |
|
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
|
612 |
|
|
}
|
613 |
|
|
break;
|
614 |
|
|
case FR30_OPERAND_I20 :
|
615 |
|
|
{
|
616 |
|
|
{
|
617 |
|
|
FLD (f_i20_4) = ((unsigned int) (FLD (f_i20)) >> (16));
|
618 |
|
|
FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
|
619 |
|
|
}
|
620 |
|
|
errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
|
621 |
|
|
if (errmsg)
|
622 |
|
|
break;
|
623 |
|
|
errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer);
|
624 |
|
|
if (errmsg)
|
625 |
|
|
break;
|
626 |
|
|
}
|
627 |
|
|
break;
|
628 |
|
|
case FR30_OPERAND_I32 :
|
629 |
|
|
errmsg = insert_normal (cd, fields->f_i32, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, buffer);
|
630 |
|
|
break;
|
631 |
|
|
case FR30_OPERAND_I8 :
|
632 |
|
|
errmsg = insert_normal (cd, fields->f_i8, 0, 0, 4, 8, 16, total_length, buffer);
|
633 |
|
|
break;
|
634 |
|
|
case FR30_OPERAND_LABEL12 :
|
635 |
|
|
{
|
636 |
|
|
long value = fields->f_rel12;
|
637 |
|
|
value = ((int) (((value) - (((pc) + (2))))) >> (1));
|
638 |
|
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
|
639 |
|
|
}
|
640 |
|
|
break;
|
641 |
|
|
case FR30_OPERAND_LABEL9 :
|
642 |
|
|
{
|
643 |
|
|
long value = fields->f_rel9;
|
644 |
|
|
value = ((int) (((value) - (((pc) + (2))))) >> (1));
|
645 |
|
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
|
646 |
|
|
}
|
647 |
|
|
break;
|
648 |
|
|
case FR30_OPERAND_M4 :
|
649 |
|
|
{
|
650 |
|
|
long value = fields->f_m4;
|
651 |
|
|
value = ((value) & (15));
|
652 |
|
|
errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
|
653 |
|
|
}
|
654 |
|
|
break;
|
655 |
|
|
case FR30_OPERAND_PS :
|
656 |
|
|
break;
|
657 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
658 |
|
|
errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer);
|
659 |
|
|
break;
|
660 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
661 |
|
|
errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer);
|
662 |
|
|
break;
|
663 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
664 |
|
|
errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer);
|
665 |
|
|
break;
|
666 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
667 |
|
|
errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer);
|
668 |
|
|
break;
|
669 |
|
|
case FR30_OPERAND_S10 :
|
670 |
|
|
{
|
671 |
|
|
long value = fields->f_s10;
|
672 |
|
|
value = ((int) (value) >> (2));
|
673 |
|
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
|
674 |
|
|
}
|
675 |
|
|
break;
|
676 |
|
|
case FR30_OPERAND_U10 :
|
677 |
|
|
{
|
678 |
|
|
long value = fields->f_u10;
|
679 |
|
|
value = ((unsigned int) (value) >> (2));
|
680 |
|
|
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
|
681 |
|
|
}
|
682 |
|
|
break;
|
683 |
|
|
case FR30_OPERAND_U4 :
|
684 |
|
|
errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer);
|
685 |
|
|
break;
|
686 |
|
|
case FR30_OPERAND_U4C :
|
687 |
|
|
errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer);
|
688 |
|
|
break;
|
689 |
|
|
case FR30_OPERAND_U8 :
|
690 |
|
|
errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer);
|
691 |
|
|
break;
|
692 |
|
|
case FR30_OPERAND_UDISP6 :
|
693 |
|
|
{
|
694 |
|
|
long value = fields->f_udisp6;
|
695 |
|
|
value = ((unsigned int) (value) >> (2));
|
696 |
|
|
errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
|
697 |
|
|
}
|
698 |
|
|
break;
|
699 |
|
|
|
700 |
|
|
default :
|
701 |
|
|
/* xgettext:c-format */
|
702 |
|
|
fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
|
703 |
|
|
opindex);
|
704 |
|
|
abort ();
|
705 |
|
|
}
|
706 |
|
|
|
707 |
|
|
return errmsg;
|
708 |
|
|
}
|
709 |
|
|
|
710 |
|
|
/* Main entry point for operand extraction.
|
711 |
|
|
The result is <= 0 for error, >0 for success.
|
712 |
|
|
??? Actual values aren't well defined right now.
|
713 |
|
|
|
714 |
|
|
This function is basically just a big switch statement. Earlier versions
|
715 |
|
|
used tables to look up the function to use, but
|
716 |
|
|
- if the table contains both assembler and disassembler functions then
|
717 |
|
|
the disassembler contains much of the assembler and vice-versa,
|
718 |
|
|
- there's a lot of inlining possibilities as things grow,
|
719 |
|
|
- using a switch statement avoids the function call overhead.
|
720 |
|
|
|
721 |
|
|
This function could be moved into `print_insn_normal', but keeping it
|
722 |
|
|
separate makes clear the interface between `print_insn_normal' and each of
|
723 |
|
|
the handlers.
|
724 |
|
|
*/
|
725 |
|
|
|
726 |
|
|
int
|
727 |
|
|
fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
|
728 |
|
|
CGEN_CPU_DESC cd;
|
729 |
|
|
int opindex;
|
730 |
|
|
CGEN_EXTRACT_INFO *ex_info;
|
731 |
|
|
CGEN_INSN_INT insn_value;
|
732 |
|
|
CGEN_FIELDS * fields;
|
733 |
|
|
bfd_vma pc;
|
734 |
|
|
{
|
735 |
|
|
/* Assume success (for those operands that are nops). */
|
736 |
|
|
int length = 1;
|
737 |
|
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
738 |
|
|
|
739 |
|
|
switch (opindex)
|
740 |
|
|
{
|
741 |
|
|
case FR30_OPERAND_CRI :
|
742 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi);
|
743 |
|
|
break;
|
744 |
|
|
case FR30_OPERAND_CRJ :
|
745 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj);
|
746 |
|
|
break;
|
747 |
|
|
case FR30_OPERAND_R13 :
|
748 |
|
|
break;
|
749 |
|
|
case FR30_OPERAND_R14 :
|
750 |
|
|
break;
|
751 |
|
|
case FR30_OPERAND_R15 :
|
752 |
|
|
break;
|
753 |
|
|
case FR30_OPERAND_RI :
|
754 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri);
|
755 |
|
|
break;
|
756 |
|
|
case FR30_OPERAND_RIC :
|
757 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric);
|
758 |
|
|
break;
|
759 |
|
|
case FR30_OPERAND_RJ :
|
760 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj);
|
761 |
|
|
break;
|
762 |
|
|
case FR30_OPERAND_RJC :
|
763 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc);
|
764 |
|
|
break;
|
765 |
|
|
case FR30_OPERAND_RS1 :
|
766 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1);
|
767 |
|
|
break;
|
768 |
|
|
case FR30_OPERAND_RS2 :
|
769 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2);
|
770 |
|
|
break;
|
771 |
|
|
case FR30_OPERAND_CC :
|
772 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc);
|
773 |
|
|
break;
|
774 |
|
|
case FR30_OPERAND_CCC :
|
775 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc);
|
776 |
|
|
break;
|
777 |
|
|
case FR30_OPERAND_DIR10 :
|
778 |
|
|
{
|
779 |
|
|
long value;
|
780 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
|
781 |
|
|
value = ((value) << (2));
|
782 |
|
|
fields->f_dir10 = value;
|
783 |
|
|
}
|
784 |
|
|
break;
|
785 |
|
|
case FR30_OPERAND_DIR8 :
|
786 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8);
|
787 |
|
|
break;
|
788 |
|
|
case FR30_OPERAND_DIR9 :
|
789 |
|
|
{
|
790 |
|
|
long value;
|
791 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
|
792 |
|
|
value = ((value) << (1));
|
793 |
|
|
fields->f_dir9 = value;
|
794 |
|
|
}
|
795 |
|
|
break;
|
796 |
|
|
case FR30_OPERAND_DISP10 :
|
797 |
|
|
{
|
798 |
|
|
long value;
|
799 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
|
800 |
|
|
value = ((value) << (2));
|
801 |
|
|
fields->f_disp10 = value;
|
802 |
|
|
}
|
803 |
|
|
break;
|
804 |
|
|
case FR30_OPERAND_DISP8 :
|
805 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
|
806 |
|
|
break;
|
807 |
|
|
case FR30_OPERAND_DISP9 :
|
808 |
|
|
{
|
809 |
|
|
long value;
|
810 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
|
811 |
|
|
value = ((value) << (1));
|
812 |
|
|
fields->f_disp9 = value;
|
813 |
|
|
}
|
814 |
|
|
break;
|
815 |
|
|
case FR30_OPERAND_I20 :
|
816 |
|
|
{
|
817 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
|
818 |
|
|
if (length <= 0) break;
|
819 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16);
|
820 |
|
|
if (length <= 0) break;
|
821 |
|
|
{
|
822 |
|
|
FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16)));
|
823 |
|
|
}
|
824 |
|
|
}
|
825 |
|
|
break;
|
826 |
|
|
case FR30_OPERAND_I32 :
|
827 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, pc, & fields->f_i32);
|
828 |
|
|
break;
|
829 |
|
|
case FR30_OPERAND_I8 :
|
830 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8);
|
831 |
|
|
break;
|
832 |
|
|
case FR30_OPERAND_LABEL12 :
|
833 |
|
|
{
|
834 |
|
|
long value;
|
835 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value);
|
836 |
|
|
value = ((((value) << (1))) + (((pc) + (2))));
|
837 |
|
|
fields->f_rel12 = value;
|
838 |
|
|
}
|
839 |
|
|
break;
|
840 |
|
|
case FR30_OPERAND_LABEL9 :
|
841 |
|
|
{
|
842 |
|
|
long value;
|
843 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value);
|
844 |
|
|
value = ((((value) << (1))) + (((pc) + (2))));
|
845 |
|
|
fields->f_rel9 = value;
|
846 |
|
|
}
|
847 |
|
|
break;
|
848 |
|
|
case FR30_OPERAND_M4 :
|
849 |
|
|
{
|
850 |
|
|
long value;
|
851 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
|
852 |
|
|
value = ((value) | (((-1) << (4))));
|
853 |
|
|
fields->f_m4 = value;
|
854 |
|
|
}
|
855 |
|
|
break;
|
856 |
|
|
case FR30_OPERAND_PS :
|
857 |
|
|
break;
|
858 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
859 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld);
|
860 |
|
|
break;
|
861 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
862 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st);
|
863 |
|
|
break;
|
864 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
865 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld);
|
866 |
|
|
break;
|
867 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
868 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st);
|
869 |
|
|
break;
|
870 |
|
|
case FR30_OPERAND_S10 :
|
871 |
|
|
{
|
872 |
|
|
long value;
|
873 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
|
874 |
|
|
value = ((value) << (2));
|
875 |
|
|
fields->f_s10 = value;
|
876 |
|
|
}
|
877 |
|
|
break;
|
878 |
|
|
case FR30_OPERAND_U10 :
|
879 |
|
|
{
|
880 |
|
|
long value;
|
881 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
|
882 |
|
|
value = ((value) << (2));
|
883 |
|
|
fields->f_u10 = value;
|
884 |
|
|
}
|
885 |
|
|
break;
|
886 |
|
|
case FR30_OPERAND_U4 :
|
887 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4);
|
888 |
|
|
break;
|
889 |
|
|
case FR30_OPERAND_U4C :
|
890 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c);
|
891 |
|
|
break;
|
892 |
|
|
case FR30_OPERAND_U8 :
|
893 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8);
|
894 |
|
|
break;
|
895 |
|
|
case FR30_OPERAND_UDISP6 :
|
896 |
|
|
{
|
897 |
|
|
long value;
|
898 |
|
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
|
899 |
|
|
value = ((value) << (2));
|
900 |
|
|
fields->f_udisp6 = value;
|
901 |
|
|
}
|
902 |
|
|
break;
|
903 |
|
|
|
904 |
|
|
default :
|
905 |
|
|
/* xgettext:c-format */
|
906 |
|
|
fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
|
907 |
|
|
opindex);
|
908 |
|
|
abort ();
|
909 |
|
|
}
|
910 |
|
|
|
911 |
|
|
return length;
|
912 |
|
|
}
|
913 |
|
|
|
914 |
|
|
cgen_insert_fn * const fr30_cgen_insert_handlers[] =
|
915 |
|
|
{
|
916 |
|
|
insert_insn_normal,
|
917 |
|
|
};
|
918 |
|
|
|
919 |
|
|
cgen_extract_fn * const fr30_cgen_extract_handlers[] =
|
920 |
|
|
{
|
921 |
|
|
extract_insn_normal,
|
922 |
|
|
};
|
923 |
|
|
|
924 |
|
|
/* Getting values from cgen_fields is handled by a collection of functions.
|
925 |
|
|
They are distinguished by the type of the VALUE argument they return.
|
926 |
|
|
TODO: floating point, inlining support, remove cases where result type
|
927 |
|
|
not appropriate. */
|
928 |
|
|
|
929 |
|
|
int
|
930 |
|
|
fr30_cgen_get_int_operand (cd, opindex, fields)
|
931 |
|
|
CGEN_CPU_DESC cd;
|
932 |
|
|
int opindex;
|
933 |
|
|
const CGEN_FIELDS * fields;
|
934 |
|
|
{
|
935 |
|
|
int value;
|
936 |
|
|
|
937 |
|
|
switch (opindex)
|
938 |
|
|
{
|
939 |
|
|
case FR30_OPERAND_CRI :
|
940 |
|
|
value = fields->f_CRi;
|
941 |
|
|
break;
|
942 |
|
|
case FR30_OPERAND_CRJ :
|
943 |
|
|
value = fields->f_CRj;
|
944 |
|
|
break;
|
945 |
|
|
case FR30_OPERAND_R13 :
|
946 |
|
|
value = 0;
|
947 |
|
|
break;
|
948 |
|
|
case FR30_OPERAND_R14 :
|
949 |
|
|
value = 0;
|
950 |
|
|
break;
|
951 |
|
|
case FR30_OPERAND_R15 :
|
952 |
|
|
value = 0;
|
953 |
|
|
break;
|
954 |
|
|
case FR30_OPERAND_RI :
|
955 |
|
|
value = fields->f_Ri;
|
956 |
|
|
break;
|
957 |
|
|
case FR30_OPERAND_RIC :
|
958 |
|
|
value = fields->f_Ric;
|
959 |
|
|
break;
|
960 |
|
|
case FR30_OPERAND_RJ :
|
961 |
|
|
value = fields->f_Rj;
|
962 |
|
|
break;
|
963 |
|
|
case FR30_OPERAND_RJC :
|
964 |
|
|
value = fields->f_Rjc;
|
965 |
|
|
break;
|
966 |
|
|
case FR30_OPERAND_RS1 :
|
967 |
|
|
value = fields->f_Rs1;
|
968 |
|
|
break;
|
969 |
|
|
case FR30_OPERAND_RS2 :
|
970 |
|
|
value = fields->f_Rs2;
|
971 |
|
|
break;
|
972 |
|
|
case FR30_OPERAND_CC :
|
973 |
|
|
value = fields->f_cc;
|
974 |
|
|
break;
|
975 |
|
|
case FR30_OPERAND_CCC :
|
976 |
|
|
value = fields->f_ccc;
|
977 |
|
|
break;
|
978 |
|
|
case FR30_OPERAND_DIR10 :
|
979 |
|
|
value = fields->f_dir10;
|
980 |
|
|
break;
|
981 |
|
|
case FR30_OPERAND_DIR8 :
|
982 |
|
|
value = fields->f_dir8;
|
983 |
|
|
break;
|
984 |
|
|
case FR30_OPERAND_DIR9 :
|
985 |
|
|
value = fields->f_dir9;
|
986 |
|
|
break;
|
987 |
|
|
case FR30_OPERAND_DISP10 :
|
988 |
|
|
value = fields->f_disp10;
|
989 |
|
|
break;
|
990 |
|
|
case FR30_OPERAND_DISP8 :
|
991 |
|
|
value = fields->f_disp8;
|
992 |
|
|
break;
|
993 |
|
|
case FR30_OPERAND_DISP9 :
|
994 |
|
|
value = fields->f_disp9;
|
995 |
|
|
break;
|
996 |
|
|
case FR30_OPERAND_I20 :
|
997 |
|
|
value = fields->f_i20;
|
998 |
|
|
break;
|
999 |
|
|
case FR30_OPERAND_I32 :
|
1000 |
|
|
value = fields->f_i32;
|
1001 |
|
|
break;
|
1002 |
|
|
case FR30_OPERAND_I8 :
|
1003 |
|
|
value = fields->f_i8;
|
1004 |
|
|
break;
|
1005 |
|
|
case FR30_OPERAND_LABEL12 :
|
1006 |
|
|
value = fields->f_rel12;
|
1007 |
|
|
break;
|
1008 |
|
|
case FR30_OPERAND_LABEL9 :
|
1009 |
|
|
value = fields->f_rel9;
|
1010 |
|
|
break;
|
1011 |
|
|
case FR30_OPERAND_M4 :
|
1012 |
|
|
value = fields->f_m4;
|
1013 |
|
|
break;
|
1014 |
|
|
case FR30_OPERAND_PS :
|
1015 |
|
|
value = 0;
|
1016 |
|
|
break;
|
1017 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
1018 |
|
|
value = fields->f_reglist_hi_ld;
|
1019 |
|
|
break;
|
1020 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
1021 |
|
|
value = fields->f_reglist_hi_st;
|
1022 |
|
|
break;
|
1023 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
1024 |
|
|
value = fields->f_reglist_low_ld;
|
1025 |
|
|
break;
|
1026 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
1027 |
|
|
value = fields->f_reglist_low_st;
|
1028 |
|
|
break;
|
1029 |
|
|
case FR30_OPERAND_S10 :
|
1030 |
|
|
value = fields->f_s10;
|
1031 |
|
|
break;
|
1032 |
|
|
case FR30_OPERAND_U10 :
|
1033 |
|
|
value = fields->f_u10;
|
1034 |
|
|
break;
|
1035 |
|
|
case FR30_OPERAND_U4 :
|
1036 |
|
|
value = fields->f_u4;
|
1037 |
|
|
break;
|
1038 |
|
|
case FR30_OPERAND_U4C :
|
1039 |
|
|
value = fields->f_u4c;
|
1040 |
|
|
break;
|
1041 |
|
|
case FR30_OPERAND_U8 :
|
1042 |
|
|
value = fields->f_u8;
|
1043 |
|
|
break;
|
1044 |
|
|
case FR30_OPERAND_UDISP6 :
|
1045 |
|
|
value = fields->f_udisp6;
|
1046 |
|
|
break;
|
1047 |
|
|
|
1048 |
|
|
default :
|
1049 |
|
|
/* xgettext:c-format */
|
1050 |
|
|
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
1051 |
|
|
opindex);
|
1052 |
|
|
abort ();
|
1053 |
|
|
}
|
1054 |
|
|
|
1055 |
|
|
return value;
|
1056 |
|
|
}
|
1057 |
|
|
|
1058 |
|
|
bfd_vma
|
1059 |
|
|
fr30_cgen_get_vma_operand (cd, opindex, fields)
|
1060 |
|
|
CGEN_CPU_DESC cd;
|
1061 |
|
|
int opindex;
|
1062 |
|
|
const CGEN_FIELDS * fields;
|
1063 |
|
|
{
|
1064 |
|
|
bfd_vma value;
|
1065 |
|
|
|
1066 |
|
|
switch (opindex)
|
1067 |
|
|
{
|
1068 |
|
|
case FR30_OPERAND_CRI :
|
1069 |
|
|
value = fields->f_CRi;
|
1070 |
|
|
break;
|
1071 |
|
|
case FR30_OPERAND_CRJ :
|
1072 |
|
|
value = fields->f_CRj;
|
1073 |
|
|
break;
|
1074 |
|
|
case FR30_OPERAND_R13 :
|
1075 |
|
|
value = 0;
|
1076 |
|
|
break;
|
1077 |
|
|
case FR30_OPERAND_R14 :
|
1078 |
|
|
value = 0;
|
1079 |
|
|
break;
|
1080 |
|
|
case FR30_OPERAND_R15 :
|
1081 |
|
|
value = 0;
|
1082 |
|
|
break;
|
1083 |
|
|
case FR30_OPERAND_RI :
|
1084 |
|
|
value = fields->f_Ri;
|
1085 |
|
|
break;
|
1086 |
|
|
case FR30_OPERAND_RIC :
|
1087 |
|
|
value = fields->f_Ric;
|
1088 |
|
|
break;
|
1089 |
|
|
case FR30_OPERAND_RJ :
|
1090 |
|
|
value = fields->f_Rj;
|
1091 |
|
|
break;
|
1092 |
|
|
case FR30_OPERAND_RJC :
|
1093 |
|
|
value = fields->f_Rjc;
|
1094 |
|
|
break;
|
1095 |
|
|
case FR30_OPERAND_RS1 :
|
1096 |
|
|
value = fields->f_Rs1;
|
1097 |
|
|
break;
|
1098 |
|
|
case FR30_OPERAND_RS2 :
|
1099 |
|
|
value = fields->f_Rs2;
|
1100 |
|
|
break;
|
1101 |
|
|
case FR30_OPERAND_CC :
|
1102 |
|
|
value = fields->f_cc;
|
1103 |
|
|
break;
|
1104 |
|
|
case FR30_OPERAND_CCC :
|
1105 |
|
|
value = fields->f_ccc;
|
1106 |
|
|
break;
|
1107 |
|
|
case FR30_OPERAND_DIR10 :
|
1108 |
|
|
value = fields->f_dir10;
|
1109 |
|
|
break;
|
1110 |
|
|
case FR30_OPERAND_DIR8 :
|
1111 |
|
|
value = fields->f_dir8;
|
1112 |
|
|
break;
|
1113 |
|
|
case FR30_OPERAND_DIR9 :
|
1114 |
|
|
value = fields->f_dir9;
|
1115 |
|
|
break;
|
1116 |
|
|
case FR30_OPERAND_DISP10 :
|
1117 |
|
|
value = fields->f_disp10;
|
1118 |
|
|
break;
|
1119 |
|
|
case FR30_OPERAND_DISP8 :
|
1120 |
|
|
value = fields->f_disp8;
|
1121 |
|
|
break;
|
1122 |
|
|
case FR30_OPERAND_DISP9 :
|
1123 |
|
|
value = fields->f_disp9;
|
1124 |
|
|
break;
|
1125 |
|
|
case FR30_OPERAND_I20 :
|
1126 |
|
|
value = fields->f_i20;
|
1127 |
|
|
break;
|
1128 |
|
|
case FR30_OPERAND_I32 :
|
1129 |
|
|
value = fields->f_i32;
|
1130 |
|
|
break;
|
1131 |
|
|
case FR30_OPERAND_I8 :
|
1132 |
|
|
value = fields->f_i8;
|
1133 |
|
|
break;
|
1134 |
|
|
case FR30_OPERAND_LABEL12 :
|
1135 |
|
|
value = fields->f_rel12;
|
1136 |
|
|
break;
|
1137 |
|
|
case FR30_OPERAND_LABEL9 :
|
1138 |
|
|
value = fields->f_rel9;
|
1139 |
|
|
break;
|
1140 |
|
|
case FR30_OPERAND_M4 :
|
1141 |
|
|
value = fields->f_m4;
|
1142 |
|
|
break;
|
1143 |
|
|
case FR30_OPERAND_PS :
|
1144 |
|
|
value = 0;
|
1145 |
|
|
break;
|
1146 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
1147 |
|
|
value = fields->f_reglist_hi_ld;
|
1148 |
|
|
break;
|
1149 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
1150 |
|
|
value = fields->f_reglist_hi_st;
|
1151 |
|
|
break;
|
1152 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
1153 |
|
|
value = fields->f_reglist_low_ld;
|
1154 |
|
|
break;
|
1155 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
1156 |
|
|
value = fields->f_reglist_low_st;
|
1157 |
|
|
break;
|
1158 |
|
|
case FR30_OPERAND_S10 :
|
1159 |
|
|
value = fields->f_s10;
|
1160 |
|
|
break;
|
1161 |
|
|
case FR30_OPERAND_U10 :
|
1162 |
|
|
value = fields->f_u10;
|
1163 |
|
|
break;
|
1164 |
|
|
case FR30_OPERAND_U4 :
|
1165 |
|
|
value = fields->f_u4;
|
1166 |
|
|
break;
|
1167 |
|
|
case FR30_OPERAND_U4C :
|
1168 |
|
|
value = fields->f_u4c;
|
1169 |
|
|
break;
|
1170 |
|
|
case FR30_OPERAND_U8 :
|
1171 |
|
|
value = fields->f_u8;
|
1172 |
|
|
break;
|
1173 |
|
|
case FR30_OPERAND_UDISP6 :
|
1174 |
|
|
value = fields->f_udisp6;
|
1175 |
|
|
break;
|
1176 |
|
|
|
1177 |
|
|
default :
|
1178 |
|
|
/* xgettext:c-format */
|
1179 |
|
|
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
1180 |
|
|
opindex);
|
1181 |
|
|
abort ();
|
1182 |
|
|
}
|
1183 |
|
|
|
1184 |
|
|
return value;
|
1185 |
|
|
}
|
1186 |
|
|
|
1187 |
|
|
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
1188 |
|
|
They are distinguished by the type of the VALUE argument they accept.
|
1189 |
|
|
TODO: floating point, inlining support, remove cases where argument type
|
1190 |
|
|
not appropriate. */
|
1191 |
|
|
|
1192 |
|
|
void
|
1193 |
|
|
fr30_cgen_set_int_operand (cd, opindex, fields, value)
|
1194 |
|
|
CGEN_CPU_DESC cd;
|
1195 |
|
|
int opindex;
|
1196 |
|
|
CGEN_FIELDS * fields;
|
1197 |
|
|
int value;
|
1198 |
|
|
{
|
1199 |
|
|
switch (opindex)
|
1200 |
|
|
{
|
1201 |
|
|
case FR30_OPERAND_CRI :
|
1202 |
|
|
fields->f_CRi = value;
|
1203 |
|
|
break;
|
1204 |
|
|
case FR30_OPERAND_CRJ :
|
1205 |
|
|
fields->f_CRj = value;
|
1206 |
|
|
break;
|
1207 |
|
|
case FR30_OPERAND_R13 :
|
1208 |
|
|
break;
|
1209 |
|
|
case FR30_OPERAND_R14 :
|
1210 |
|
|
break;
|
1211 |
|
|
case FR30_OPERAND_R15 :
|
1212 |
|
|
break;
|
1213 |
|
|
case FR30_OPERAND_RI :
|
1214 |
|
|
fields->f_Ri = value;
|
1215 |
|
|
break;
|
1216 |
|
|
case FR30_OPERAND_RIC :
|
1217 |
|
|
fields->f_Ric = value;
|
1218 |
|
|
break;
|
1219 |
|
|
case FR30_OPERAND_RJ :
|
1220 |
|
|
fields->f_Rj = value;
|
1221 |
|
|
break;
|
1222 |
|
|
case FR30_OPERAND_RJC :
|
1223 |
|
|
fields->f_Rjc = value;
|
1224 |
|
|
break;
|
1225 |
|
|
case FR30_OPERAND_RS1 :
|
1226 |
|
|
fields->f_Rs1 = value;
|
1227 |
|
|
break;
|
1228 |
|
|
case FR30_OPERAND_RS2 :
|
1229 |
|
|
fields->f_Rs2 = value;
|
1230 |
|
|
break;
|
1231 |
|
|
case FR30_OPERAND_CC :
|
1232 |
|
|
fields->f_cc = value;
|
1233 |
|
|
break;
|
1234 |
|
|
case FR30_OPERAND_CCC :
|
1235 |
|
|
fields->f_ccc = value;
|
1236 |
|
|
break;
|
1237 |
|
|
case FR30_OPERAND_DIR10 :
|
1238 |
|
|
fields->f_dir10 = value;
|
1239 |
|
|
break;
|
1240 |
|
|
case FR30_OPERAND_DIR8 :
|
1241 |
|
|
fields->f_dir8 = value;
|
1242 |
|
|
break;
|
1243 |
|
|
case FR30_OPERAND_DIR9 :
|
1244 |
|
|
fields->f_dir9 = value;
|
1245 |
|
|
break;
|
1246 |
|
|
case FR30_OPERAND_DISP10 :
|
1247 |
|
|
fields->f_disp10 = value;
|
1248 |
|
|
break;
|
1249 |
|
|
case FR30_OPERAND_DISP8 :
|
1250 |
|
|
fields->f_disp8 = value;
|
1251 |
|
|
break;
|
1252 |
|
|
case FR30_OPERAND_DISP9 :
|
1253 |
|
|
fields->f_disp9 = value;
|
1254 |
|
|
break;
|
1255 |
|
|
case FR30_OPERAND_I20 :
|
1256 |
|
|
fields->f_i20 = value;
|
1257 |
|
|
break;
|
1258 |
|
|
case FR30_OPERAND_I32 :
|
1259 |
|
|
fields->f_i32 = value;
|
1260 |
|
|
break;
|
1261 |
|
|
case FR30_OPERAND_I8 :
|
1262 |
|
|
fields->f_i8 = value;
|
1263 |
|
|
break;
|
1264 |
|
|
case FR30_OPERAND_LABEL12 :
|
1265 |
|
|
fields->f_rel12 = value;
|
1266 |
|
|
break;
|
1267 |
|
|
case FR30_OPERAND_LABEL9 :
|
1268 |
|
|
fields->f_rel9 = value;
|
1269 |
|
|
break;
|
1270 |
|
|
case FR30_OPERAND_M4 :
|
1271 |
|
|
fields->f_m4 = value;
|
1272 |
|
|
break;
|
1273 |
|
|
case FR30_OPERAND_PS :
|
1274 |
|
|
break;
|
1275 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
1276 |
|
|
fields->f_reglist_hi_ld = value;
|
1277 |
|
|
break;
|
1278 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
1279 |
|
|
fields->f_reglist_hi_st = value;
|
1280 |
|
|
break;
|
1281 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
1282 |
|
|
fields->f_reglist_low_ld = value;
|
1283 |
|
|
break;
|
1284 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
1285 |
|
|
fields->f_reglist_low_st = value;
|
1286 |
|
|
break;
|
1287 |
|
|
case FR30_OPERAND_S10 :
|
1288 |
|
|
fields->f_s10 = value;
|
1289 |
|
|
break;
|
1290 |
|
|
case FR30_OPERAND_U10 :
|
1291 |
|
|
fields->f_u10 = value;
|
1292 |
|
|
break;
|
1293 |
|
|
case FR30_OPERAND_U4 :
|
1294 |
|
|
fields->f_u4 = value;
|
1295 |
|
|
break;
|
1296 |
|
|
case FR30_OPERAND_U4C :
|
1297 |
|
|
fields->f_u4c = value;
|
1298 |
|
|
break;
|
1299 |
|
|
case FR30_OPERAND_U8 :
|
1300 |
|
|
fields->f_u8 = value;
|
1301 |
|
|
break;
|
1302 |
|
|
case FR30_OPERAND_UDISP6 :
|
1303 |
|
|
fields->f_udisp6 = value;
|
1304 |
|
|
break;
|
1305 |
|
|
|
1306 |
|
|
default :
|
1307 |
|
|
/* xgettext:c-format */
|
1308 |
|
|
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
1309 |
|
|
opindex);
|
1310 |
|
|
abort ();
|
1311 |
|
|
}
|
1312 |
|
|
}
|
1313 |
|
|
|
1314 |
|
|
void
|
1315 |
|
|
fr30_cgen_set_vma_operand (cd, opindex, fields, value)
|
1316 |
|
|
CGEN_CPU_DESC cd;
|
1317 |
|
|
int opindex;
|
1318 |
|
|
CGEN_FIELDS * fields;
|
1319 |
|
|
bfd_vma value;
|
1320 |
|
|
{
|
1321 |
|
|
switch (opindex)
|
1322 |
|
|
{
|
1323 |
|
|
case FR30_OPERAND_CRI :
|
1324 |
|
|
fields->f_CRi = value;
|
1325 |
|
|
break;
|
1326 |
|
|
case FR30_OPERAND_CRJ :
|
1327 |
|
|
fields->f_CRj = value;
|
1328 |
|
|
break;
|
1329 |
|
|
case FR30_OPERAND_R13 :
|
1330 |
|
|
break;
|
1331 |
|
|
case FR30_OPERAND_R14 :
|
1332 |
|
|
break;
|
1333 |
|
|
case FR30_OPERAND_R15 :
|
1334 |
|
|
break;
|
1335 |
|
|
case FR30_OPERAND_RI :
|
1336 |
|
|
fields->f_Ri = value;
|
1337 |
|
|
break;
|
1338 |
|
|
case FR30_OPERAND_RIC :
|
1339 |
|
|
fields->f_Ric = value;
|
1340 |
|
|
break;
|
1341 |
|
|
case FR30_OPERAND_RJ :
|
1342 |
|
|
fields->f_Rj = value;
|
1343 |
|
|
break;
|
1344 |
|
|
case FR30_OPERAND_RJC :
|
1345 |
|
|
fields->f_Rjc = value;
|
1346 |
|
|
break;
|
1347 |
|
|
case FR30_OPERAND_RS1 :
|
1348 |
|
|
fields->f_Rs1 = value;
|
1349 |
|
|
break;
|
1350 |
|
|
case FR30_OPERAND_RS2 :
|
1351 |
|
|
fields->f_Rs2 = value;
|
1352 |
|
|
break;
|
1353 |
|
|
case FR30_OPERAND_CC :
|
1354 |
|
|
fields->f_cc = value;
|
1355 |
|
|
break;
|
1356 |
|
|
case FR30_OPERAND_CCC :
|
1357 |
|
|
fields->f_ccc = value;
|
1358 |
|
|
break;
|
1359 |
|
|
case FR30_OPERAND_DIR10 :
|
1360 |
|
|
fields->f_dir10 = value;
|
1361 |
|
|
break;
|
1362 |
|
|
case FR30_OPERAND_DIR8 :
|
1363 |
|
|
fields->f_dir8 = value;
|
1364 |
|
|
break;
|
1365 |
|
|
case FR30_OPERAND_DIR9 :
|
1366 |
|
|
fields->f_dir9 = value;
|
1367 |
|
|
break;
|
1368 |
|
|
case FR30_OPERAND_DISP10 :
|
1369 |
|
|
fields->f_disp10 = value;
|
1370 |
|
|
break;
|
1371 |
|
|
case FR30_OPERAND_DISP8 :
|
1372 |
|
|
fields->f_disp8 = value;
|
1373 |
|
|
break;
|
1374 |
|
|
case FR30_OPERAND_DISP9 :
|
1375 |
|
|
fields->f_disp9 = value;
|
1376 |
|
|
break;
|
1377 |
|
|
case FR30_OPERAND_I20 :
|
1378 |
|
|
fields->f_i20 = value;
|
1379 |
|
|
break;
|
1380 |
|
|
case FR30_OPERAND_I32 :
|
1381 |
|
|
fields->f_i32 = value;
|
1382 |
|
|
break;
|
1383 |
|
|
case FR30_OPERAND_I8 :
|
1384 |
|
|
fields->f_i8 = value;
|
1385 |
|
|
break;
|
1386 |
|
|
case FR30_OPERAND_LABEL12 :
|
1387 |
|
|
fields->f_rel12 = value;
|
1388 |
|
|
break;
|
1389 |
|
|
case FR30_OPERAND_LABEL9 :
|
1390 |
|
|
fields->f_rel9 = value;
|
1391 |
|
|
break;
|
1392 |
|
|
case FR30_OPERAND_M4 :
|
1393 |
|
|
fields->f_m4 = value;
|
1394 |
|
|
break;
|
1395 |
|
|
case FR30_OPERAND_PS :
|
1396 |
|
|
break;
|
1397 |
|
|
case FR30_OPERAND_REGLIST_HI_LD :
|
1398 |
|
|
fields->f_reglist_hi_ld = value;
|
1399 |
|
|
break;
|
1400 |
|
|
case FR30_OPERAND_REGLIST_HI_ST :
|
1401 |
|
|
fields->f_reglist_hi_st = value;
|
1402 |
|
|
break;
|
1403 |
|
|
case FR30_OPERAND_REGLIST_LOW_LD :
|
1404 |
|
|
fields->f_reglist_low_ld = value;
|
1405 |
|
|
break;
|
1406 |
|
|
case FR30_OPERAND_REGLIST_LOW_ST :
|
1407 |
|
|
fields->f_reglist_low_st = value;
|
1408 |
|
|
break;
|
1409 |
|
|
case FR30_OPERAND_S10 :
|
1410 |
|
|
fields->f_s10 = value;
|
1411 |
|
|
break;
|
1412 |
|
|
case FR30_OPERAND_U10 :
|
1413 |
|
|
fields->f_u10 = value;
|
1414 |
|
|
break;
|
1415 |
|
|
case FR30_OPERAND_U4 :
|
1416 |
|
|
fields->f_u4 = value;
|
1417 |
|
|
break;
|
1418 |
|
|
case FR30_OPERAND_U4C :
|
1419 |
|
|
fields->f_u4c = value;
|
1420 |
|
|
break;
|
1421 |
|
|
case FR30_OPERAND_U8 :
|
1422 |
|
|
fields->f_u8 = value;
|
1423 |
|
|
break;
|
1424 |
|
|
case FR30_OPERAND_UDISP6 :
|
1425 |
|
|
fields->f_udisp6 = value;
|
1426 |
|
|
break;
|
1427 |
|
|
|
1428 |
|
|
default :
|
1429 |
|
|
/* xgettext:c-format */
|
1430 |
|
|
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
1431 |
|
|
opindex);
|
1432 |
|
|
abort ();
|
1433 |
|
|
}
|
1434 |
|
|
}
|
1435 |
|
|
|
1436 |
|
|
/* Function to call before using the instruction builder tables. */
|
1437 |
|
|
|
1438 |
|
|
void
|
1439 |
|
|
fr30_cgen_init_ibld_table (cd)
|
1440 |
|
|
CGEN_CPU_DESC cd;
|
1441 |
|
|
{
|
1442 |
|
|
cd->insert_handlers = & fr30_cgen_insert_handlers[0];
|
1443 |
|
|
cd->extract_handlers = & fr30_cgen_extract_handlers[0];
|
1444 |
|
|
|
1445 |
|
|
cd->insert_operand = fr30_cgen_insert_operand;
|
1446 |
|
|
cd->extract_operand = fr30_cgen_extract_operand;
|
1447 |
|
|
|
1448 |
|
|
cd->get_int_operand = fr30_cgen_get_int_operand;
|
1449 |
|
|
cd->set_int_operand = fr30_cgen_set_int_operand;
|
1450 |
|
|
cd->get_vma_operand = fr30_cgen_get_vma_operand;
|
1451 |
|
|
cd->set_vma_operand = fr30_cgen_set_vma_operand;
|
1452 |
|
|
}
|