OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [opcodes/] [m32r-opinst.c] - Blame information for rev 1772

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom 
/* Semantic operand instances for m32r.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include "ansidecl.h"
27 
#include "bfd.h"
28 
#include "symcat.h"
29 
#include "m32r-desc.h"
30 
#include "m32r-opc.h"
31 
 
32 
/* Operand references.  */
33 
 
34 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
35 
#define OP_ENT(op) M32R_OPERAND_##op
36 
#else
37 
#define OP_ENT(op) M32R_OPERAND_/**/op
38 
#endif
39 
#define INPUT CGEN_OPINST_INPUT
40 
#define OUTPUT CGEN_OPINST_OUTPUT
41 
#define END CGEN_OPINST_END
42 
#define COND_REF CGEN_OPINST_COND_REF
43 
 
44 
static const CGEN_OPINST sfmt_empty_ops[] = {
45 
  { END }
46 
};
47 
 
48 
static const CGEN_OPINST sfmt_add_ops[] = {
49 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
50 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
51 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
52 
  { END }
53 
};
54 
 
55 
static const CGEN_OPINST sfmt_add3_ops[] = {
56 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
57 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
58 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
59 
  { END }
60 
};
61 
 
62 
static const CGEN_OPINST sfmt_and3_ops[] = {
63 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
64 
  { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
65 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
66 
  { END }
67 
};
68 
 
69 
static const CGEN_OPINST sfmt_or3_ops[] = {
70 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
71 
  { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
72 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
73 
  { END }
74 
};
75 
 
76 
static const CGEN_OPINST sfmt_addi_ops[] = {
77 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
78 
  { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
79 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
80 
  { END }
81 
};
82 
 
83 
static const CGEN_OPINST sfmt_addv_ops[] = {
84 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
85 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
86 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
87 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
88 
  { END }
89 
};
90 
 
91 
static const CGEN_OPINST sfmt_addv3_ops[] = {
92 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
93 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
94 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
95 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
96 
  { END }
97 
};
98 
 
99 
static const CGEN_OPINST sfmt_addx_ops[] = {
100 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
101 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
102 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
103 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
104 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
105 
  { END }
106 
};
107 
 
108 
static const CGEN_OPINST sfmt_bc8_ops[] = {
109 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
110 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
111 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
112 
  { END }
113 
};
114 
 
115 
static const CGEN_OPINST sfmt_bc24_ops[] = {
116 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
117 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
118 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
119 
  { END }
120 
};
121 
 
122 
static const CGEN_OPINST sfmt_beq_ops[] = {
123 
  { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
124 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
125 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
126 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
127 
  { END }
128 
};
129 
 
130 
static const CGEN_OPINST sfmt_beqz_ops[] = {
131 
  { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
132 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
133 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
134 
  { END }
135 
};
136 
 
137 
static const CGEN_OPINST sfmt_bl8_ops[] = {
138 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
139 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
140 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
141 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
142 
  { END }
143 
};
144 
 
145 
static const CGEN_OPINST sfmt_bl24_ops[] = {
146 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
147 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
148 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
149 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
150 
  { END }
151 
};
152 
 
153 
static const CGEN_OPINST sfmt_bcl8_ops[] = {
154 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
155 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
156 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
157 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
158 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
159 
  { END }
160 
};
161 
 
162 
static const CGEN_OPINST sfmt_bcl24_ops[] = {
163 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
164 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
165 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
166 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
167 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
168 
  { END }
169 
};
170 
 
171 
static const CGEN_OPINST sfmt_bra8_ops[] = {
172 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
173 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
174 
  { END }
175 
};
176 
 
177 
static const CGEN_OPINST sfmt_bra24_ops[] = {
178 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
179 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
180 
  { END }
181 
};
182 
 
183 
static const CGEN_OPINST sfmt_cmp_ops[] = {
184 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
185 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
186 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
187 
  { END }
188 
};
189 
 
190 
static const CGEN_OPINST sfmt_cmpi_ops[] = {
191 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
192 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
193 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
194 
  { END }
195 
};
196 
 
197 
static const CGEN_OPINST sfmt_cmpz_ops[] = {
198 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
199 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
200 
  { END }
201 
};
202 
 
203 
static const CGEN_OPINST sfmt_div_ops[] = {
204 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
205 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
206 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
207 
  { END }
208 
};
209 
 
210 
static const CGEN_OPINST sfmt_jc_ops[] = {
211 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
212 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
213 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
214 
  { END }
215 
};
216 
 
217 
static const CGEN_OPINST sfmt_jl_ops[] = {
218 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
219 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
220 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
221 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
222 
  { END }
223 
};
224 
 
225 
static const CGEN_OPINST sfmt_jmp_ops[] = {
226 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
227 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
228 
  { END }
229 
};
230 
 
231 
static const CGEN_OPINST sfmt_ld_ops[] = {
232 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
233 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
234 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
235 
  { END }
236 
};
237 
 
238 
static const CGEN_OPINST sfmt_ld_d_ops[] = {
239 
  { INPUT, "h_memory_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
240 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
241 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
242 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
243 
  { END }
244 
};
245 
 
246 
static const CGEN_OPINST sfmt_ld_plus_ops[] = {
247 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
248 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
249 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
250 
  { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
251 
  { END }
252 
};
253 
 
254 
static const CGEN_OPINST sfmt_ld24_ops[] = {
255 
  { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
256 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
257 
  { END }
258 
};
259 
 
260 
static const CGEN_OPINST sfmt_ldi8_ops[] = {
261 
  { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
262 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
263 
  { END }
264 
};
265 
 
266 
static const CGEN_OPINST sfmt_ldi16_ops[] = {
267 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
268 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
269 
  { END }
270 
};
271 
 
272 
static const CGEN_OPINST sfmt_lock_ops[] = {
273 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
274 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
275 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
276 
  { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
277 
  { END }
278 
};
279 
 
280 
static const CGEN_OPINST sfmt_machi_ops[] = {
281 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
282 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
283 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
284 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
285 
  { END }
286 
};
287 
 
288 
static const CGEN_OPINST sfmt_machi_a_ops[] = {
289 
  { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
290 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
291 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
292 
  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
293 
  { END }
294 
};
295 
 
296 
static const CGEN_OPINST sfmt_mulhi_ops[] = {
297 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
298 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
299 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
300 
  { END }
301 
};
302 
 
303 
static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
304 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
305 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
306 
  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
307 
  { END }
308 
};
309 
 
310 
static const CGEN_OPINST sfmt_mv_ops[] = {
311 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
312 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
313 
  { END }
314 
};
315 
 
316 
static const CGEN_OPINST sfmt_mvfachi_ops[] = {
317 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
318 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
319 
  { END }
320 
};
321 
 
322 
static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
323 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
324 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
325 
  { END }
326 
};
327 
 
328 
static const CGEN_OPINST sfmt_mvfc_ops[] = {
329 
  { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
330 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
331 
  { END }
332 
};
333 
 
334 
static const CGEN_OPINST sfmt_mvtachi_ops[] = {
335 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
336 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
337 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
338 
  { END }
339 
};
340 
 
341 
static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
342 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
343 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
344 
  { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
345 
  { END }
346 
};
347 
 
348 
static const CGEN_OPINST sfmt_mvtc_ops[] = {
349 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
350 
  { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
351 
  { END }
352 
};
353 
 
354 
static const CGEN_OPINST sfmt_nop_ops[] = {
355 
  { END }
356 
};
357 
 
358 
static const CGEN_OPINST sfmt_rac_ops[] = {
359 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
360 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
361 
  { END }
362 
};
363 
 
364 
static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
365 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
366 
  { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
367 
  { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
368 
  { END }
369 
};
370 
 
371 
static const CGEN_OPINST sfmt_rte_ops[] = {
372 
  { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
373 
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
374 
  { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
375 
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
376 
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
377 
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
378 
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
379 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
380 
  { END }
381 
};
382 
 
383 
static const CGEN_OPINST sfmt_seth_ops[] = {
384 
  { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
385 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
386 
  { END }
387 
};
388 
 
389 
static const CGEN_OPINST sfmt_sll3_ops[] = {
390 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
391 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
392 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
393 
  { END }
394 
};
395 
 
396 
static const CGEN_OPINST sfmt_slli_ops[] = {
397 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
398 
  { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
399 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
400 
  { END }
401 
};
402 
 
403 
static const CGEN_OPINST sfmt_st_ops[] = {
404 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
405 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
406 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
407 
  { END }
408 
};
409 
 
410 
static const CGEN_OPINST sfmt_st_d_ops[] = {
411 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
412 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
413 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
414 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
415 
  { END }
416 
};
417 
 
418 
static const CGEN_OPINST sfmt_stb_ops[] = {
419 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
420 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
421 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
422 
  { END }
423 
};
424 
 
425 
static const CGEN_OPINST sfmt_stb_d_ops[] = {
426 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
427 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
428 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
429 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
430 
  { END }
431 
};
432 
 
433 
static const CGEN_OPINST sfmt_sth_ops[] = {
434 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
435 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
436 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
437 
  { END }
438 
};
439 
 
440 
static const CGEN_OPINST sfmt_sth_d_ops[] = {
441 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
442 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
443 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
444 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
445 
  { END }
446 
};
447 
 
448 
static const CGEN_OPINST sfmt_st_plus_ops[] = {
449 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
450 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
451 
  { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
452 
  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
453 
  { END }
454 
};
455 
 
456 
static const CGEN_OPINST sfmt_trap_ops[] = {
457 
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
458 
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
459 
  { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
460 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
461 
  { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
462 
  { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
463 
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
464 
  { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
465 
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
466 
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
467 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
468 
  { END }
469 
};
470 
 
471 
static const CGEN_OPINST sfmt_unlock_ops[] = {
472 
  { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
473 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
474 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
475 
  { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
476 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
477 
  { END }
478 
};
479 
 
480 
static const CGEN_OPINST sfmt_satb_ops[] = {
481 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
482 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
483 
  { END }
484 
};
485 
 
486 
static const CGEN_OPINST sfmt_sat_ops[] = {
487 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
488 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
489 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
490 
  { END }
491 
};
492 
 
493 
static const CGEN_OPINST sfmt_sadd_ops[] = {
494 
  { INPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
495 
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
496 
  { OUTPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
497 
  { END }
498 
};
499 
 
500 
static const CGEN_OPINST sfmt_macwu1_ops[] = {
501 
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
502 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
503 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
504 
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
505 
  { END }
506 
};
507 
 
508 
static const CGEN_OPINST sfmt_mulwu1_ops[] = {
509 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
510 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
511 
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
512 
  { END }
513 
};
514 
 
515 
static const CGEN_OPINST sfmt_sc_ops[] = {
516 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
517 
  { END }
518 
};
519 
 
520 
#undef OP_ENT
521 
#undef INPUT
522 
#undef OUTPUT
523 
#undef END
524 
#undef COND_REF
525 
 
526 
/* Operand instance lookup table.  */
527 
 
528 
static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
529 
  0,
530 
  & sfmt_add_ops[0],
531 
  & sfmt_add3_ops[0],
532 
  & sfmt_add_ops[0],
533 
  & sfmt_and3_ops[0],
534 
  & sfmt_add_ops[0],
535 
  & sfmt_or3_ops[0],
536 
  & sfmt_add_ops[0],
537 
  & sfmt_and3_ops[0],
538 
  & sfmt_addi_ops[0],
539 
  & sfmt_addv_ops[0],
540 
  & sfmt_addv3_ops[0],
541 
  & sfmt_addx_ops[0],
542 
  & sfmt_bc8_ops[0],
543 
  & sfmt_bc24_ops[0],
544 
  & sfmt_beq_ops[0],
545 
  & sfmt_beqz_ops[0],
546 
  & sfmt_beqz_ops[0],
547 
  & sfmt_beqz_ops[0],
548 
  & sfmt_beqz_ops[0],
549 
  & sfmt_beqz_ops[0],
550 
  & sfmt_beqz_ops[0],
551 
  & sfmt_bl8_ops[0],
552 
  & sfmt_bl24_ops[0],
553 
  & sfmt_bcl8_ops[0],
554 
  & sfmt_bcl24_ops[0],
555 
  & sfmt_bc8_ops[0],
556 
  & sfmt_bc24_ops[0],
557 
  & sfmt_beq_ops[0],
558 
  & sfmt_bra8_ops[0],
559 
  & sfmt_bra24_ops[0],
560 
  & sfmt_bcl8_ops[0],
561 
  & sfmt_bcl24_ops[0],
562 
  & sfmt_cmp_ops[0],
563 
  & sfmt_cmpi_ops[0],
564 
  & sfmt_cmp_ops[0],
565 
  & sfmt_cmpi_ops[0],
566 
  & sfmt_cmp_ops[0],
567 
  & sfmt_cmpz_ops[0],
568 
  & sfmt_div_ops[0],
569 
  & sfmt_div_ops[0],
570 
  & sfmt_div_ops[0],
571 
  & sfmt_div_ops[0],
572 
  & sfmt_div_ops[0],
573 
  & sfmt_jc_ops[0],
574 
  & sfmt_jc_ops[0],
575 
  & sfmt_jl_ops[0],
576 
  & sfmt_jmp_ops[0],
577 
  & sfmt_ld_ops[0],
578 
  & sfmt_ld_d_ops[0],
579 
  & sfmt_ld_ops[0],
580 
  & sfmt_ld_d_ops[0],
581 
  & sfmt_ld_ops[0],
582 
  & sfmt_ld_d_ops[0],
583 
  & sfmt_ld_ops[0],
584 
  & sfmt_ld_d_ops[0],
585 
  & sfmt_ld_ops[0],
586 
  & sfmt_ld_d_ops[0],
587 
  & sfmt_ld_plus_ops[0],
588 
  & sfmt_ld24_ops[0],
589 
  & sfmt_ldi8_ops[0],
590 
  & sfmt_ldi16_ops[0],
591 
  & sfmt_lock_ops[0],
592 
  & sfmt_machi_ops[0],
593 
  & sfmt_machi_a_ops[0],
594 
  & sfmt_machi_ops[0],
595 
  & sfmt_machi_a_ops[0],
596 
  & sfmt_machi_ops[0],
597 
  & sfmt_machi_a_ops[0],
598 
  & sfmt_machi_ops[0],
599 
  & sfmt_machi_a_ops[0],
600 
  & sfmt_add_ops[0],
601 
  & sfmt_mulhi_ops[0],
602 
  & sfmt_mulhi_a_ops[0],
603 
  & sfmt_mulhi_ops[0],
604 
  & sfmt_mulhi_a_ops[0],
605 
  & sfmt_mulhi_ops[0],
606 
  & sfmt_mulhi_a_ops[0],
607 
  & sfmt_mulhi_ops[0],
608 
  & sfmt_mulhi_a_ops[0],
609 
  & sfmt_mv_ops[0],
610 
  & sfmt_mvfachi_ops[0],
611 
  & sfmt_mvfachi_a_ops[0],
612 
  & sfmt_mvfachi_ops[0],
613 
  & sfmt_mvfachi_a_ops[0],
614 
  & sfmt_mvfachi_ops[0],
615 
  & sfmt_mvfachi_a_ops[0],
616 
  & sfmt_mvfc_ops[0],
617 
  & sfmt_mvtachi_ops[0],
618 
  & sfmt_mvtachi_a_ops[0],
619 
  & sfmt_mvtachi_ops[0],
620 
  & sfmt_mvtachi_a_ops[0],
621 
  & sfmt_mvtc_ops[0],
622 
  & sfmt_mv_ops[0],
623 
  & sfmt_nop_ops[0],
624 
  & sfmt_mv_ops[0],
625 
  & sfmt_rac_ops[0],
626 
  & sfmt_rac_dsi_ops[0],
627 
  & sfmt_rac_ops[0],
628 
  & sfmt_rac_dsi_ops[0],
629 
  & sfmt_rte_ops[0],
630 
  & sfmt_seth_ops[0],
631 
  & sfmt_add_ops[0],
632 
  & sfmt_sll3_ops[0],
633 
  & sfmt_slli_ops[0],
634 
  & sfmt_add_ops[0],
635 
  & sfmt_sll3_ops[0],
636 
  & sfmt_slli_ops[0],
637 
  & sfmt_add_ops[0],
638 
  & sfmt_sll3_ops[0],
639 
  & sfmt_slli_ops[0],
640 
  & sfmt_st_ops[0],
641 
  & sfmt_st_d_ops[0],
642 
  & sfmt_stb_ops[0],
643 
  & sfmt_stb_d_ops[0],
644 
  & sfmt_sth_ops[0],
645 
  & sfmt_sth_d_ops[0],
646 
  & sfmt_st_plus_ops[0],
647 
  & sfmt_st_plus_ops[0],
648 
  & sfmt_add_ops[0],
649 
  & sfmt_addv_ops[0],
650 
  & sfmt_addx_ops[0],
651 
  & sfmt_trap_ops[0],
652 
  & sfmt_unlock_ops[0],
653 
  & sfmt_satb_ops[0],
654 
  & sfmt_satb_ops[0],
655 
  & sfmt_sat_ops[0],
656 
  & sfmt_cmpz_ops[0],
657 
  & sfmt_sadd_ops[0],
658 
  & sfmt_macwu1_ops[0],
659 
  & sfmt_machi_ops[0],
660 
  & sfmt_mulwu1_ops[0],
661 
  & sfmt_macwu1_ops[0],
662 
  & sfmt_sc_ops[0],
663 
  & sfmt_sc_ops[0],
664 
};
665 
 
666 
/* Function to call before using the operand instance table.  */
667 
 
668 
void
669 
m32r_cgen_init_opinst_table (cd)
670 
     CGEN_CPU_DESC cd;
671 
{
672 
  int i;
673 
  const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
674 
  CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
675 
  for (i = 0; i < MAX_INSNS; ++i)
676 
    insns[i].opinst = oi[i];
677 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.