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[/] [or1k/] [trunk/] [insight/] [opcodes/] [mips-opc.c] - Blame information for rev 1780

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1 578 markom 
/* mips-opc.c -- MIPS opcode list.
2 
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 
   Free Software Foundation, Inc.
4 
   Contributed by Ralph Campbell and OSF
5 
   Commented and modified by Ian Lance Taylor, Cygnus Support
6 
   Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
7 
 
8 
This file is part of GDB, GAS, and the GNU binutils.
9 
 
10 
GDB, GAS, and the GNU binutils are free software; you can redistribute
11 
them and/or modify them under the terms of the GNU General Public
12 
License as published by the Free Software Foundation; either version
13 
1, or (at your option) any later version.
14 
 
15 
GDB, GAS, and the GNU binutils are distributed in the hope that they
16 
will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
18 
the GNU General Public License for more details.
19 
 
20 
You should have received a copy of the GNU General Public License
21 
along with this file; see the file COPYING.  If not, write to the Free
22 
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
23 
 
24 
#include <stdio.h>
25 
#include "sysdep.h"
26 
#include "opcode/mips.h"
27 
 
28 
/* Short hand so the lines aren't too long.  */
29 
 
30 
#define LDD     INSN_LOAD_MEMORY_DELAY
31 
#define LCD     INSN_LOAD_COPROC_DELAY
32 
#define UBD     INSN_UNCOND_BRANCH_DELAY
33 
#define CBD     INSN_COND_BRANCH_DELAY
34 
#define COD     INSN_COPROC_MOVE_DELAY
35 
#define CLD     INSN_COPROC_MEMORY_DELAY
36 
#define CBL     INSN_COND_BRANCH_LIKELY
37 
#define TRAP    INSN_TRAP
38 
#define SM      INSN_STORE_MEMORY
39 
 
40 
#define WR_d    INSN_WRITE_GPR_D
41 
#define WR_t    INSN_WRITE_GPR_T
42 
#define WR_31   INSN_WRITE_GPR_31
43 
#define WR_D    INSN_WRITE_FPR_D
44 
#define WR_T    INSN_WRITE_FPR_T
45 
#define WR_S    INSN_WRITE_FPR_S
46 
#define RD_s    INSN_READ_GPR_S
47 
#define RD_b    INSN_READ_GPR_S
48 
#define RD_t    INSN_READ_GPR_T
49 
#define RD_S    INSN_READ_FPR_S
50 
#define RD_T    INSN_READ_FPR_T
51 
#define RD_R    INSN_READ_FPR_R
52 
#define WR_CC   INSN_WRITE_COND_CODE
53 
#define RD_CC   INSN_READ_COND_CODE
54 
#define RD_C0   INSN_COP
55 
#define RD_C1   INSN_COP
56 
#define RD_C2   INSN_COP
57 
#define RD_C3   INSN_COP
58 
#define WR_C0   INSN_COP
59 
#define WR_C1   INSN_COP
60 
#define WR_C2   INSN_COP
61 
#define WR_C3   INSN_COP
62 
 
63 
#define WR_HI   INSN_WRITE_HI
64 
#define RD_HI   INSN_READ_HI
65 
#define MOD_HI  WR_HI|RD_HI
66 
 
67 
#define WR_LO   INSN_WRITE_LO
68 
#define RD_LO   INSN_READ_LO
69 
#define MOD_LO  WR_LO|RD_LO
70 
 
71 
#define WR_HILO WR_HI|WR_LO
72 
#define RD_HILO RD_HI|RD_LO
73 
#define MOD_HILO WR_HILO|RD_HILO
74 
 
75 
#define IS_M    INSN_MULT
76 
 
77 
#define I1      INSN_ISA1
78 
#define I2      INSN_ISA2
79 
#define I3      INSN_ISA3
80 
#define I4      INSN_ISA4
81 
#define I5      INSN_ISA5
82 
#define I32     INSN_ISA32
83 
#define I64     INSN_ISA64
84 
 
85 
#define P3      INSN_4650
86 
#define L1      INSN_4010
87 
#define V1      INSN_4100
88 
#define T3      INSN_3900
89 
 
90 
#define G1      (T3             \
91 
                 )
92 
 
93 
#define G2      (T3                   \
94 
                 )
95 
 
96 
#define G3 (I4             \
97 
            )
98 
 
99 
#define G6      INSN_GP32
100 
 
101 
/* The order of overloaded instructions matters.  Label arguments and
102 
   register arguments look the same. Instructions that can have either
103 
   for arguments must apear in the correct order in this table for the
104 
   assembler to pick the right one. In other words, entries with
105 
   immediate operands must apear after the same instruction with
106 
   registers.
107 
 
108 
   Many instructions are short hand for other instructions (i.e., The
109 
   jal <register> instruction is short for jalr <register>).  */
110 
 
111 
const struct mips_opcode mips_builtin_opcodes[] =
112 
{
113 
/* These instructions appear first so that the disassembler will find
114 
   them first.  The assemblers uses a hash table based on the
115 
   instruction name anyhow.  */
116 
/* name,    args,       match,      mask,       pinfo,                  membership */
117 
{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   I32|G3  },
118 
{"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              I4      },
119 
{"nop",     "",         0x00000000, 0xffffffff, 0,               I1      },
120 
{"ssnop",   "",         0x00000040, 0xffffffff, 0,               I32     },
121 
{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   I1      }, /* addiu */
122 
{"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   I1      }, /* ori */
123 
{"li",      "t,I",      0,    (int) M_LI,        INSN_MACRO,             I1      },
124 
{"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              I1|G6   },/* or */
125 
{"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              I3      },/* daddu */
126 
{"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              I1      },/* addu */
127 
{"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              I1      },/* or */
128 
{"b",       "p",        0x10000000, 0xffff0000, UBD,                    I1      },/* beq 0,0 */
129 
{"b",       "p",        0x04010000, 0xffff0000, UBD,                    I1      },/* bgez 0 */
130 
{"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              I1      },/* bgezal 0*/
131 
 
132 
{"abs",     "d,v",      0,    (int) M_ABS,       INSN_MACRO,             I1      },
133 
{"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
134 
{"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
135 
{"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
136 
{"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
137 
{"add",     "t,r,I",    0,    (int) M_ADD_I,     INSN_MACRO,             I1      },
138 
{"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
139 
{"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
140 
{"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
141 
{"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              I1      },
142 
{"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              I1      },
143 
{"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
144 
{"addu",    "t,r,I",    0,    (int) M_ADDU_I,    INSN_MACRO,             I1      },
145 
{"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    I5      },
146 
{"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
147 
{"and",     "t,r,I",    0,    (int) M_AND_I,     INSN_MACRO,             I1      },
148 
{"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              I1      },
149 
/* b is at the top of the table.  */
150 
/* bal is at the top of the table.  */
151 
{"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              I1      },
152 
{"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
153 
{"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
154 
{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         I4|I32  },
155 
{"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
156 
{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         I4|I32  },
157 
{"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              I1      },
158 
{"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
159 
{"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              I1      },
160 
{"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
161 
{"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              I1      },
162 
{"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
163 
{"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
164 
{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         I4|I32  },
165 
{"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
166 
{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         I4|I32  },
167 
{"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              I1      },
168 
{"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
169 
{"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              I1      },
170 
{"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
171 
{"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               I1      },
172 
{"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
173 
{"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          I1      },
174 
{"beq",     "s,I,p",    0,    (int) M_BEQ_I,     INSN_MACRO,             I1      },
175 
{"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          I2|T3   },
176 
{"beql",    "s,I,p",    0,    (int) M_BEQL_I,    INSN_MACRO,             I2      },
177 
{"bge",     "s,t,p",    0,    (int) M_BGE,       INSN_MACRO,             I1      },
178 
{"bge",     "s,I,p",    0,    (int) M_BGE_I,     INSN_MACRO,             I1      },
179 
{"bgel",    "s,t,p",    0,    (int) M_BGEL,      INSN_MACRO,             I2      },
180 
{"bgel",    "s,I,p",    0,    (int) M_BGEL_I,    INSN_MACRO,             I2      },
181 
{"bgeu",    "s,t,p",    0,    (int) M_BGEU,      INSN_MACRO,             I1      },
182 
{"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,    INSN_MACRO,             I1      },
183 
{"bgeul",   "s,t,p",    0,    (int) M_BGEUL,     INSN_MACRO,             I2      },
184 
{"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,   INSN_MACRO,             I2      },
185 
{"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               I1      },
186 
{"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
187 
{"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         I1      },
188 
{"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
189 
{"bgt",     "s,t,p",    0,    (int) M_BGT,       INSN_MACRO,             I1      },
190 
{"bgt",     "s,I,p",    0,    (int) M_BGT_I,     INSN_MACRO,             I1      },
191 
{"bgtl",    "s,t,p",    0,    (int) M_BGTL,      INSN_MACRO,             I2      },
192 
{"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,    INSN_MACRO,             I2      },
193 
{"bgtu",    "s,t,p",    0,    (int) M_BGTU,      INSN_MACRO,             I1      },
194 
{"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,    INSN_MACRO,             I1      },
195 
{"bgtul",   "s,t,p",    0,    (int) M_BGTUL,     INSN_MACRO,             I2      },
196 
{"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,   INSN_MACRO,             I2      },
197 
{"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               I1      },
198 
{"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
199 
{"ble",     "s,t,p",    0,    (int) M_BLE,       INSN_MACRO,             I1      },
200 
{"ble",     "s,I,p",    0,    (int) M_BLE_I,     INSN_MACRO,             I1      },
201 
{"blel",    "s,t,p",    0,    (int) M_BLEL,      INSN_MACRO,             I2      },
202 
{"blel",    "s,I,p",    0,    (int) M_BLEL_I,    INSN_MACRO,             I2      },
203 
{"bleu",    "s,t,p",    0,    (int) M_BLEU,      INSN_MACRO,             I1      },
204 
{"bleu",    "s,I,p",    0,    (int) M_BLEU_I,    INSN_MACRO,             I1      },
205 
{"bleul",   "s,t,p",    0,    (int) M_BLEUL,     INSN_MACRO,             I2      },
206 
{"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,   INSN_MACRO,             I2      },
207 
{"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               I1      },
208 
{"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
209 
{"blt",     "s,t,p",    0,    (int) M_BLT,       INSN_MACRO,             I1      },
210 
{"blt",     "s,I,p",    0,    (int) M_BLT_I,     INSN_MACRO,             I1      },
211 
{"bltl",    "s,t,p",    0,    (int) M_BLTL,      INSN_MACRO,             I2      },
212 
{"bltl",    "s,I,p",    0,    (int) M_BLTL_I,    INSN_MACRO,             I2      },
213 
{"bltu",    "s,t,p",    0,    (int) M_BLTU,      INSN_MACRO,             I1      },
214 
{"bltu",    "s,I,p",    0,    (int) M_BLTU_I,    INSN_MACRO,             I1      },
215 
{"bltul",   "s,t,p",    0,    (int) M_BLTUL,     INSN_MACRO,             I2      },
216 
{"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,   INSN_MACRO,             I2      },
217 
{"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               I1      },
218 
{"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
219 
{"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         I1      },
220 
{"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
221 
{"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               I1      },
222 
{"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
223 
{"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          I1      },
224 
{"bne",     "s,I,p",    0,    (int) M_BNE_I,     INSN_MACRO,             I1      },
225 
{"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          I2|T3   },
226 
{"bnel",    "s,I,p",    0,    (int) M_BNEL_I,    INSN_MACRO,             I2      },
227 
{"break",   "",         0x0000000d, 0xffffffff, TRAP,                   I1      },
228 
{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,                   I32     },
229 
{"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   I1      },
230 
{"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   I1      },
231 
{"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
232 
{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
233 
{"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
234 
{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
235 
{"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
236 
{"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
237 
{"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
238 
{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
239 
{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
240 
{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
241 
{"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
242 
{"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
243 
{"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
244 
{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
245 
{"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
246 
{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
247 
{"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
248 
{"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
249 
{"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
250 
{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
251 
{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
252 
{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
253 
{"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
254 
{"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
255 
{"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
256 
{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
257 
{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
258 
{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
259 
{"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
260 
{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
261 
{"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
262 
{"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
263 
{"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
264 
{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
265 
{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
266 
{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
267 
{"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
268 
{"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
269 
{"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
270 
{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
271 
{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
272 
{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
273 
{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
274 
{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
275 
{"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
276 
{"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
277 
{"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
278 
{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
279 
{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
280 
{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
281 
{"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
282 
{"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
283 
{"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
284 
{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
285 
{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
286 
{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
287 
{"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
288 
{"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
289 
{"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
290 
{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
291 
{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
292 
{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
293 
{"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
294 
{"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
295 
{"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
296 
{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
297 
{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
298 
{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
299 
{"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
300 
{"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
301 
{"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
302 
{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
303 
{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
304 
{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
305 
{"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
306 
{"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
307 
{"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
308 
{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
309 
{"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
310 
{"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
311 
{"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
312 
{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
313 
{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
314 
{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
315 
{"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
316 
{"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
317 
{"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
318 
{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
319 
{"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
320 
{"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
321 
{"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
322 
{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32  },
323 
{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
324 
{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32  },
325 
{"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
326 
{"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
327 
{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   I3|I32|T3},
328 
{"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
329 
{"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
330 
{"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
331 
{"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
332 
{"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
333 
{"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
334 
{"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
335 
{"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         I1      },
336 
{"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         I1      },
337 
{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         I32     },
338 
{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         I32     },
339 
{"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
340 
{"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
341 
{"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
342 
{"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
343 
{"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
344 
{"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
345 
{"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S,    I1      },
346 
{"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
347 
{"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
348 
{"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
349 
{"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
350 
{"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I1      },
351 
{"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
352 
{"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
353 
{"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
354 
{"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
355 
{"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
356 
{"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
357 
{"dabs",    "d,v",      0,    (int) M_DABS,      INSN_MACRO,             I3      },
358 
{"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
359 
{"dadd",    "t,r,I",    0,    (int) M_DADD_I,    INSN_MACRO,             I3      },
360 
{"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              I3      },
361 
{"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              I3      },
362 
{"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
363 
{"daddu",   "t,r,I",    0,    (int) M_DADDU_I,   INSN_MACRO,             I3      },
364 
{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         I64     },
365 
{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         I64     },
366 
/* dctr and dctw are used on the r5000.  */
367 
{"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   I3      },
368 
{"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   I3      },
369 
{"deret",   "",         0x4200001f, 0xffffffff, 0,                       I32|G2  },
370 
/* For ddiv, see the comments about div.  */
371 
{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
372 
{"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,    INSN_MACRO,             I3      },
373 
{"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,   INSN_MACRO,             I3      },
374 
/* For ddivu, see the comments about div.  */
375 
{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
376 
{"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,   INSN_MACRO,             I3      },
377 
{"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I,  INSN_MACRO,             I3      },
378 
/* The MIPS assembler treats the div opcode with two operands as
379 
   though the first operand appeared twice (the first operand is both
380 
   a source and a destination).  To get the div machine instruction,
381 
   you must use an explicit destination of $0.  */
382 
{"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
383 
{"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
384 
{"div",     "d,v,t",    0,    (int) M_DIV_3,     INSN_MACRO,             I1      },
385 
{"div",     "d,v,I",    0,    (int) M_DIV_3I,    INSN_MACRO,             I1      },
386 
{"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
387 
{"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
388 
/* For divu, see the comments about div.  */
389 
{"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
390 
{"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
391 
{"divu",    "d,v,t",    0,    (int) M_DIVU_3,    INSN_MACRO,             I1      },
392 
{"divu",    "d,v,I",    0,    (int) M_DIVU_3I,   INSN_MACRO,             I1      },
393 
{"dla",     "t,o(b)",   0x64000000, 0xfc000000, WR_t|RD_s,              I3      }, /* daddiu */
394 
{"dla",     "t,A(b)",   0,    (int) M_DLA_AB,    INSN_MACRO,             I3      },
395 
{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   I3      }, /* addiu */
396 
{"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   I3      }, /* ori */
397 
{"dli",     "t,I",      0,    (int) M_DLI,       INSN_MACRO,             I3      },
398 
 
399 
{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       V1      },
400 
{"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         I3      },
401 
{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         I64     },
402 
{"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I3      },
403 
{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
404 
{"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
405 
{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
406 
{"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I3      },
407 
{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I3      },
408 
{"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         I3      },
409 
{"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         I64     },
410 
{"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I3      },
411 
{"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I64     },
412 
{"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         I3      },
413 
{"dmfc3",   "t,G,H",    0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3,         I64     },
414 
{"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I3      },
415 
{"dmtc3",   "t,G,H",    0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I64     },
416 
{"dmul",    "d,v,t",    0,    (int) M_DMUL,      INSN_MACRO,             I3      },
417 
{"dmul",    "d,v,I",    0,    (int) M_DMUL_I,    INSN_MACRO,             I3      },
418 
{"dmulo",   "d,v,t",    0,    (int) M_DMULO,     INSN_MACRO,             I3      },
419 
{"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,   INSN_MACRO,             I3      },
420 
{"dmulou",  "d,v,t",    0,    (int) M_DMULOU,    INSN_MACRO,             I3      },
421 
{"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I,  INSN_MACRO,             I3      },
422 
{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
423 
{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
424 
{"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              I3      }, /* dsub 0 */
425 
{"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              I3      }, /* dsubu 0*/
426 
{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
427 
{"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             I3      },
428 
{"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             I3      },
429 
{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
430 
{"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             I3      },
431 
{"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             I3      },
432 
{"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
433 
{"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      },
434 
{"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsllv */
435 
{"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsll32 */
436 
{"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              I3      },
437 
{"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
438 
{"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              I3      },
439 
{"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsrav */
440 
{"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsra32 */
441 
{"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              I3      },
442 
{"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
443 
{"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              I3      },
444 
{"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsrlv */
445 
{"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsrl32 */
446 
{"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              I3      },
447 
{"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
448 
{"dsub",    "d,v,I",    0,    (int) M_DSUB_I,    INSN_MACRO,             I3      },
449 
{"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
450 
{"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,   INSN_MACRO,             I3      },
451 
{"eret",    "",         0x42000018, 0xffffffff, 0,               I3|I32  },
452 
{"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
453 
{"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
454 
{"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
455 
{"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
456 
{"flushi",  "",         0xbc010000, 0xffffffff, 0,                       L1      },
457 
{"flushd",  "",         0xbc020000, 0xffffffff, 0,                       L1      },
458 
{"flushid", "",         0xbc030000, 0xffffffff, 0,                       L1      },
459 
{"hibernate","",        0x42000023, 0xffffffff, 0,                       V1      },
460 
{"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               I1      },
461 
{"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               I1      }, /* jr */
462 
/* SVR4 PIC code requires special handling for j, so it must be a
463 
   macro.  */
464 
{"j",       "a",        0,     (int) M_J_A,      INSN_MACRO,             I1      },
465 
/* This form of j is used by the disassembler and internally by the
466 
   assembler, but will never match user input (because the line above
467 
   will match first).  */
468 
{"j",       "a",        0x08000000, 0xfc000000, UBD,                    I1      },
469 
{"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          I1      },
470 
{"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          I1      },
471 
/* SVR4 PIC code requires special handling for jal, so it must be a
472 
   macro.  */
473 
{"jal",     "d,s",      0,     (int) M_JAL_2,    INSN_MACRO,             I1      },
474 
{"jal",     "s",        0,     (int) M_JAL_1,    INSN_MACRO,             I1      },
475 
{"jal",     "a",        0,     (int) M_JAL_A,    INSN_MACRO,             I1      },
476 
/* This form of jal is used by the disassembler and internally by the
477 
   assembler, but will never match user input (because the line above
478 
   will match first).  */
479 
{"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              I1      },
480 
  /* jalx really should only be avaliable if mips16 is available,
481 
     but for now make it I1. */
482 
{"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              I1      },
483 
{"la",      "t,o(b)",   0x24000000, 0xfc000000, WR_t|RD_s,              I1      }, /* addiu */
484 
{"la",      "t,A(b)",   0,    (int) M_LA_AB,     INSN_MACRO,             I1      },
485 
{"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
486 
{"lb",      "t,A(b)",   0,    (int) M_LB_AB,     INSN_MACRO,             I1      },
487 
{"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
488 
{"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,    INSN_MACRO,             I1      },
489 
{"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              I3      },
490 
{"ld",      "t,o(b)",   0,    (int) M_LD_OB,     INSN_MACRO,             I1      },
491 
{"ld",      "t,A(b)",   0,    (int) M_LD_AB,     INSN_MACRO,             I1      },
492 
{"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      },
493 
{"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      },
494 
{"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,   INSN_MACRO,             I2      },
495 
{"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,   INSN_MACRO,             I2      },
496 
{"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      }, /* ldc1 */
497 
{"l.d",     "T,o(b)",   0,    (int) M_L_DOB,     INSN_MACRO,             I1      },
498 
{"l.d",     "T,A(b)",   0,    (int) M_L_DAB,     INSN_MACRO,             I1      },
499 
{"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         I2      },
500 
{"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,   INSN_MACRO,             I2      },
501 
{"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         I2      },
502 
{"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,   INSN_MACRO,             I2      },
503 
{"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          I3      },
504 
{"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,    INSN_MACRO,             I3      },
505 
{"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          I3      },
506 
{"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,    INSN_MACRO,             I3      },
507 
{"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
508 
{"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
509 
{"lh",      "t,A(b)",   0,    (int) M_LH_AB,     INSN_MACRO,             I1      },
510 
{"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
511 
{"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,    INSN_MACRO,             I1      },
512 
/* li is at the start of the table.  */
513 
{"li.d",    "t,F",      0,    (int) M_LI_D,      INSN_MACRO,             I1      },
514 
{"li.d",    "T,L",      0,    (int) M_LI_DD,     INSN_MACRO,             I1      },
515 
{"li.s",    "t,f",      0,    (int) M_LI_S,      INSN_MACRO,             I1      },
516 
{"li.s",    "T,l",      0,    (int) M_LI_SS,     INSN_MACRO,             I1      },
517 
{"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          I2      },
518 
{"ll",      "t,A(b)",   0,    (int) M_LL_AB,     INSN_MACRO,             I2      },
519 
{"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          I3      },
520 
{"lld",     "t,A(b)",   0,    (int) M_LLD_AB,    INSN_MACRO,             I3      },
521 
{"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   I1      },
522 
{"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I5      },
523 
{"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
524 
{"lw",      "t,A(b)",   0,    (int) M_LW_AB,     INSN_MACRO,             I1      },
525 
{"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
526 
{"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,   INSN_MACRO,             I1      },
527 
{"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      },
528 
{"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      },
529 
{"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             I1      },
530 
{"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             I1      },
531 
{"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      }, /* lwc1 */
532 
{"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             I1      },
533 
{"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
534 
{"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,   INSN_MACRO,             I1      },
535 
{"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
536 
{"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,   INSN_MACRO,             I1      },
537 
{"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
538 
{"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,    INSN_MACRO,             I1      },
539 
{"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          I2      }, /* same */
540 
{"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,    INSN_MACRO,             I2      }, /* as lwl */
541 
{"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
542 
{"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,    INSN_MACRO,             I1      },
543 
{"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          I2      }, /* same */
544 
{"flush",   "t,A(b)",   0,    (int) M_LWR_AB,    INSN_MACRO,             I2      }, /* as lwr */
545 
{"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          I3      },
546 
{"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,    INSN_MACRO,             I3      },
547 
{"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
548 
{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
549 
{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
550 
{"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I4 },
551 
{"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    I4 },
552 
{"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I5 },
553 
{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
554 
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
555 
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1 },
556 
{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
557 
{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
558 
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
559 
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1 },
560 
{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
561 
{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          V1 },
562 
{"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
563 
{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         I32     },
564 
{"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
565 
{"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
566 
{"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         I1      },
567 
{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         I32     },
568 
{"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         I1      },
569 
{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         I32     },
570 
{"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             I1      },
571 
{"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             I1      },
572 
{"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
573 
{"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
574 
{"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
575 
{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
576 
{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32  },
577 
{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32  },
578 
{"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
579 
{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         I4|I32  },
580 
{"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              L1      },
581 
{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32  },
582 
{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32  },
583 
{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32  },
584 
{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32  },
585 
{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32  },
586 
{"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
587 
{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         I4|I32  },
588 
{"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              L1      },
589 
{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32  },
590 
{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32  },
591 
/* move is at the top of the table.  */
592 
{"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
593 
{"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
594 
{"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
595 
{"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      L1      },
596 
{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
597 
{"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      L1      },
598 
{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
599 
{"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
600 
{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
601 
{"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
602 
{"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
603 
{"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I1      },
604 
{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
605 
{"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I1      },
606 
{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
607 
{"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             I1      },
608 
{"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             I1      },
609 
{"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
610 
{"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
611 
{"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
612 
{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3  },
613 
{"mul",     "d,v,t",    0,    (int) M_MUL,       INSN_MACRO,             I1      },
614 
{"mul",     "d,v,I",    0,    (int) M_MUL_I,     INSN_MACRO,             I1      },
615 
{"mulo",    "d,v,t",    0,    (int) M_MULO,      INSN_MACRO,             I1      },
616 
{"mulo",    "d,v,I",    0,    (int) M_MULO_I,    INSN_MACRO,             I1      },
617 
{"mulou",   "d,v,t",    0,    (int) M_MULOU,     INSN_MACRO,             I1      },
618 
{"mulou",   "d,v,I",    0,    (int) M_MULOU_I,   INSN_MACRO,             I1      },
619 
{"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1      },
620 
{"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
621 
{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1      },
622 
{"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
623 
{"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              I1      }, /* sub 0 */
624 
{"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              I1      }, /* subu 0 */
625 
{"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
626 
{"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
627 
{"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
628 
{"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
629 
{"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
630 
{"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
631 
{"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
632 
{"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
633 
{"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
634 
/* nop is at the start of the table.  */
635 
{"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
636 
{"nor",     "t,r,I",    0,    (int) M_NOR_I,     INSN_MACRO,             I1      },
637 
{"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         I1      },/*nor d,s,0*/
638 
{"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
639 
{"or",      "t,r,I",    0,    (int) M_OR_I,      INSN_MACRO,             I1      },
640 
{"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              I1      },
641 
 
642 
{"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
643 
{"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
644 
 
645 
  /* pref and prefx are at the start of the table.  */
646 
 
647 
{"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
648 
{"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
649 
 
650 
{"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
651 
{"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
652 
{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
653 
{"rem",     "d,v,t",    0,    (int) M_REM_3,     INSN_MACRO,             I1      },
654 
{"rem",     "d,v,I",    0,    (int) M_REM_3I,    INSN_MACRO,             I1      },
655 
{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
656 
{"remu",    "d,v,t",    0,    (int) M_REMU_3,    INSN_MACRO,             I1      },
657 
{"remu",    "d,v,I",    0,    (int) M_REMU_3I,   INSN_MACRO,             I1      },
658 
{"rfe",     "",         0x42000010, 0xffffffff, 0,                       I1|T3   },
659 
{"rol",     "d,v,t",    0,    (int) M_ROL,       INSN_MACRO,             I1      },
660 
{"rol",     "d,v,I",    0,    (int) M_ROL_I,     INSN_MACRO,             I1      },
661 
{"ror",     "d,v,t",    0,    (int) M_ROR,       INSN_MACRO,             I1      },
662 
{"ror",     "d,v,I",    0,    (int) M_ROR_I,     INSN_MACRO,             I1      },
663 
{"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
664 
{"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
665 
{"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
666 
{"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
667 
{"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
668 
{"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
669 
{"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
670 
{"sb",      "t,A(b)",   0,    (int) M_SB_AB,     INSN_MACRO,             I1      },
671 
{"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I2      },
672 
{"sc",      "t,A(b)",   0,    (int) M_SC_AB,     INSN_MACRO,             I2      },
673 
{"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I3      },
674 
{"scd",     "t,A(b)",   0,    (int) M_SCD_AB,    INSN_MACRO,             I3      },
675 
{"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
676 
{"sd",      "t,o(b)",   0,    (int) M_SD_OB,     INSN_MACRO,             I1      },
677 
{"sd",      "t,A(b)",   0,    (int) M_SD_AB,     INSN_MACRO,             I1      },
678 
{"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   G2      },
679 
{"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   G2      },
680 
{"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   G2      },
681 
{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   I32     },
682 
{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   I32     },
683 
{"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
684 
{"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
685 
{"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,   INSN_MACRO,             I2      },
686 
{"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,   INSN_MACRO,             I2      },
687 
{"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          I2      },
688 
{"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,   INSN_MACRO,             I2      },
689 
{"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          I2      },
690 
{"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,   INSN_MACRO,             I2      },
691 
{"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
692 
{"s.d",     "T,o(b)",   0,    (int) M_S_DOB,     INSN_MACRO,             I1      },
693 
{"s.d",     "T,A(b)",   0,    (int) M_S_DAB,     INSN_MACRO,             I1      },
694 
{"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
695 
{"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,    INSN_MACRO,             I3      },
696 
{"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
697 
{"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,    INSN_MACRO,             I3      },
698 
{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      I4      },
699 
{"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
700 
{"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
701 
{"seq",     "d,v,t",    0,    (int) M_SEQ,       INSN_MACRO,             I1      },
702 
{"seq",     "d,v,I",    0,    (int) M_SEQ_I,     INSN_MACRO,             I1      },
703 
{"sge",     "d,v,t",    0,    (int) M_SGE,       INSN_MACRO,             I1      },
704 
{"sge",     "d,v,I",    0,    (int) M_SGE_I,     INSN_MACRO,             I1      },
705 
{"sgeu",    "d,v,t",    0,    (int) M_SGEU,      INSN_MACRO,             I1      },
706 
{"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,    INSN_MACRO,             I1      },
707 
{"sgt",     "d,v,t",    0,    (int) M_SGT,       INSN_MACRO,             I1      },
708 
{"sgt",     "d,v,I",    0,    (int) M_SGT_I,     INSN_MACRO,             I1      },
709 
{"sgtu",    "d,v,t",    0,    (int) M_SGTU,      INSN_MACRO,             I1      },
710 
{"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,    INSN_MACRO,             I1      },
711 
{"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
712 
{"sh",      "t,A(b)",   0,    (int) M_SH_AB,     INSN_MACRO,             I1      },
713 
{"sle",     "d,v,t",    0,    (int) M_SLE,       INSN_MACRO,             I1      },
714 
{"sle",     "d,v,I",    0,    (int) M_SLE_I,     INSN_MACRO,             I1      },
715 
{"sleu",    "d,v,t",    0,    (int) M_SLEU,      INSN_MACRO,             I1      },
716 
{"sleu",    "d,v,I",    0,    (int) M_SLEU_I,    INSN_MACRO,             I1      },
717 
{"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
718 
{"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* sllv */
719 
{"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              I1      },
720 
{"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
721 
{"slt",     "d,v,I",    0,    (int) M_SLT_I,     INSN_MACRO,             I1      },
722 
{"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              I1      },
723 
{"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              I1      },
724 
{"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
725 
{"sltu",    "d,v,I",    0,    (int) M_SLTU_I,    INSN_MACRO,             I1      },
726 
{"sne",     "d,v,t",    0,    (int) M_SNE,       INSN_MACRO,             I1      },
727 
{"sne",     "d,v,I",    0,    (int) M_SNE_I,     INSN_MACRO,             I1      },
728 
{"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
729 
{"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
730 
{"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
731 
{"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* srav */
732 
{"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              I1      },
733 
{"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
734 
{"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* srlv */
735 
{"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              I1      },
736 
/* ssnop is at the start of the table.  */
737 
{"standby", "",         0x42000021, 0xffffffff, 0,                       V1      },
738 
{"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
739 
{"sub",     "d,v,I",    0,    (int) M_SUB_I,     INSN_MACRO,             I1      },
740 
{"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
741 
{"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
742 
{"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
743 
{"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
744 
{"subu",    "d,v,I",    0,    (int) M_SUBU_I,    INSN_MACRO,             I1      },
745 
{"suspend", "",         0x42000022, 0xffffffff, 0,                       V1      },
746 
{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      I5      },
747 
{"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
748 
{"sw",      "t,A(b)",   0,    (int) M_SW_AB,     INSN_MACRO,             I1      },
749 
{"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          I1      },
750 
{"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,   INSN_MACRO,             I1      },
751 
{"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      },
752 
{"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      },
753 
{"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             I1      },
754 
{"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             I1      },
755 
{"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      }, /* swc1 */
756 
{"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             I1      },
757 
{"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          I1      },
758 
{"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,   INSN_MACRO,             I1      },
759 
{"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          I1      },
760 
{"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,   INSN_MACRO,             I1      },
761 
{"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
762 
{"swl",     "t,A(b)",   0,    (int) M_SWL_AB,    INSN_MACRO,             I1      },
763 
{"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              I2      }, /* same */
764 
{"scache",  "t,A(b)",   0,    (int) M_SWL_AB,    INSN_MACRO,             I2      }, /* as swl */
765 
{"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
766 
{"swr",     "t,A(b)",   0,    (int) M_SWR_AB,    INSN_MACRO,             I1      },
767 
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              I2      }, /* same */
768 
{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,    INSN_MACRO,             I2      }, /* as swr */
769 
{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      I4      },
770 
{"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              I2|G1   },
771 
{"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              I2      },
772 
{"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              I2      },
773 
{"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   I1      },
774 
{"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   I1      },
775 
{"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              I2      },
776 
{"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
777 
{"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
778 
{"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* teqi */
779 
{"teq",     "s,I",      0,    (int) M_TEQ_I,     INSN_MACRO,             I2      },
780 
{"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              I2      },
781 
{"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
782 
{"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
783 
{"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tgei */
784 
{"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,              I2      },
785 
{"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              I2      },
786 
{"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
787 
{"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
788 
{"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tgeiu */
789 
{"tgeu",    "s,I",      0,    (int) M_TGEU_I,    INSN_MACRO,             I2      },
790 
{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               I1      },
791 
{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               I1      },
792 
{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               I1      },
793 
{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               I1      },
794 
{"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              I2      },
795 
{"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
796 
{"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
797 
{"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tlti */
798 
{"tlt",     "s,I",      0,    (int) M_TLT_I,     INSN_MACRO,             I2      },
799 
{"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              I2      },
800 
{"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
801 
{"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
802 
{"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tltiu */
803 
{"tltu",    "s,I",      0,    (int) M_TLTU_I,    INSN_MACRO,             I2      },
804 
{"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              I2      },
805 
{"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
806 
{"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
807 
{"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tnei */
808 
{"tne",     "s,I",      0,    (int) M_TNE_I,     INSN_MACRO,             I2      },
809 
{"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
810 
{"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
811 
{"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
812 
{"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
813 
{"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,   INSN_MACRO,             I1      },
814 
{"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
815 
{"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
816 
{"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,   INSN_MACRO,             I1      },
817 
{"uld",     "t,o(b)",   0,    (int) M_ULD,       INSN_MACRO,             I3      },
818 
{"uld",     "t,A(b)",   0,    (int) M_ULD_A,     INSN_MACRO,             I3      },
819 
{"ulh",     "t,o(b)",   0,    (int) M_ULH,       INSN_MACRO,             I1      },
820 
{"ulh",     "t,A(b)",   0,    (int) M_ULH_A,     INSN_MACRO,             I1      },
821 
{"ulhu",    "t,o(b)",   0,    (int) M_ULHU,      INSN_MACRO,             I1      },
822 
{"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,    INSN_MACRO,             I1      },
823 
{"ulw",     "t,o(b)",   0,    (int) M_ULW,       INSN_MACRO,             I1      },
824 
{"ulw",     "t,A(b)",   0,    (int) M_ULW_A,     INSN_MACRO,             I1      },
825 
{"usd",     "t,o(b)",   0,    (int) M_USD,       INSN_MACRO,             I3      },
826 
{"usd",     "t,A(b)",   0,    (int) M_USD_A,     INSN_MACRO,             I3      },
827 
{"ush",     "t,o(b)",   0,    (int) M_USH,       INSN_MACRO,             I1      },
828 
{"ush",     "t,A(b)",   0,    (int) M_USH_A,     INSN_MACRO,             I1      },
829 
{"usw",     "t,o(b)",   0,    (int) M_USW,       INSN_MACRO,             I1      },
830 
{"usw",     "t,A(b)",   0,    (int) M_USW_A,     INSN_MACRO,             I1      },
831 
{"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
832 
{"xor",     "t,r,I",    0,    (int) M_XOR_I,     INSN_MACRO,             I1      },
833 
{"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              I1      },
834 
{"wait",    "",         0x42000020, 0xffffffff, TRAP,                   I3|I32  },
835 
{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   I32     },
836 
{"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   L1      },
837 
{"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                L1      },
838 
/* No hazard protection on coprocessor instructions--they shouldn't
839 
   change the state of the processor and if they do it's up to the
840 
   user to put in nops as necessary.  These are at the end so that the
841 
   disasembler recognizes more specific versions first.  */
842 
{"c0",      "C",        0x42000000, 0xfe000000, 0,                       I1      },
843 
{"c1",      "C",        0x46000000, 0xfe000000, 0,                       I1      },
844 
{"c2",      "C",        0x4a000000, 0xfe000000, 0,                       I1      },
845 
{"c3",      "C",        0x4e000000, 0xfe000000, 0,                       I1      },
846 
{"cop0",     "C",       0,    (int) M_COP0,      INSN_MACRO,             I1      },
847 
{"cop1",     "C",       0,    (int) M_COP1,      INSN_MACRO,             I1      },
848 
{"cop2",     "C",       0,    (int) M_COP2,      INSN_MACRO,             I1      },
849 
{"cop3",     "C",       0,    (int) M_COP3,      INSN_MACRO,             I1      },
850 
 
851 
  /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
852 
     4010 any more, so move this insn out of the way.  If the object
853 
     format gave us more info, we could do this right.  */
854 
{"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              L1      },
855 
};
856 
 
857 
#define MIPS_NUM_OPCODES \
858 
        ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
859 
const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
860 
 
861 
/* const removed from the following to allow for dynamic extensions to the
862 
 * built-in instruction set. */
863 
struct mips_opcode *mips_opcodes =
864 
  (struct mips_opcode *) mips_builtin_opcodes;
865 
int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
866 
#undef MIPS_NUM_OPCODES

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