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[/] [or1k/] [trunk/] [insight/] [sim/] [d30v/] [d30v-insns] - Blame information for rev 1771

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1 578 markom 
//  -*- C -*-
2 
//  Mitsubishi Electric Corp. D30V Simulator.
3 
//  Copyright (C) 1997, Free Software Foundation, Inc.
4 
//  Contributed by Cygnus Solutions Inc.
5 
//
6 
//  This file is part of GDB, the GNU debugger.
7 
//
8 
//  This program is free software; you can redistribute it and/or modify
9 
//  it under the terms of the GNU General Public License as published by
10 
//  the Free Software Foundation; either version 2 of the License, or
11 
//  (at your option) any later version.
12 
//
13 
//  This program is distributed in the hope that it will be useful,
14 
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
//  GNU General Public License for more details.
17 
//
18 
//  You should have received a copy of the GNU General Public License
19 
//  along with this program; if not, write to the Free Software
20 
//  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 
//
22 
 
23 
 
24 
define( _BRA,  `1.*,CCC,000')
25 
define( _LOGIC, `1.*,CCC,001')
26 
define( _IMEM, `1.*,CCC,010')
27 
define( _IALU1, `1.*,CCC,100')
28 
define(_IALU2, `1.*,CCC,101')
29 
 
30 
 
31 
 
32 
define(_IMM6, `6.IMM_6S')
33 
define(_IMM12, `12.IMM_12S')
34 
define(_IMM18, `18.IMM_18S')
35 
define(_IMM32, `6.IMM_6L,*,000,8.IMM_8L,00,18.IMM_18L')
36 
 
37 
 
38 
 
39 
// The following is called when ever an illegal instruction is
40 
// encountered
41 
::internal::illegal
42 
        sim_io_eprintf (sd, "illegal instruction at 0x%lx\n", (long) cia);
43 
        sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
44 
 
45 
// The following is called when ever an instruction in the wrong
46 
// slot is encountered.
47 
::internal::wrong_slot
48 
        sim_io_eprintf (sd, "wrong slot at 0x%lx\n", (long) cia);
49 
        sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
50 
 
51 
 
52 
 
53 
// Something illegal that can be used to contact the simulator emul
54 
// library.
55 
define(_EMUL, `1.*,CCC,111')
56 
 
57 
void::function::do_emul:int imm
58 
        /* temp hack - later replace with real interface */
59 
        enum {
60 
          param1 = 2, param2, param3, param4
61 
        };
62 
        switch (imm) {
63 
        case 0:
64 
          {
65 
            sim_engine_abort (SD, CPU, cia, "UNIX call emulation unsupported");
66 
            break;
67 
          }
68 
        case 1:
69 
          /* Trap 1 - prints a string */
70 
          {
71 
            address_word str = GPR[param1];
72 
            char chr;
73 
            while (1) {
74 
              chr = MEM (unsigned, str, 1);
75 
            if (chr == '\0') break;
76 
              sim_io_write_stdout (sd, &chr, sizeof chr);
77 
              str++;
78 
            }
79 
            break;
80 
          }
81 
        case 3:
82 
          /* Trap 3 - writes a character */
83 
          {
84 
            char chr = GPR[param1];
85 
            sim_io_write_stdout (sd, &chr, sizeof chr);
86 
            break;
87 
          }
88 
        case 4:
89 
          /* Trap 4 exits with status in [param1] */
90 
          {
91 
            sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR[param1]);
92 
            break;
93 
          }
94 
        case 5:
95 
          /* Trap 5 breakpoints.  If the breakpoint system knows about this, it
96 
             won't return.  Otherwise, we fall through to treat this as an
97 
             unknown instruction.  */
98 
          {
99 
            sim_handle_breakpoint (SD, CPU, cia);
100 
          /* Fall through to default case.*/
101 
          }
102 
        default:
103 
          sim_engine_abort (SD, CPU, cia, "Unknown monitor call %d", imm);
104 
        }
105 
 
106 
_EMUL,00000,00,6.*,6.*,IMM_6S:EMUL:short,emul:iu,mu:EMUL
107 
"syscall "
108 
        do_emul (_SD, imm);
109 
_BRA,00000,00,6.**,6.**,_IMM32:BRA:long:iu,mu:EMUL long
110 
"syscall "
111 
        do_emul (_SD, imm);
112 
 
113 
// ABS
114 
 
115 
_IALU1,01000,00,6.RA,6.RB,6.**:IALU1:short:iu,mu:ABS
116 
"abs r, r"
117 
        WRITE32_QUEUE (Ra, abs(Rb));
118 
 
119 
 
120 
 
121 
// ADD
122 
 
123 
void::function::do_add:unsigned32 *ra, unsigned32 rb, unsigned32 imm
124 
        ALU_BEGIN(rb);
125 
        ALU_ADDC(imm);
126 
        ALU_END(ra);
127 
 
128 
_IALU1,00000,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD
129 
"add r, r, r"
130 
        do_add (_SD, Ra, Rb, Rc);
131 
_IALU1,00000,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD imm
132 
"add r, r, "
133 
        do_add (_SD, Ra, Rb, imm);
134 
_IALU1,00000,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD imm long
135 
"add r, r, "
136 
        do_add (_SD, Ra, Rb, imm);
137 
 
138 
 
139 
 
140 
// ADD2H
141 
 
142 
void::function::do_add2h:signed32 *ra, signed32 rb, signed32 imm
143 
        unsigned16 ah2 = VH2_4(rb) + VH2_4(imm);
144 
        unsigned16 al2 = VL2_4(rb) + VL2_4(imm);
145 
        WRITE32_QUEUE (ra, (ah2 << 16) | al2);
146 
 
147 
_IALU1,00001,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD2H
148 
"add2h r, r, r"
149 
        do_add2h (_SD, Ra, Rb, Rc);
150 
_IALU1,00001,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD2H imm
151 
"add2h r, r, "
152 
        do_add2h (_SD, Ra, Rb, immHL);
153 
_IALU1,00001,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD2H imm long
154 
"add2h r, r, "
155 
        do_add2h (_SD, Ra, Rb, imm);
156 
 
157 
 
158 
 
159 
// ADDC
160 
 
161 
void::function::do_addc:unsigned32 *ra, unsigned32 rb, unsigned32 imm
162 
        ALU_BEGIN(rb);
163 
        ALU_ADDC_C(imm, ALU_CARRY);
164 
        ALU_END(ra);
165 
 
166 
_IALU1,00100,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDC
167 
"addc r, r, r"
168 
        do_addc (_SD, Ra, Rb, Rc);
169 
_IALU1,00100,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDC imm
170 
"addc r, r, "
171 
        do_addc (_SD, Ra, Rb, imm);
172 
_IALU1,00100,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDC imm long
173 
"addc r, r, "
174 
        do_addc (_SD, Ra, Rb, imm);
175 
 
176 
 
177 
 
178 
// ADDHppp
179 
 
180 
void::function::do_addh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
181 
        switch (ppp) {
182 
        case 0x0: /* LLL */
183 
          {
184 
          ALU16_BEGIN(VL2_4(rb));
185 
          ALU16_ADDC(VL2_4(src));
186 
          ALU16_END(ra, 0);
187 
          }
188 
          break;
189 
        case 0x1: /* LLH */
190 
          {
191 
          ALU16_BEGIN(VL2_4(rb));
192 
          ALU16_ADDC(VH2_4(src));
193 
          ALU16_END(ra, 0);
194 
          }
195 
          break;
196 
        case 0x2: /* LHL */
197 
          {
198 
          ALU16_BEGIN(VH2_4(rb));
199 
          ALU16_ADDC(VL2_4(src));
200 
          ALU16_END(ra, 0);
201 
          }
202 
          break;
203 
        case 0x3: /* LHH */
204 
          {
205 
          ALU16_BEGIN(VH2_4(rb));
206 
          ALU16_ADDC(VH2_4(src));
207 
          ALU16_END(ra, 0);
208 
          }
209 
          break;
210 
        case 0x4: /* HLL */
211 
          {
212 
          ALU16_BEGIN(VL2_4(rb));
213 
          ALU16_ADDC(VL2_4(src));
214 
          ALU16_END(ra, 1);
215 
          }
216 
          break;
217 
        case 0x5: /* HLH */
218 
          {
219 
          ALU16_BEGIN(VL2_4(rb));
220 
          ALU16_ADDC(VH2_4(src));
221 
          ALU16_END(ra, 1);
222 
          }
223 
          break;
224 
        case 0x6: /* HHL */
225 
          {
226 
          ALU16_BEGIN(VH2_4(rb));
227 
          ALU16_ADDC(VL2_4(src));
228 
          ALU16_END(ra, 1);
229 
          }
230 
          break;
231 
        case 0x7: /* HHH */
232 
          {
233 
          ALU16_BEGIN(VH2_4(rb));
234 
          ALU16_ADDC(VH2_4(src));
235 
          ALU16_END(ra, 1);
236 
          }
237 
          break;
238 
        default:
239 
          sim_engine_abort (SD, CPU, cia, "do_addh_ppp - internal error - bad switch");
240 
        }
241 
::%s::ppp:int ppp
242 
        switch (ppp)
243 
          {
244 
          case 0x0: return "lll";
245 
          case 0x1: return "llh";
246 
          case 0x2: return "lhl";
247 
          case 0x3: return "lhh";
248 
          case 0x4: return "hll";
249 
          case 0x5: return "hlh";
250 
          case 0x6: return "hhl";
251 
          case 0x7: return "hhh";
252 
          default: return "?";
253 
          }
254 
 
255 
_IALU1,10,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDHppp
256 
"addh%s r, r, r"
257 
        do_addh_ppp(_SD, ppp, Ra, Rb, Rc);
258 
_IALU1,10,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDHppp imm
259 
"addh%s r, r, "
260 
        do_addh_ppp(_SD, ppp, Ra, Rb, immHL);
261 
_IALU1,10,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDHppp imm long
262 
"addh%s r, r, "
263 
        do_addh_ppp(_SD, ppp, Ra, Rb, imm);
264 
 
265 
 
266 
 
267 
// ADDS
268 
 
269 
void::function::do_adds:unsigned32 *ra, unsigned32 rb, unsigned32 imm
270 
        ALU_BEGIN(rb);
271 
        ALU_ADDC(EXTRACTED32(imm, 0, 0));
272 
        ALU_END(ra);
273 
 
274 
_IALU1,00110,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS
275 
"adds r, r, r"
276 
        do_adds (_SD, Ra, Rb, Rc);
277 
_IALU1,00110,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS imm
278 
"adds r, r, "
279 
        do_adds (_SD, Ra, Rb, imm);
280 
_IALU1,00110,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS imm long
281 
"adds r, r, "
282 
        do_adds (_SD, Ra, Rb, imm);
283 
 
284 
 
285 
 
286 
// ADDS2H
287 
 
288 
void::function::do_adds2h:unsigned32 *ra, unsigned32 rb, unsigned32 immHL
289 
        unsigned16 high = VH2_4(rb) + EXTRACTED32(immHL, 0, 0);
290 
        unsigned16 low = VL2_4(rb) + EXTRACTED32(immHL, 16, 16);
291 
        WRITE32_QUEUE (ra, (high << 16) | low);
292 
 
293 
_IALU1,00111,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS2H
294 
"adds2h r, r, r"
295 
        do_adds2h (_SD, Ra, Rb, Rc);
296 
_IALU1,00111,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS2H imm
297 
"adds2h r, r, "
298 
        do_adds2h (_SD, Ra, Rb, immHL);
299 
_IALU1,00111,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS2H imm long
300 
"adds2h r, r, "
301 
        do_adds2h (_SD, Ra, Rb, imm);
302 
 
303 
 
304 
 
305 
// AND
306 
 
307 
_LOGIC,11000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:AND
308 
"and r, r, r"
309 
        WRITE32_QUEUE (Ra, Rb & Rc);
310 
_LOGIC,11000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:AND imm
311 
"and r, r, "
312 
        WRITE32_QUEUE (Ra, Rb & imm);
313 
_LOGIC,11000,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:AND imm long
314 
"and r, r, "
315 
        WRITE32_QUEUE (Ra, Rb & imm);
316 
 
317 
 
318 
// ANDFG
319 
 
320 
_LOGIC,01000,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:Logical AND Flags
321 
"andfg f, f, f"
322 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & PSW_FLAG_VAL(FC));
323 
_LOGIC,01000,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:Logical AND Flags imm
324 
"andfg f, f, "
325 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & (imm_6 & 1));
326 
 
327 
 
328 
 
329 
// AVG
330 
 
331 
void::function::do_avg:unsigned32 *ra, unsigned32 rb, unsigned32 imm
332 
        WRITE32_QUEUE (ra, ((signed64)(signed32)rb + (signed64)(signed32)imm + 1) >> 1);
333 
 
334 
_IALU1,01010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG
335 
"avg r, r, r"
336 
        do_avg (_SD, Ra, Rb, Rc);
337 
_IALU1,01010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG imm
338 
"avg r, r, "
339 
        do_avg (_SD, Ra, Rb, imm);
340 
_IALU1,01010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG imm long
341 
"avg r, r, "
342 
        do_avg (_SD, Ra, Rb, imm);
343 
 
344 
 
345 
 
346 
// AVG2H
347 
 
348 
void::function::do_avg2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
349 
        unsigned16 high = ((signed32)(signed16)VH2_4(rb) + (signed32)(signed16)VH2_4(imm) + 1) >> 1;
350 
        unsigned16 low  = ((signed32)(signed16)VL2_4(rb) + (signed32)(signed16)VL2_4(imm) + 1) >> 1;
351 
        WRITE32_QUEUE (ra, (high << 16) | low);
352 
 
353 
_IALU1,01011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG2H
354 
"avg2h r, r, r"
355 
        do_avg2h (_SD, Ra, Rb, Rc);
356 
_IALU1,01011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG2H imm
357 
"avg2h r, r, "
358 
        do_avg2h (_SD, Ra, Rb, immHL);
359 
_IALU1,01011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG2H imm long
360 
"avg2h r, r, "
361 
        do_avg2h (_SD, Ra, Rb, imm);
362 
 
363 
 
364 
 
365 
// BCLR
366 
 
367 
_LOGIC,00011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BCLR
368 
"bclr r, r, r"
369 
        WRITE32_QUEUE(Ra, Rb & ~BIT32((Rc) % 32));
370 
_LOGIC,00011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BCLR imm
371 
"bclr r, r, "
372 
        WRITE32_QUEUE(Ra, Rb & ~BIT32((imm) % 32));
373 
 
374 
 
375 
 
376 
// BNOT
377 
 
378 
_LOGIC,00001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BNOT
379 
"bnot r, r, r"
380 
        WRITE32_QUEUE (Ra, Rb ^ BIT32((Rc) % 32));
381 
_LOGIC,00001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BNOT imm
382 
"bnot r, r, "
383 
        WRITE32_QUEUE (Ra, Rb ^ BIT32((imm) % 32));
384 
 
385 
 
386 
 
387 
// BRA
388 
 
389 
_BRA,00000,00,6.**,6.**,6.RC:BRA:short:mu:BRA
390 
"bra r"
391 
        nia = cia + pcdisp;
392 
_BRA,00000,10,_IMM18:BRA:short:mu:BRA imm
393 
"bra "
394 
        nia = cia + pcdisp;
395 
_BRA,00000,10,6.**,6.**,_IMM32:BRA:long:mu:BRA imm long
396 
"bra "
397 
        nia = cia + pcdisp;
398 
 
399 
 
400 
 
401 
// BRATNZ
402 
 
403 
_BRA,00100,01,6.RA,6.**,6.RC:BRA:short:mu:BRATNZ
404 
"bratnz r"
405 
        if (*Ra != 0)
406 
          nia = cia + pcdisp;
407 
_BRA,00100,11,6.RA,_IMM12:BRA:short:mu:BRATNZ imm
408 
"bratnz "
409 
        if (*Ra != 0)
410 
          nia = cia + pcdisp;
411 
_BRA,00100,11,6.RA,6.**,_IMM32:BRA:long:mu:BRATNZ imm long
412 
"bratnz "
413 
        if (*Ra != 0)
414 
          nia = cia + pcdisp;
415 
 
416 
 
417 
 
418 
// BRATZR
419 
 
420 
_BRA,00100,00,6.RA,6.**,6.RC:BRA:short:mu:BRATZR
421 
"bratzr r"
422 
        if (val_Ra == 0)
423 
          nia = cia + pcdisp;
424 
_BRA,00100,10,6.RA,_IMM12:BRA:short:mu:BRATZR imm
425 
"bratzr "
426 
        if (val_Ra == 0)
427 
          nia = cia + pcdisp;
428 
_BRA,00100,10,6.RA,6.**,_IMM32:BRA:long:mu:BRATZR imm long
429 
"bratzr "
430 
        if (val_Ra == 0)
431 
          nia = cia + pcdisp;
432 
 
433 
 
434 
 
435 
// BSET
436 
 
437 
_LOGIC,00010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BSET
438 
"bset r, r, r"
439 
        WRITE32_QUEUE (Ra, Rb | BIT32((Rc) % 32));
440 
_LOGIC,00010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BSET imm
441 
"bset r, r, "
442 
        WRITE32_QUEUE (Ra, Rb | BIT32((imm) % 32));
443 
 
444 
 
445 
 
446 
// BSR
447 
 
448 
_BRA,00010,00,6.**,6.**,6.RC:BRA:short:mu:BSR
449 
"bsr r"
450 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
451 
          WRITE32_QUEUE (&GPR[62], RPT_S);
452 
        else
453 
          WRITE32_QUEUE (&GPR[62], cia + 8);
454 
        nia = cia + pcdisp;
455 
        if (TRACE_CALL_P)
456 
          TRACE_ACTION |= TRACE_ACTION_CALL;
457 
_BRA,00010,10,_IMM18:BRA:short:mu:BSR imm
458 
"bsr "
459 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
460 
          WRITE32_QUEUE (&GPR[62], RPT_S);
461 
        else
462 
          WRITE32_QUEUE (&GPR[62], cia + 8);
463 
        nia = cia + pcdisp;
464 
        if (TRACE_CALL_P)
465 
          TRACE_ACTION |= TRACE_ACTION_CALL;
466 
_BRA,00010,10,6.**,6.**,_IMM32:BRA:long:mu:BSR imm long
467 
"bsr "
468 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
469 
          WRITE32_QUEUE (&GPR[62], RPT_S);
470 
        else
471 
          WRITE32_QUEUE (&GPR[62], cia + 8);
472 
        nia = cia + pcdisp;
473 
        if (TRACE_CALL_P)
474 
          TRACE_ACTION |= TRACE_ACTION_CALL;
475 
 
476 
 
477 
// BSRTNZ
478 
 
479 
_BRA,00110,01,6.RA,6.**,6.RC:BRA:short:mu:BSRTNZ
480 
"bsrtnz r"
481 
        if (val_Ra != 0) {
482 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
483 
            WRITE32_QUEUE (&GPR[62], RPT_S);
484 
          else
485 
            WRITE32_QUEUE (&GPR[62], cia + 8);
486 
          nia = cia + pcdisp;
487 
          if (TRACE_CALL_P)
488 
            TRACE_ACTION |= TRACE_ACTION_CALL;
489 
        }
490 
 
491 
_BRA,00110,11,6.RA,_IMM12:BRA:short:mu:BSRTNZ imm
492 
"bsrtnz "
493 
        if (val_Ra != 0) {
494 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
495 
            WRITE32_QUEUE (&GPR[62], RPT_S);
496 
          else
497 
            WRITE32_QUEUE (&GPR[62], cia + 8);
498 
          nia = cia + pcdisp;
499 
          if (TRACE_CALL_P)
500 
            TRACE_ACTION |= TRACE_ACTION_CALL;
501 
        }
502 
 
503 
_BRA,00110,11,6.RA,6.**,_IMM32:BRA:long:mu:BSRTNZ imm long
504 
"bsrtnz "
505 
        if (val_Ra != 0) {
506 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
507 
            WRITE32_QUEUE (&GPR[62], RPT_S);
508 
          else
509 
            WRITE32_QUEUE (&GPR[62], cia + 8);
510 
          nia = cia + pcdisp;
511 
          if (TRACE_CALL_P)
512 
            TRACE_ACTION |= TRACE_ACTION_CALL;
513 
        }
514 
 
515 
 
516 
// BSRTZR
517 
 
518 
_BRA,00110,00,6.RA,6.**,6.RC:BRA:short:mu:BSRTZR
519 
"bsrtzr r"
520 
        if (val_Ra == 0) {
521 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
522 
            WRITE32_QUEUE (&GPR[62], RPT_S);
523 
          else
524 
            WRITE32_QUEUE (&GPR[62], cia + 8);
525 
          nia = cia + pcdisp;
526 
          if (TRACE_CALL_P)
527 
            TRACE_ACTION |= TRACE_ACTION_CALL;
528 
        }
529 
 
530 
_BRA,00110,10,6.RA,_IMM12:BRA:short:mu:BSRTZR imm
531 
"bsrtzr "
532 
        if (val_Ra == 0) {
533 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
534 
            WRITE32_QUEUE (&GPR[62], RPT_S);
535 
          else
536 
            WRITE32_QUEUE (&GPR[62], cia + 8);
537 
          nia = cia + pcdisp;
538 
          if (TRACE_CALL_P)
539 
            TRACE_ACTION |= TRACE_ACTION_CALL;
540 
        }
541 
 
542 
_BRA,00110,10,6.RA,6.**,_IMM32:BRA:long:mu:BSRTZR imm long
543 
"bsrtzr "
544 
        if (val_Ra == 0) {
545 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
546 
            WRITE32_QUEUE (&GPR[62], RPT_S);
547 
          else
548 
            WRITE32_QUEUE (&GPR[62], cia + 8);
549 
          nia = cia + pcdisp;
550 
          if (TRACE_CALL_P)
551 
            TRACE_ACTION |= TRACE_ACTION_CALL;
552 
        }
553 
 
554 
 
555 
// BTST
556 
 
557 
_LOGIC,00000,00,***,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:BTST
558 
"btst f, r, r"
559 
        int bit = (Rc) % 32;
560 
        PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
561 
_LOGIC,00000,10,***,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:BTST imm
562 
"btst f, r, "
563 
        int bit = imm % 32;
564 
        PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
565 
 
566 
 
567 
 
568 
// CMPcc
569 
 
570 
void::function::do_cmp_cc:int cc, int fa, signed32 rb, signed32 rc
571 
        int value = 0;
572 
        switch (cc) {
573 
        case 0: /* EQ */
574 
          value = (rb == rc);
575 
          break;
576 
        case 1: /* NE */
577 
          value = (rb != rc);
578 
          break;
579 
        case 2: /* GT */
580 
          value = (rb > rc);
581 
          break;
582 
        case 3: /* GE */
583 
          value = (rb >= rc);
584 
          break;
585 
        case 4: /* LT */
586 
          value = (rb < rc);
587 
          break;
588 
        case 5: /* LE */
589 
          value = (rb <= rc);
590 
          break;
591 
        case 6: /* PS */
592 
          value = ((rb >= 0) && (rc >= 0));
593 
          break;
594 
        case 7: /* NG */
595 
          value = ((rb < 0) && (rc < 0));
596 
          break;
597 
        default:
598 
          sim_engine_abort (SD, CPU, cia, "do_cmp_cc - internal error - bad switch (%d)", cc);
599 
        }
600 
        PSW_FLAG_SET_QUEUE(fa, value);
601 
 
602 
::%s::ccc:int ccc
603 
        switch (ccc)
604 
          {
605 
          case 0: return "eq";
606 
          case 1: return "ne";
607 
          case 2: return "gt";
608 
          case 3: return "ge";
609 
          case 4: return "lt";
610 
          case 5: return "le";
611 
          case 6: return "ps";
612 
          case 7: return "ng";
613 
          default: return "?";
614 
          }
615 
 
616 
_LOGIC,01100,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPcc
617 
"cmp%s f, r, r"
618 
        do_cmp_cc(_SD, ccc, FA, Rb, Rc);
619 
_LOGIC,01100,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPcc imm
620 
"cmp%s f, r, "
621 
        do_cmp_cc(_SD, ccc, FA, Rb, imm);
622 
_LOGIC,01100,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPcc imm long
623 
"cmp%s f, r, "
624 
        do_cmp_cc(_SD, ccc, FA, Rb, imm);
625 
 
626 
 
627 
 
628 
// CMPUcc
629 
 
630 
void::function::do_cmpu_cc:int cc, int fa, unsigned32 rb, unsigned32 rc
631 
        int value = 0;
632 
        switch (cc) {
633 
        case 2: /* GT */
634 
          value = (rb > rc);
635 
          break;
636 
        case 3: /* GE */
637 
          value = (rb >= rc);
638 
          break;
639 
        case 4: /* LT */
640 
          value = (rb < rc);
641 
          break;
642 
        case 5: /* LE */
643 
          value = (rb <= rc);
644 
          break;
645 
        default:
646 
          sim_engine_abort (SD, CPU, cia, "do_cmpu_cc - internal error - bad switch (%d)", cc);
647 
        }
648 
        PSW_FLAG_SET_QUEUE(fa, value);
649 
 
650 
_LOGIC,01101,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPUcc
651 
"cmpu%s f, r, r"
652 
        do_cmpu_cc(_SD, ccc, FA, Rb, Rc);
653 
_LOGIC,01101,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPUcc imm
654 
"cmpu%s f, r, "
655 
        do_cmpu_cc(_SD, ccc, FA, Rb, imm_6u);
656 
_LOGIC,01101,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPUcc imm long
657 
"cmpu%s f, r, "
658 
        do_cmpu_cc(_SD, ccc, FA, Rb, imm);
659 
 
660 
 
661 
 
662 
// DBRA
663 
 
664 
void::function::do_dbra:address_word pcdisp, unsigned32 ra
665 
        PSW_SET_QUEUE (PSW_RP, 1);
666 
        WRITE32_QUEUE (&RPT_C, 1);
667 
        WRITE32_QUEUE (&RPT_S, cia + pcdisp);
668 
        WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
669 
 
670 
_BRA,10000,00,6.RA,6.**,6.RC:BRA:short:mu:DBRA
671 
"dbra r, r"
672 
        do_dbra(_SD, pcdisp, val_Ra);
673 
_BRA,10000,10,6.RA,_IMM12:BRA:short:mu:DBRA imm
674 
"dbra r, "
675 
        do_dbra(_SD, pcdisp, val_Ra);
676 
_BRA,10000,10,6.RA,6.**,_IMM32:BRA:long:mu:DBRA imm long
677 
"dbra r, "
678 
        do_dbra(_SD, pcdisp, val_Ra);
679 
 
680 
 
681 
 
682 
// DBRAI
683 
 
684 
void::function::do_dbrai:address_word pcdisp, unsigned32 imm
685 
        PSW_SET_QUEUE (PSW_RP, 1);
686 
        WRITE32_QUEUE (&RPT_C, 1);
687 
        WRITE32_QUEUE (&RPT_S, cia + pcdisp);
688 
        WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
689 
 
690 
_BRA,10100,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBRAI
691 
"dbrai , r"
692 
        do_dbrai(_SD, pcdisp, IMM_6);
693 
_BRA,10100,10,6.IMM_6,_IMM12:BRA:short:mu:DBRAI imm
694 
"dbrai , "
695 
        do_dbrai(_SD, pcdisp, IMM_6);
696 
_BRA,10100,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBRAI imm long
697 
"dbrai , "
698 
        do_dbrai(_SD, pcdisp, IMM_6);
699 
 
700 
 
701 
 
702 
// DBSR
703 
 
704 
void::function::do_dbsr:address_word pcdisp, unsigned32 ra
705 
        PSW_SET_QUEUE (PSW_RP, 1);
706 
        WRITE32_QUEUE (&RPT_C, 1);
707 
        WRITE32_QUEUE (&RPT_S, cia + pcdisp);
708 
        WRITE32_QUEUE (&RPT_E, cia + ra);
709 
        WRITE32_QUEUE (&GPR[62], cia + ra + 8);
710 
 
711 
_BRA,10010,00,6.RA,6.**,6.RC:BRA:short:mu:DBSR
712 
"dbsr r, r"
713 
        do_dbsr(_SD, pcdisp, val_Ra);
714 
_BRA,10010,10,6.RA,_IMM12:BRA:short:mu:DBSR imm
715 
"dbsr r, "
716 
        do_dbsr(_SD, pcdisp, val_Ra);
717 
_BRA,10010,10,6.RA,6.**,_IMM32:BRA:long:mu:DBSR imm long
718 
"dbsr r, "
719 
        do_dbsr(_SD, pcdisp, val_Ra);
720 
 
721 
 
722 
 
723 
// DBSRI
724 
 
725 
void::function::do_dbsri:address_word pcdisp, unsigned32 imm
726 
        PSW_SET_QUEUE (PSW_RP, 1);
727 
        WRITE32_QUEUE (&RPT_C, 1);
728 
        WRITE32_QUEUE (&RPT_S, cia + pcdisp);
729 
        WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
730 
        WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
731 
 
732 
_BRA,10110,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBSRI
733 
"dbsri , r"
734 
        do_dbsri(_SD, pcdisp, IMM_6);
735 
_BRA,10110,10,6.IMM_6,_IMM12:BRA:short:mu:DBSRI imm
736 
"dbsri , "
737 
        do_dbsri(_SD, pcdisp, IMM_6);
738 
_BRA,10110,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBSRI imm long
739 
"dbsri , "
740 
        do_dbsri(_SD, pcdisp, IMM_6);
741 
 
742 
 
743 
 
744 
// DBT
745 
 
746 
 
747 
_BRA,01011,00,6.**,6.**,6.**:BRA:short:mu:DBT
748 
"dbt"
749 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
750 
          {
751 
            WRITE32_QUEUE (&DPC, RPT_S);
752 
            if (RPT_C == 0)
753 
              PSW_SET (PSW_RP, 0);
754 
          }
755 
        else
756 
          WRITE32_QUEUE (&DPC, cia + 8);
757 
        DID_TRAP = 2;
758 
        nia = 0xfffff120; /* debug_trap_address */
759 
 
760 
// DJMP
761 
 
762 
void::function::do_djmp:address_word pcdisp, unsigned32 ra
763 
        PSW_SET_QUEUE (PSW_RP, 1);
764 
        WRITE32_QUEUE (&RPT_C, 1);
765 
        WRITE32_QUEUE (&RPT_S, pcdisp);
766 
        WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
767 
 
768 
_BRA,10001,00,6.RA,6.**,6.RC:BRA:short:mu:DJMP
769 
"djmp r, r"
770 
        do_djmp(_SD, pcdisp, val_Ra);
771 
_BRA,10001,10,6.RA,_IMM12:BRA:short:mu:DJMP imm
772 
"djmp r, "
773 
        do_djmp(_SD, pcdisp, val_Ra);
774 
_BRA,10001,10,6.RA,6.**,_IMM32:BRA:long:mu:DJMP imm long
775 
"djmp r, "
776 
        do_djmp(_SD, pcdisp, val_Ra);
777 
 
778 
 
779 
 
780 
// DJMPI
781 
 
782 
void::function::do_djmpi:address_word pcdisp, unsigned32 imm
783 
        PSW_SET_QUEUE (PSW_RP, 1);
784 
        WRITE32_QUEUE (&RPT_C, 1);
785 
        WRITE32_QUEUE (&RPT_S, pcdisp);
786 
        WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
787 
 
788 
_BRA,10101,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJMPI
789 
"djmpi , r"
790 
        do_djmpi(_SD, pcdisp, IMM_6);
791 
_BRA,10101,10,6.IMM_6,_IMM12:BRA:short:mu:DJMPI imm
792 
"djmpi , "
793 
        do_djmpi(_SD, pcdisp, IMM_6);
794 
_BRA,10101,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJMPI imm long
795 
"djmpi , "
796 
        do_djmpi(_SD, pcdisp, IMM_6);
797 
 
798 
 
799 
 
800 
// DJSR
801 
 
802 
void::function::do_djsr:address_word pcdisp, unsigned32 ra
803 
        PSW_SET_QUEUE (PSW_RP, 1);
804 
        WRITE32_QUEUE (&RPT_C, 1);
805 
        WRITE32_QUEUE (&RPT_S, pcdisp);
806 
        WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
807 
        WRITE32_QUEUE (&GPR[62], cia + (ra & ~0x7) + 8);
808 
 
809 
_BRA,10011,00,6.RA,6.**,6.RC:BRA:short:mu:DJSR
810 
"djsr r, r"
811 
        do_djsr(_SD, pcdisp, val_Ra);
812 
_BRA,10011,10,6.RA,_IMM12:BRA:short:mu:DJSR imm
813 
"djsr r, "
814 
        do_djsr(_SD, pcdisp, val_Ra);
815 
_BRA,10011,10,6.RA,6.**,_IMM32:BRA:long:mu:DJSR imm long
816 
"djsr r, "
817 
        do_djsr(_SD, pcdisp, val_Ra);
818 
 
819 
 
820 
 
821 
// DJSRI
822 
 
823 
void::function::do_djsri:address_word pcdisp, unsigned32 imm
824 
        PSW_SET_QUEUE (PSW_RP, 1);
825 
        WRITE32_QUEUE (&RPT_C, 1);
826 
        WRITE32_QUEUE (&RPT_S, pcdisp);
827 
        WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
828 
        WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
829 
 
830 
_BRA,10111,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJSRI
831 
"djsri , r"
832 
        do_djsri(_SD, pcdisp, IMM_6);
833 
_BRA,10111,10,6.IMM_6,_IMM12:BRA:short:mu:DJSRI imm
834 
"djsri , "
835 
        do_djsri(_SD, pcdisp, IMM_6);
836 
_BRA,10111,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJSRI imm long
837 
"djsri , "
838 
        do_djsri(_SD, pcdisp, IMM_6);
839 
 
840 
 
841 
 
842 
// JMP
843 
 
844 
_BRA,00001,00,6.**,6.**,6.RC:BRA:short:mu:JMP
845 
"jmp r"
846 
        nia = pcaddr;
847 
        if (RC == 62 && TRACE_CALL_P)
848 
          TRACE_ACTION |= TRACE_ACTION_RETURN;
849 
_BRA,00001,10,_IMM18:BRA:short:mu:JMP imm
850 
"jmp "
851 
        nia = pcaddr;
852 
_BRA,00001,10,6.**,6.**,_IMM32:BRA:long:mu:JMP imm long
853 
"jmp "
854 
        nia = pcaddr;
855 
 
856 
 
857 
 
858 
// JMPTNZ
859 
 
860 
_BRA,00101,01,6.RA,6.**,6.RC:BRA:short:mu:JMPTNZ
861 
"jmptnz r"
862 
        if (val_Ra != 0)
863 
          nia = pcaddr;
864 
_BRA,00101,11,6.RA,_IMM12:BRA:short:mu:JMPTNZ imm
865 
"jmptnz "
866 
        if (val_Ra != 0)
867 
          nia = pcaddr;
868 
_BRA,00101,11,6.RA,6.**,_IMM32:BRA:long:mu:JMPTNZ imm long
869 
"jmptnz "
870 
        if (val_Ra != 0)
871 
          nia = pcaddr;
872 
 
873 
 
874 
 
875 
// JMPTZR
876 
 
877 
_BRA,00101,00,6.RA,6.**,6.RC:BRA:short:mu:JMPTZR
878 
"jmptzr r"
879 
        if (val_Ra == 0)
880 
          nia = pcaddr;
881 
_BRA,00101,10,6.RA,_IMM12:BRA:short:mu:JMPTZR imm
882 
"jmptzr "
883 
        if (val_Ra == 0)
884 
          nia = pcaddr;
885 
_BRA,00101,10,6.RA,6.**,_IMM32:BRA:long:mu:JMPTZR imm long
886 
"jmptzr "
887 
        if (val_Ra == 0)
888 
          nia = pcaddr;
889 
 
890 
 
891 
 
892 
// JOINpp
893 
 
894 
void::function::do_join_pp:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
895 
        switch (pp) {
896 
        case 0x0: /* LL */
897 
          WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VL2_4(src));
898 
          break;
899 
        case 0x1: /* LH */
900 
          WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VH2_4(src));
901 
          break;
902 
        case 0x2: /* HL */
903 
          WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VL2_4(src));
904 
          break;
905 
        case 0x3: /* HH */
906 
          WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VH2_4(src));
907 
          break;
908 
        }
909 
 
910 
::%s::pp:int pp
911 
        switch (pp)
912 
          {
913 
          case 0x0: return "ll";
914 
          case 0x1: return "lh";
915 
          case 0x2: return "hl";
916 
          case 0x3: return "hh";
917 
          default: return "?";
918 
          }
919 
 
920 
_IALU1,011,pp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:JOINpp
921 
"join%s r, r, r"
922 
        do_join_pp(_SD, pp, Ra, Rb, Rc);
923 
_IALU1,011,pp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:JOINpp imm
924 
"join%s r, r, "
925 
        do_join_pp(_SD, pp, Ra, Rb, immHL);
926 
_IALU1,011,pp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:JOINpp imm long
927 
"join%s r, r, "
928 
        do_join_pp(_SD, pp, Ra, Rb, immHL);
929 
 
930 
 
931 
 
932 
// JSR
933 
 
934 
_BRA,00011,00,6.**,6.**,6.RC:BRA:short:mu:JSR
935 
"jsr r"
936 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
937 
          WRITE32_QUEUE (&GPR[62], RPT_S);
938 
        else
939 
          WRITE32_QUEUE (&GPR[62], cia + 8);
940 
        if (TRACE_CALL_P)
941 
          TRACE_ACTION |= TRACE_ACTION_CALL;
942 
        return pcaddr;
943 
_BRA,00011,10,_IMM18:BRA:short:mu:JSR imm
944 
"jsr "
945 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
946 
          WRITE32_QUEUE (&GPR[62], RPT_S);
947 
        else
948 
          WRITE32_QUEUE (&GPR[62], cia + 8);
949 
        if (TRACE_CALL_P)
950 
          TRACE_ACTION |= TRACE_ACTION_CALL;
951 
        return pcaddr;
952 
_BRA,00011,10,6.**,6.**,_IMM32:BRA:long:mu:JSR imm long
953 
"jsr "
954 
        if (cia == RPT_E && PSW_VAL (PSW_RP))
955 
          WRITE32_QUEUE (&GPR[62], RPT_S);
956 
        else
957 
          WRITE32_QUEUE (&GPR[62], cia + 8);
958 
        if (TRACE_CALL_P)
959 
          TRACE_ACTION |= TRACE_ACTION_CALL;
960 
        return pcaddr;
961 
 
962 
 
963 
// JSRTNZ
964 
 
965 
_BRA,00111,01,6.RA,6.**,6.RC:BRA:short:mu:JSRTNZ
966 
"jsrtnz r"
967 
        if (val_Ra != 0) {
968 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
969 
            WRITE32_QUEUE (&GPR[62], RPT_S);
970 
          else
971 
            WRITE32_QUEUE (&GPR[62], cia + 8);
972 
          nia = pcaddr;
973 
          if (TRACE_CALL_P)
974 
            TRACE_ACTION |= TRACE_ACTION_CALL;
975 
        }
976 
_BRA,00111,11,6.RA,_IMM12:BRA:short:mu:JSRTNZ imm
977 
"jsrtnz "
978 
        if (val_Ra != 0) {
979 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
980 
            WRITE32_QUEUE (&GPR[62], RPT_S);
981 
          else
982 
            WRITE32_QUEUE (&GPR[62], cia + 8);
983 
          nia = pcaddr;
984 
          if (TRACE_CALL_P)
985 
            TRACE_ACTION |= TRACE_ACTION_CALL;
986 
        }
987 
_BRA,00111,11,6.RA,6.**,_IMM32:BRA:long:mu:JSRTNZ imm long
988 
"jsrtnz "
989 
        if (val_Ra != 0) {
990 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
991 
            WRITE32_QUEUE (&GPR[62], RPT_S);
992 
          else
993 
            WRITE32_QUEUE (&GPR[62], cia + 8);
994 
          nia = pcaddr;
995 
          if (TRACE_CALL_P)
996 
            TRACE_ACTION |= TRACE_ACTION_CALL;
997 
        }
998 
 
999 
 
1000 
 
1001 
// JSRTZR
1002 
 
1003 
_BRA,00111,00,6.RA,6.**,6.RC:BRA:short:mu:JSRTZR
1004 
"jsrtzr r"
1005 
        if (val_Ra == 0) {
1006 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
1007 
            WRITE32_QUEUE (&GPR[62], RPT_S);
1008 
          else
1009 
            WRITE32_QUEUE (&GPR[62], cia + 8);
1010 
          nia = pcaddr;
1011 
          if (TRACE_CALL_P)
1012 
            TRACE_ACTION |= TRACE_ACTION_CALL;
1013 
        }
1014 
_BRA,00111,10,6.RA,_IMM12:BRA:short:mu:JSRTZR imm
1015 
"jsrtzr "
1016 
        if (val_Ra == 0) {
1017 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
1018 
            WRITE32_QUEUE (&GPR[62], RPT_S);
1019 
          else
1020 
            WRITE32_QUEUE (&GPR[62], cia + 8);
1021 
          nia = pcaddr;
1022 
          if (TRACE_CALL_P)
1023 
            TRACE_ACTION |= TRACE_ACTION_CALL;
1024 
        }
1025 
_BRA,00111,10,6.RA,6.**,_IMM32:BRA:long:mu:JSRTZR imm long
1026 
"jsrtzr "
1027 
        if (val_Ra == 0) {
1028 
          if (cia == RPT_E && PSW_VAL (PSW_RP))
1029 
            WRITE32_QUEUE (&GPR[62], RPT_S);
1030 
          else
1031 
            WRITE32_QUEUE (&GPR[62], cia + 8);
1032 
          nia = pcaddr;
1033 
          if (TRACE_CALL_P)
1034 
            TRACE_ACTION |= TRACE_ACTION_CALL;
1035 
        }
1036 
 
1037 
 
1038 
 
1039 
// Post increment
1040 
 
1041 
void::function::do_incr:int x, unsigned32 *rb, int delta
1042 
        unsigned32 next_rb;
1043 
        if (x == 1)
1044 
          next_rb = *rb + delta;
1045 
        else if (x == 3)
1046 
          next_rb = *rb - delta;
1047 
        else
1048 
          next_rb = *rb; /* value not used */
1049 
        /* HW erratum: check value after incrementing */
1050 
        if (next_rb == MOD_E
1051 
            && (x == 1 || x == 3)
1052 
            && (PSW_VAL(PSW_MD))) {
1053 
          WRITE32_QUEUE (rb, MOD_S);
1054 
        }
1055 
        else if (x == 1 || x == 3)
1056 
          WRITE32_QUEUE (rb, next_rb);
1057 
 
1058 
// LD2H
1059 
 
1060 
int::function::make_even_reg:int reg, const char *name
1061 
        if (reg & 1)
1062 
          sim_engine_abort (SD, CPU, cia,
1063 
                            "0x%lx:%s odd register (r%d) used in multi-word load/mulx2h",
1064 
                            (long) cia, name, reg);
1065 
        return reg;
1066 
 
1067 
void::function::do_ld2h:int ra, unsigned32 rb, unsigned32 src
1068 
        signed32 mem;
1069 
        ra = make_even_reg(_SD, ra, "LD2H");
1070 
        mem = MEM(signed, rb + src, 4);
1071 
        if (ra != 0)
1072 
        {
1073 
          WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16));
1074 
          WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16));
1075 
        }
1076 
 
1077 
::%s::XX:int XX
1078 
        switch (XX)
1079 
          {
1080 
          case 0: return "";
1081 
          case 1: return "+";
1082 
          case 3: return "-";
1083 
          default: return "?";
1084 
          }
1085 
 
1086 
_IMEM,00011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD2H
1087 
"ld2h r, @(r, )":XX == 0
1088 
"ld2h r, @(r%s, r)"
1089 
        do_ld2h(_SD, RA, Rb, src);
1090 
        do_incr(_SD, XX, &GPR[RB], 4);
1091 
_IMEM,00011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD2H long
1092 
"ld2h r, @(r, )"
1093 
        do_ld2h(_SD, RA, Rb, imm);
1094 
 
1095 
 
1096 
 
1097 
// LD2W
1098 
 
1099 
void::function::do_ld2w:int ra, unsigned32 rb, unsigned32 src
1100 
        unsigned64 mem;
1101 
        ra = make_even_reg(_SD, ra, "LD2W");
1102 
        mem = MEM(unsigned, rb + src, 8);
1103 
        if (ra != 0)
1104 
        {
1105 
          WRITE32_QUEUE (&GPR[ra + 0], EXTRACTED64 (mem, 0, 31));
1106 
          WRITE32_QUEUE (&GPR[ra + 1], EXTRACTED64 (mem, 32, 63));
1107 
        }
1108 
 
1109 
_IMEM,00110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:L2W
1110 
"ld2w r, @(r, )":XX == 0
1111 
"ld2w r, @(r%s, r)"
1112 
        do_ld2w(_SD, RA, Rb, src);
1113 
        do_incr(_SD, XX, &GPR[RB], 8);
1114 
_IMEM,00110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:L2W long
1115 
"ld2w r, @(r, )"
1116 
        do_ld2w(_SD, RA, Rb, imm);
1117 
 
1118 
 
1119 
 
1120 
// LD4BH
1121 
 
1122 
void::function::do_ld4bh:unsigned32 ra, unsigned32 rb, unsigned32 src
1123 
        unsigned16 l1, l2, h1, h2;
1124 
        unsigned32 mem;
1125 
        ra = make_even_reg(_SD, ra, "LD4BH");
1126 
        mem = MEM(unsigned, rb + src, 4);
1127 
        h1 = SEXT16(EXTRACTED32(mem, 0, 7), 8);
1128 
        l1 = SEXT16(EXTRACTED32(mem, 8, 15), 8);
1129 
        h2 = SEXT16(EXTRACTED32(mem, 16, 23), 8);
1130 
        l2 = SEXT16(EXTRACTED32(mem, 24, 31), 8);
1131 
        if (ra != 0)
1132 
        {
1133 
          WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1134 
          WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1135 
        }
1136 
 
1137 
_IMEM,00101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BH
1138 
"ld4bh r, @(r, )":XX == 0
1139 
"ld4bh r, @(r%s, r)"
1140 
        do_ld4bh(_SD, RA, Rb, src);
1141 
        do_incr(_SD, XX, &GPR[RB], 4);
1142 
_IMEM,00101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BH long
1143 
"ld4bh r, @(r, )"
1144 
        do_ld4bh(_SD, RA, Rb, imm);
1145 
 
1146 
 
1147 
 
1148 
// LD4BHU
1149 
 
1150 
void::function::do_ld4bhu:unsigned32 ra, unsigned32 rb, unsigned32 src
1151 
        unsigned16 l1, l2, h1, h2;
1152 
        unsigned32 mem;
1153 
        ra = make_even_reg(_SD, ra, "LD4BH");
1154 
        mem = MEM(signed, rb + src, 4);
1155 
        h1 = EXTRACTED32(mem, 0, 7);
1156 
        l1 = EXTRACTED32(mem, 8, 15);
1157 
        h2 = EXTRACTED32(mem, 16, 23);
1158 
        l2 = EXTRACTED32(mem, 24, 31);
1159 
        if (ra != 0)
1160 
        {
1161 
          WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1162 
          WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1163 
        }
1164 
 
1165 
_IMEM,01101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BHU
1166 
"ld4hbu r, @(r, )":XX == 0
1167 
"ld4hbu r, @(r%s, r)"
1168 
        do_ld4bhu(_SD, RA, Rb, src);
1169 
        do_incr(_SD, XX, &GPR[RB], 4);
1170 
_IMEM,01101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BHU long
1171 
"ld4hbu r, @(r, )"
1172 
        do_ld4bhu(_SD, RA, Rb, imm);
1173 
 
1174 
 
1175 
 
1176 
// LDB
1177 
 
1178 
void::function::do_ldb:unsigned32 *ra, unsigned32 rb, unsigned32 src
1179 
        WRITE32_QUEUE (ra, MEM(signed, rb + src, 1));
1180 
 
1181 
_IMEM,00000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDB
1182 
"ldb r, @(r, )":XX == 0
1183 
"ldb r, @(r%s, r)"
1184 
        do_ldb(_SD, Ra, Rb, src);
1185 
        do_incr(_SD, XX, &GPR[RB], 1);
1186 
_IMEM,00000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDB long
1187 
"ldb r, @(r, )"
1188 
        do_ldb(_SD, Ra, Rb, imm);
1189 
 
1190 
 
1191 
 
1192 
// LDBU
1193 
 
1194 
void::function::do_ldbu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1195 
        WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 1));
1196 
 
1197 
_IMEM,01001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDBU
1198 
"ldbu r, @(r, )":XX == 0
1199 
"ldbu r, @(r%s, r)"
1200 
        do_ldbu(_SD, Ra, Rb, src);
1201 
        do_incr(_SD, XX, &GPR[RB], 1);
1202 
_IMEM,01001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDBU long
1203 
"ldbu r, @(r, )"
1204 
        do_ldbu(_SD, Ra, Rb, imm);
1205 
 
1206 
 
1207 
 
1208 
// LDH
1209 
 
1210 
void::function::do_ldh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1211 
        WRITE32_QUEUE (ra, MEM(signed, rb + src, 2));
1212 
 
1213 
_IMEM,00010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDH
1214 
"ldh r, @(r, )":XX == 0
1215 
"ldh r, @(r%s, r)"
1216 
        do_ldh(_SD, Ra, Rb, src);
1217 
        do_incr(_SD, XX, &GPR[RB], 2);
1218 
_IMEM,00010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDH long
1219 
"ldh r, @(r, )"
1220 
        do_ldh(_SD, Ra, Rb, imm);
1221 
 
1222 
 
1223 
 
1224 
// LDHH
1225 
 
1226 
void::function::do_ldhh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1227 
        WRITE32_QUEUE (ra, MEM(signed, rb + src, 2) << 16);
1228 
 
1229 
_IMEM,00001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHH
1230 
"ldhh r, @(r, )":XX == 0
1231 
"ldhh r, @(r%s, r)"
1232 
        do_ldhh(_SD, Ra, Rb, src);
1233 
        do_incr(_SD, XX, &GPR[RB], 2);
1234 
_IMEM,00001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHH long
1235 
"ldhh r, @(r, )"
1236 
        do_ldhh(_SD, Ra, Rb, imm);
1237 
 
1238 
 
1239 
 
1240 
// LDHU
1241 
 
1242 
void::function::do_ldhu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1243 
        WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 2));
1244 
 
1245 
_IMEM,01010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHU
1246 
"ldhu r, @(r, )":XX == 0
1247 
"ldhu r, @(r%s, r)"
1248 
        do_ldhu(_SD, Ra, Rb, src);
1249 
        do_incr(_SD, XX, &GPR[RB], 2);
1250 
_IMEM,01010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHU long
1251 
"ldhu r, @(r, )"
1252 
        do_ldhu(_SD, Ra, Rb, imm);
1253 
 
1254 
 
1255 
 
1256 
// LDW
1257 
 
1258 
void::function::do_ldw:unsigned32 *ra, unsigned32 rb, unsigned32 src
1259 
        WRITE32_QUEUE (ra, MEM(signed, rb + src, 4));
1260 
 
1261 
_IMEM,00100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDW
1262 
"ldw r, @(r, )":XX == 0
1263 
"ldw r, @(r%s, r)"
1264 
        do_ldw(_SD, Ra, Rb, src);
1265 
        do_incr(_SD, XX, &GPR[RB], 4);
1266 
_IMEM,00100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDW long
1267 
"ldw r, @(r, )"
1268 
        do_ldw(_SD, Ra, Rb, imm);
1269 
 
1270 
 
1271 
 
1272 
// MACa
1273 
 
1274 
void::function::do_mac:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1275 
        unsigned64 accum = *aa;
1276 
        accum += (signed64) (rb) * (signed64) (src);
1277 
        WRITE64_QUEUE (aa, accum);
1278 
        WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1279 
 
1280 
_IALU2,10100,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACa
1281 
"mac r, r, r"
1282 
        do_mac(_SD, Aa, Ra, Rb, Rc);
1283 
_IALU2,10100,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACa imm
1284 
"mac r, r, "
1285 
        do_mac(_SD, Aa, Ra, Rb, imm);
1286 
 
1287 
 
1288 
 
1289 
// MACSa
1290 
 
1291 
void::function::do_macs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1292 
        unsigned64 accum = *aa;
1293 
        accum += ((signed64) (rb) * (signed64) (src)) << 1;
1294 
        WRITE64_QUEUE (aa, accum);
1295 
        WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1296 
 
1297 
_IALU2,10101,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACSa
1298 
"macs r, r, r"
1299 
        do_macs(_SD, Aa, Ra, Rb, Rc);
1300 
_IALU2,10101,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACSa imm
1301 
"macs r, r, "
1302 
        do_macs(_SD, Aa, Ra, Rb, imm);
1303 
 
1304 
 
1305 
 
1306 
// MODDEC | MODINC
1307 
 
1308 
_IMEM,00111,11,6.**,6.RB,_IMM6:IMEM:short:mu:MODDEC
1309 
"moddec r, "
1310 
        do_incr(_SD, 3/*0b11*/, &GPR[RB], imm_5);
1311 
_IMEM,00111,01,6.**,6.RB,_IMM6:IMEM:short:mu:MODINC
1312 
"modinc r, "
1313 
        do_incr(_SD, 1/*0b01*/, &GPR[RB], imm_5);
1314 
 
1315 
 
1316 
 
1317 
// MSUBa
1318 
 
1319 
void::function::do_msub:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1320 
        unsigned64 accum = *aa;
1321 
        accum -= (signed64) (rb) * (signed64) (src);
1322 
        WRITE64_QUEUE (aa, accum);
1323 
        WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1324 
 
1325 
_IALU2,10110,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBa
1326 
"msub r, r, r"
1327 
        do_msub(_SD, Aa, Ra, Rb, Rc);
1328 
_IALU2,10110,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBa imm
1329 
"msub r, r, "
1330 
        do_msub(_SD, Aa, Ra, Rb, imm);
1331 
 
1332 
 
1333 
 
1334 
// MSUBSa
1335 
 
1336 
void::function::do_msubs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1337 
        unsigned64 accum = *aa;
1338 
        accum -= ((signed64) (rb) * (signed64) (src)) << 1;
1339 
        WRITE64_QUEUE (aa, accum);
1340 
        WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1341 
 
1342 
_IALU2,10111,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBSa
1343 
"msubs r, r, r"
1344 
        do_msubs(_SD, Aa, Ra, Rb, Rc);
1345 
_IALU2,10111,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBSa imm
1346 
"msubs r, r, "
1347 
        do_msubs(_SD, Aa, Ra, Rb, imm);
1348 
 
1349 
 
1350 
 
1351 
// MUL
1352 
 
1353 
void::function::do_mul:unsigned32 *ra, unsigned32 rb, unsigned32 src
1354 
        WRITE32_QUEUE (ra, rb * src);
1355 
 
1356 
_IALU2,10000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL
1357 
"mul r, r, r"
1358 
        do_mul(_SD, Ra, Rb, Rc);
1359 
_IALU2,10000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL imm
1360 
"mul r, r, "
1361 
        do_mul(_SD, Ra, Rb, imm);
1362 
 
1363 
 
1364 
 
1365 
// MUL2H
1366 
 
1367 
void::function::do_mul2h:unsigned32 *ra, unsigned32 rb, unsigned32 src
1368 
        unsigned16 high = VH2_4(rb) * VH2_4(src);
1369 
        unsigned16 low  = VL2_4(rb) * VL2_4(src);
1370 
        WRITE32_QUEUE (ra, (high << 16) | low);
1371 
 
1372 
_IALU2,00000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL2H
1373 
"mul2h r, r, r"
1374 
        do_mul2h(_SD, Ra, Rb, Rc);
1375 
_IALU2,00000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL2H imm
1376 
"mul2h r, r, "
1377 
        do_mul2h(_SD, Ra, Rb, immHL);
1378 
 
1379 
 
1380 
 
1381 
// MULX
1382 
 
1383 
void::function::do_mulx:unsigned64 *aa, signed32 rb, signed32 src
1384 
        WRITE64_QUEUE (aa, (signed64) (rb) * (signed64) (src));
1385 
 
1386 
_IALU2,11000,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULX
1387 
"mulx a, r, r"
1388 
        do_mulx(_SD, Aa, Rb, Rc);
1389 
_IALU2,11000,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULX imm
1390 
"mulx a, r, "
1391 
        do_mulx(_SD, Aa, Rb, imm);
1392 
 
1393 
 
1394 
// MULX2H
1395 
 
1396 
void::function::do_mulx2h:int ra, signed32 rb, signed32 src, int high
1397 
        signed32 result = rb * src;
1398 
        if (!high)
1399 
          {
1400 
            ra = make_even_reg(_SD, ra, "MULX2H");
1401 
            if (ra != 0)
1402 
              WRITE32_QUEUE (&GPR[ra+1], result);
1403 
          }
1404 
        else if (ra != 0)
1405 
          {
1406 
              WRITE32_QUEUE (&GPR[ra+0], result);
1407 
          }
1408 
 
1409 
_IALU2,00001,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULX2H
1410 
"mul2h r, r, r"
1411 
        do_mulx2h(_SD, RA, RbH, RcH, 1);
1412 
        do_mulx2h(_SD, RA, RbL, RcL, 0);
1413 
_IALU2,00001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULX2H imm
1414 
"mul2h r, r, "
1415 
        do_mulx2h(_SD, RA, RbH, imm, 1);
1416 
        do_mulx2h(_SD, RA, RbL, imm, 0);
1417 
 
1418 
// MULHXpp
1419 
 
1420 
void::function::do_mulhx:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
1421 
        signed32 value = 0;
1422 
        switch (pp) {
1423 
        case 0: /* LL */
1424 
          value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1425 
          break;
1426 
        case 1: /* LH */
1427 
          value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1428 
          break;
1429 
        case 2: /* HL */
1430 
          value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1431 
          break;
1432 
        case 3: /* HH */
1433 
          value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1434 
          break;
1435 
        default:
1436 
          sim_engine_abort (SD, CPU, cia, "do_mulhx - internal error - bad switch");
1437 
        }
1438 
        WRITE32_QUEUE (ra, value);
1439 
 
1440 
_IALU2,001,pp,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULHXpp
1441 
"mulhx%s r, r, r"
1442 
        do_mulhx(_SD, pp, Ra, Rb, Rc);
1443 
_IALU2,001,pp,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULHXpp imm
1444 
"mulhx%s r, r, "
1445 
        do_mulhx(_SD, pp, Ra, Rb, immHL);
1446 
 
1447 
 
1448 
 
1449 
// MULXS
1450 
 
1451 
void::function::do_mulxs:unsigned64 *aa, signed32 rb, signed32 src
1452 
        WRITE64_QUEUE (aa, ((signed64) (rb) * (signed64) (src)) << 1);
1453 
 
1454 
_IALU2,11001,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULXS
1455 
"mulxs a, r, r"
1456 
        do_mulxs(_SD, Aa, Rb, Rc);
1457 
_IALU2,11001,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULXS imm
1458 
"mulxs a, r, "
1459 
        do_mulxs(_SD, Aa, Rb, imm);
1460 
 
1461 
 
1462 
 
1463 
// MVFACC
1464 
 
1465 
void::function::do_mvfacc:unsigned32 *ra, unsigned64 ab, unsigned32 src
1466 
        while (src > 63) src -= 64;
1467 
        WRITE32_QUEUE (ra, ((signed64)ab) >> src);
1468 
 
1469 
_IALU2,11111,00,6.RA,5.*,1.AB,6.RC:IALU2:short:iu:MVFACC
1470 
"mvfacc r, a, r"
1471 
        do_mvfacc(_SD, Ra, *Ab, Rc);
1472 
_IALU2,11111,10,6.RA,5.*,1.AB,_IMM6:IALU2:short:iu:MVFACC imm
1473 
"mvfacc r, a, "
1474 
        do_mvfacc(_SD, Ra, *Ab, imm_6u);
1475 
 
1476 
 
1477 
 
1478 
// MVFSYS
1479 
 
1480 
_BRA,11110,00,6.RA,6.CR,6.ID:BRA:short:mu:MVFSYS
1481 
"mvfsys r, cr"
1482 
        switch (ID) {
1483 
        case 0:
1484 
          if (CR >= NR_CONTROL_REGISTERS)
1485 
            sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1486 
          else
1487 
            WRITE32_QUEUE (Ra, (CPU)->regs.control[CR]);
1488 
          break;
1489 
        case 1:
1490 
          WRITE32_QUEUE (Ra, PSWL);
1491 
          break;
1492 
        case 2:
1493 
          WRITE32_QUEUE (Ra, EXTRACTED32(PSWH, 16, 31));
1494 
          break;
1495 
        case 3:
1496 
          WRITE32_QUEUE (Ra, PSW_FLAG_VAL(CR));
1497 
          break;
1498 
        default:
1499 
          sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1500 
        }
1501 
 
1502 
 
1503 
 
1504 
// MVTACC
1505 
 
1506 
_IALU2,01111,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MVTACC
1507 
"mvtacc a, r, r"
1508 
        WRITE64_QUEUE (Aa, INSERTED64(RbU, 0, 31) | (RcU));
1509 
 
1510 
 
1511 
 
1512 
// MVTSYS
1513 
 
1514 
_BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
1515 
"mvtsys cr, r"
1516 
        switch (ID) {
1517 
        case 0:                 /* control register */
1518 
          if (CR >= NR_CONTROL_REGISTERS)
1519 
            sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1520 
          else
1521 
            {
1522 
              unsigned32 value = Rb;
1523 
              CPU->mvtsys_left_p = 1;
1524 
              if (CR == processor_status_word_cr)
1525 
                {
1526 
                  unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
1527 
                  value = ds | (value & PSW_VALID);
1528 
                }
1529 
              else if (CR == backup_processor_status_word_cr
1530 
                       || CR == debug_backup_processor_status_word_cr)
1531 
                value &= DPSW_VALID;
1532 
              else if (CR == eit_vector_base_cr)
1533 
                value &= EIT_VALID;
1534 
              WRITE32_QUEUE (&(CPU)->regs.control[CR], value);
1535 
            }
1536 
          break;
1537 
        case 1:                 /* PSWL */
1538 
          WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31),
1539 
                              PSW_VALID & 0x0000ffff);
1540 
          break;
1541 
        case 2:                 /* PSWH */
1542 
          {
1543 
            unsigned32 ds = PSW & BIT32 (PSW_DS);       /* preserve ds */
1544 
            WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds,
1545 
                                (PSW_VALID | ds) & 0xffff0000);
1546 
          }
1547 
          break;
1548 
        case 3:                 /* FLAG */
1549 
          PSW_FLAG_SET_QUEUE(CR, Rb & 1);
1550 
          break;
1551 
        default:
1552 
          sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1553 
        }
1554 
 
1555 
 
1556 
 
1557 
// NOP
1558 
 
1559 
_BRA,01111,00,6.**,6.**,6.**:BRA:short:iu,mu:NOP
1560 
"nop"
1561 
        /* NOP */;
1562 
 
1563 
 
1564 
// NOT
1565 
 
1566 
_LOGIC,11001,00,6.RA,6.RB,6.*:LOGIC:short:iu,mu:NOT
1567 
"not r, r"
1568 
        WRITE32_QUEUE (Ra, ~Rb);
1569 
 
1570 
 
1571 
 
1572 
// NOTFG
1573 
 
1574 
_LOGIC,01001,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:NOTFG
1575 
"notfg f, f"
1576 
        PSW_FLAG_SET_QUEUE(FA, !PSW_FLAG_VAL(FB));
1577 
 
1578 
 
1579 
// OR
1580 
 
1581 
_LOGIC,11010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:OR
1582 
"or r, r, r"
1583 
        WRITE32_QUEUE (Ra, Rb | Rc);
1584 
_LOGIC,11010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:OR imm
1585 
"or r, r, "
1586 
        WRITE32_QUEUE (Ra, Rb | imm);
1587 
_LOGIC,11010,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:OR imm long
1588 
"or r, r, "
1589 
        WRITE32_QUEUE (Ra, Rb | imm);
1590 
 
1591 
 
1592 
 
1593 
// ORFG
1594 
 
1595 
_LOGIC,01010,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:ORFG
1596 
"orfg f, f, f"
1597 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | PSW_FLAG_VAL(FC));
1598 
_LOGIC,01010,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:ORFG imm
1599 
"orfg f, f, "
1600 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | (imm_6 & 1));
1601 
 
1602 
 
1603 
 
1604 
// REIT
1605 
 
1606 
_BRA,01000,00,6.**,6.**,6.**:BRA:short:mu:REIT
1607 
"reit"
1608 
        WRITE32_QUEUE (&PSW, bPSW);
1609 
        nia = bPC;
1610 
 
1611 
 
1612 
 
1613 
 
1614 
// REPEAT
1615 
 
1616 
void::function::do_repeat:unsigned32 count, address_word pcaddr
1617 
        address_word rpt_s = cia + 8;
1618 
        address_word rpt_e = cia + pcaddr;
1619 
 
1620 
        if (count == 0)
1621 
          sim_engine_abort (SD, CPU, cia, "REPEAT with ra=0 and REPEATI with imm = 0 is forbidden.");
1622 
        if (count > 1)
1623 
          PSW_SET_QUEUE (PSW_RP, 1);
1624 
        if (rpt_e  < rpt_s + 0x10)
1625 
          sim_io_eprintf (sd, "warning: 0x%lx: REPEAT or REPEATI loop is too small\n", (long) cia);
1626 
        WRITE32_QUEUE (&RPT_C, count - 1);
1627 
        WRITE32_QUEUE (&RPT_S, rpt_s);
1628 
        WRITE32_QUEUE (&RPT_E, rpt_e);
1629 
 
1630 
_BRA,11000,00,6.RA,6.**,6.RC:BRA:short:mu:REPEAT
1631 
"repeat r, r"
1632 
        do_repeat(_SD, val_Ra, pcaddr);
1633 
_BRA,11000,10,6.RA,_IMM12:BRA:short:mu:REPEAT imm
1634 
"repeat r, "
1635 
        do_repeat(_SD, val_Ra, pcaddr);
1636 
_BRA,11000,10,6.RA,6.**,_IMM32:BRA:long:mu:REPEAT imm long
1637 
"repeat r, "
1638 
        do_repeat(_SD, val_Ra, pcaddr);
1639 
 
1640 
 
1641 
 
1642 
 
1643 
// REPEATI
1644 
 
1645 
_BRA,11010,00,6.IMM_6,6.**,6.RC:BRA:short:mu:REPEATI
1646 
"repeati , r"
1647 
        do_repeat(_SD, IMM_6, pcaddr);
1648 
_BRA,11010,10,6.IMM_6,_IMM12:BRA:short:mu:REPEATI imm
1649 
"repeati , "
1650 
        do_repeat(_SD, IMM_6, pcaddr);
1651 
_BRA,11010,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:REPEATI imm long
1652 
"repeati , "
1653 
        do_repeat(_SD, IMM_6, pcaddr);
1654 
 
1655 
 
1656 
 
1657 
 
1658 
// RTD
1659 
 
1660 
_BRA,01010,00,6.*,6.*,6.*:BRA:short:mu:RTD
1661 
"rtd"
1662 
        WRITE32_QUEUE (&PSW, DPSW);
1663 
        nia = DPC;
1664 
 
1665 
 
1666 
 
1667 
 
1668 
// ROT
1669 
 
1670 
_LOGIC,10100,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT
1671 
"rot r, r, r"
1672 
        WRITE32_QUEUE (Ra, ROT32(Rb, Rc & 0x1f));
1673 
_LOGIC,10100,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT imm
1674 
"rot r, r, "
1675 
        WRITE32_QUEUE (Ra, ROT32(Rb, imm & 0x1f));
1676 
 
1677 
 
1678 
 
1679 
 
1680 
// ROT2H
1681 
 
1682 
void::function::do_rot2h:unsigned32 *ra, unsigned32 rb, signed32 src
1683 
        unsigned16 high = ROTR16(VH2_4(rb), VH2_4(src) & 0xf);
1684 
        unsigned16 low  = ROTR16(VL2_4(rb), VL2_4(src) & 0xf);
1685 
        WRITE32_QUEUE (ra, (high << 16) | low);
1686 
 
1687 
_LOGIC,10101,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT2H
1688 
"rot2h r, r, r"
1689 
        do_rot2h(_SD, Ra, Rb, Rc);
1690 
_LOGIC,10101,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT2H imm
1691 
"rot2h r, r, "
1692 
        do_rot2h(_SD, Ra, Rb, immHL);
1693 
 
1694 
 
1695 
 
1696 
 
1697 
// SAT
1698 
 
1699 
void::function::do_sat:signed32 *ra, signed32 rb, signed32 src
1700 
        int bits = LSMASKED32(src, 4, 0); /* 5 */
1701 
        signed32 sat = LSMASK32(bits, 0) >> 2;
1702 
        signed32 nsat = ~sat;
1703 
        signed32 value;
1704 
        if (bits != src)
1705 
          sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia);
1706 
        if (bits == 0)
1707 
          value = rb;
1708 
        else if (rb >= sat)
1709 
          value = sat;
1710 
        else if (rb <= nsat)
1711 
          value = nsat;
1712 
        else
1713 
          value = rb;
1714 
        WRITE32_QUEUE (ra, value);
1715 
 
1716 
_IALU2,01000,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT
1717 
"sat r, r, r"
1718 
        do_sat(_SD, Ra, Rb, Rc);
1719 
_IALU2,01000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT imm
1720 
"sat r, r, "
1721 
        do_sat(_SD, Ra, Rb, imm_5);
1722 
 
1723 
 
1724 
 
1725 
 
1726 
// SAT2H
1727 
 
1728 
void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int updates_f4
1729 
        int bits = LSMASKED32(src, 4, 0); /* 5 */
1730 
        signed32 sat = LSMASK32(bits, 0) >> 2;
1731 
        signed32 nsat = ~sat;
1732 
        signed32 value;
1733 
        if (bits != src)
1734 
          sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia);
1735 
        if (bits == 0)
1736 
          value = rb;
1737 
        else if (rb >= sat)
1738 
          value = sat;
1739 
        else if (rb <= nsat)
1740 
          value = nsat;
1741 
        else
1742 
          value = rb;
1743 
        if (high)
1744 
          WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1745 
        else
1746 
          WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1747 
        if (updates_f4)
1748 
          {
1749 
            /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */
1750 
            if(STATE_CPU (sd, 0)->mvtsys_left_p)
1751 
              unqueue_writes (sd, STATE_CPU (sd, 0), cia);
1752 
            PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1));
1753 
          }
1754 
 
1755 
_IALU2,01001,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT2H
1756 
"sat2h r, r, r"
1757 
        do_sath(_SD, Ra, RbH, RcH, 1, 0);
1758 
        do_sath(_SD, Ra, RbL, RcL, 0, 0);
1759 
_IALU2,01001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT2H imm
1760 
"sat2h r, r, "
1761 
        do_sath(_SD, Ra, RbH, imm_5, 1, 0);
1762 
        do_sath(_SD, Ra, RbL, imm_5, 0, 0);
1763 
 
1764 
 
1765 
 
1766 
 
1767 
// SATHp
1768 
 
1769 
::%s::p:int p
1770 
        switch (p)
1771 
          {
1772 
          case 0: return "l";
1773 
          case 1: return "h";
1774 
          default: return "?";
1775 
          }
1776 
 
1777 
_IALU2,1110,p,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATHP
1778 
"sath%s
 r, r, r"
1779 
        do_sath(_SD, Ra, Rb, Rc, p, 1);
1780 
_IALU2,1110,p,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATHP imm
1781 
"sath%s
 r, r, "
1782 
        do_sath(_SD, Ra, Rb, imm_5, p, 1);
1783 
 
1784 
 
1785 
 
1786 
// SATZ
1787 
 
1788 
void::function::do_satz:signed32 *ra, signed32 rb, signed32 src
1789 
        if (rb < 0)
1790 
          WRITE32_QUEUE (ra, 0);
1791 
        else
1792 
          do_sat (_SD, ra, rb, src);
1793 
 
1794 
_IALU2,01010,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ
1795 
"satz r, r, r"
1796 
        do_satz(_SD, Ra, Rb, Rc);
1797 
_IALU2,01010,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ imm
1798 
"satz r, r, "
1799 
        do_satz(_SD, Ra, Rb, imm_5);
1800 
 
1801 
 
1802 
 
1803 
 
1804 
// SATZ2H
1805 
 
1806 
void::function::do_satzh:signed32 *ra, signed16 rb, signed32 src, int high
1807 
        int bits = LSMASKED32(src, 3, 0); /*4*/
1808 
        signed16 sat = LSMASK16(bits, 0) >> 2;
1809 
        signed16 nsat = 0;
1810 
        signed16 value;
1811 
        if (bits != src)
1812 
          sim_io_eprintf (sd, "warning: 0x%lx:SATZ2H bit overflow\n", (long) cia);
1813 
        if (bits == 0 && rb > sat)
1814 
          value = rb;
1815 
        else if (rb > sat)
1816 
          value = sat;
1817 
        else if (rb < nsat)
1818 
          value = nsat;
1819 
        else
1820 
          value = rb;
1821 
        if (high)
1822 
          WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1823 
        else
1824 
          WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1825 
 
1826 
 
1827 
_IALU2,01011,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ2H
1828 
"satz2h r, r, r"
1829 
        do_satzh(_SD, Ra, RbH, RcH, 1);
1830 
        do_satzh(_SD, Ra, RbL, RcL, 0);
1831 
_IALU2,01011,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ2H imm
1832 
"satz2h r, r, "
1833 
        do_satzh(_SD, Ra, RbH, imm, 1);
1834 
        do_satzh(_SD, Ra, RbL, imm, 0);
1835 
 
1836 
 
1837 
 
1838 
 
1839 
// SRA
1840 
 
1841 
void::function::do_sra:unsigned32 *ra, unsigned32 rb, signed32 src
1842 
        unsigned32 value;
1843 
        while (src > 31) src -= 32;
1844 
        while (src < -32) src += 32;
1845 
        if (src >= 0)
1846 
          value = (signed32)rb >> src;
1847 
        else if (src == -32)
1848 
          value = 0;
1849 
        else
1850 
          value = rb << -src;
1851 
        WRITE32_QUEUE (ra, value);
1852 
 
1853 
_LOGIC,10000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA
1854 
"sra r, r, r"
1855 
        do_sra(_SD, Ra, Rb, Rc);
1856 
_LOGIC,10000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA imm
1857 
"sra r, r, "
1858 
        do_sra(_SD, Ra, Rb, imm);
1859 
 
1860 
 
1861 
 
1862 
 
1863 
// SRAHp
1864 
 
1865 
void::function::do_srah:unsigned32 *ra, unsigned32 rb, int src, int high
1866 
        unsigned32 value;
1867 
        while (src > 31) src -= 32;
1868 
        while (src < -32) src += 32;
1869 
        if (src >= 0)
1870 
          value = (signed32)rb >> src;
1871 
        else if (src == -32)
1872 
          value = 0;
1873 
        else
1874 
          value = rb << -src;
1875 
        if (high)
1876 
          WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1877 
        else
1878 
          WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1879 
 
1880 
_LOGIC,0010,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRAHP
1881 
"srah%s
 r, r, r"
1882 
        do_srah(_SD, Ra, Rb, Rc, p);
1883 
_LOGIC,0010,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRAHP imm
1884 
"srah%s
 r, r, "
1885 
        do_srah(_SD, Ra, Rb, imm, p);
1886 
 
1887 
 
1888 
 
1889 
 
1890 
// SRA2H
1891 
 
1892 
_LOGIC,10001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA2H
1893 
"sra2h r, r, r"
1894 
        signed32 srcH = RcH;
1895 
        signed32 srcL = RcL;
1896 
        while (srcH > 15) srcH -= 16;
1897 
        while (srcH < -16) srcH += 16;
1898 
        while (srcL > 15) srcL -= 16;
1899 
        while (srcL < -16) srcL += 16;
1900 
        do_srah(_SD, Ra, RbH, srcH, 1);
1901 
        do_srah(_SD, Ra, RbL, srcL, 0);
1902 
_LOGIC,10001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA2H imm
1903 
"sra2h r, r, "
1904 
        signed32 src = imm;
1905 
        while (src > 15) src -= 16;
1906 
        while (src < -16) src += 16;
1907 
        do_srah(_SD, Ra, RbH, src, 1);
1908 
        do_srah(_SD, Ra, RbL, src, 0);
1909 
 
1910 
 
1911 
 
1912 
 
1913 
// SRC
1914 
 
1915 
void::function::do_src:unsigned32 *ra, unsigned32 rb, int src
1916 
        unsigned32 value;
1917 
        unsigned64 operand;
1918 
        unsigned64 shifted;
1919 
        while (src > 31) src -= 32;
1920 
        while (src < -32) src += 32;
1921 
        if (src >= 0)
1922 
          {
1923 
            operand = (INSERTED64(rb, 0, 31) | INSERTED64(*ra, 32, 63));
1924 
            shifted = operand >> src;
1925 
            value = EXTRACTED64(shifted, 32, 63);
1926 
          }
1927 
        else
1928 
          {
1929 
            operand = (INSERTED64(*ra, 0, 31) | INSERTED64(rb, 32, 63));
1930 
            shifted = operand << -src;
1931 
            value = EXTRACTED64(shifted, 0, 31);
1932 
          }
1933 
        WRITE32_QUEUE (ra, value);
1934 
 
1935 
_LOGIC,10110,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRC
1936 
"src r, r, r"
1937 
        do_src(_SD, Ra, Rb, Rc);
1938 
_LOGIC,10110,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRC imm
1939 
"src r, r, "
1940 
        do_src(_SD, Ra, Rb, imm);
1941 
 
1942 
 
1943 
 
1944 
 
1945 
// SRL
1946 
 
1947 
void::function::do_srl:unsigned32 *ra, unsigned32 rb, int src
1948 
        unsigned32 value;
1949 
        while (src > 31) src -= 32;
1950 
        while (src < -32) src += 32;
1951 
        if (src >= 0)
1952 
          value = (unsigned32)rb >> src;
1953 
        else if (src == -32)
1954 
          value = 0;
1955 
        else
1956 
          value = (unsigned32)rb << -src;
1957 
        WRITE32_QUEUE (ra, value);
1958 
 
1959 
_LOGIC,10010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL
1960 
"srl r, r, r"
1961 
        do_srl(_SD, Ra, Rb, Rc);
1962 
_LOGIC,10010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL imm
1963 
"srl r, r, "
1964 
        do_srl(_SD, Ra, Rb, imm);
1965 
 
1966 
 
1967 
 
1968 
 
1969 
// SRLHp
1970 
 
1971 
void::function::do_srlh:unsigned32 *ra, unsigned32 rb, int src, int high
1972 
        unsigned32 value;
1973 
        while (src > 31) src -= 32;
1974 
        while (src < -32) src += 32;
1975 
        if (src >= 0)
1976 
          value = rb >> src;
1977 
        else if (src == -32)
1978 
          value = 0;
1979 
        else
1980 
          value = rb << -src;
1981 
        if (high)
1982 
          WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1983 
        else
1984 
          WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1985 
 
1986 
_LOGIC,0011,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRLHP
1987 
"srlh%s
 r, r, r"
1988 
        do_srlh(_SD, Ra, Rb, Rc, p);
1989 
_LOGIC,0011,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRLHP imm
1990 
"srlh%s
 r, r, "
1991 
        do_srlh(_SD, Ra, Rb, imm, p);
1992 
 
1993 
 
1994 
// SRL2H
1995 
 
1996 
_LOGIC,10011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL2H
1997 
"srl2h r, r, r"
1998 
        signed32 srcH = RcH;
1999 
        signed32 srcL = RcL;
2000 
        while (srcH > 15) srcH -= 16;
2001 
        while (srcH < -16) srcH += 16;
2002 
        while (srcL > 15) srcL -= 16;
2003 
        while (srcL < -16) srcL += 16;
2004 
        do_srlh(_SD, Ra, RbHU, srcH, 1);
2005 
        do_srlh(_SD, Ra, RbLU, srcL, 0);
2006 
_LOGIC,10011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL2H imm
2007 
"srl2h r, r, "
2008 
        signed32 src = imm;
2009 
        while (src > 15) src -= 16;
2010 
        while (src < -16) src += 16;
2011 
        do_srlh(_SD, Ra, RbHU, src, 1);
2012 
        do_srlh(_SD, Ra, RbLU, src, 0);
2013 
 
2014 
 
2015 
 
2016 
 
2017 
// ST2H
2018 
 
2019 
void::function::get_even_reg:int *reg, unsigned32 *r0, const char *name
2020 
        if (*reg & 1)
2021 
          sim_engine_abort (SD, CPU, cia,
2022 
                            "0x%lx:%s odd register (r%d) used in multi-word store",
2023 
                            (long) cia, name, *reg);
2024 
        if (*reg == 0)
2025 
          *r0 = 0;
2026 
        else
2027 
          *r0 = GPR[*reg];
2028 
 
2029 
void::function::do_st2h:int ra, unsigned32 rb, unsigned32 src
2030 
        unsigned32 val_ra;
2031 
        unsigned32 mem;
2032 
        get_even_reg(_SD, &ra, &val_ra, "ST2H");
2033 
        mem = INSERTED32(val_ra, 0, 15) |
2034 
              INSERTED32(GPR[ra + 1], 16, 31);
2035 
        STORE(rb + src, 4, mem);
2036 
 
2037 
_IMEM,10011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2H
2038 
"st2h r, @(r, )":XX == 0
2039 
"st2h r, @(r%s, r)"
2040 
        do_st2h(_SD, RA, Rb, src);
2041 
        do_incr(_SD, XX, &GPR[RB], 4);
2042 
_IMEM,10011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2H long
2043 
"st2h r, @(r, )"
2044 
        do_st2h(_SD, RA, Rb, imm);
2045 
 
2046 
 
2047 
 
2048 
// ST2W
2049 
 
2050 
void::function::do_st2w:int ra, unsigned32 rb, unsigned32 src
2051 
        unsigned32 val_ra;
2052 
        unsigned64 mem;
2053 
        get_even_reg(_SD, &ra, &val_ra, "ST2W");
2054 
        mem = INSERTED64(val_ra, 0, 31) | INSERTED64(GPR[ra + 1], 32, 63);
2055 
        STORE(rb + src, 8, mem);
2056 
 
2057 
_IMEM,10110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2W
2058 
"st2w r, @(r, )":XX == 0
2059 
"st2w r, @(r%s, r)"
2060 
        do_st2w(_SD, RA, Rb, src);
2061 
        do_incr(_SD, XX, &GPR[RB], 8);
2062 
_IMEM,10110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2W long
2063 
"st2w r, @(r, )"
2064 
        do_st2w(_SD, RA, Rb, imm);
2065 
 
2066 
 
2067 
 
2068 
// ST4HB
2069 
 
2070 
void::function::do_st4hb:int ra, unsigned32 rb, unsigned32 src
2071 
        unsigned32 val_ra;
2072 
        unsigned32 mem;
2073 
        get_even_reg(_SD, &ra, &val_ra, "ST4HB");
2074 
        mem = INSERTED32(EXTRACTED32(val_ra, 8, 15), 0, 7) |
2075 
              INSERTED32(EXTRACTED32(val_ra, 24, 31), 8, 15) |
2076 
              INSERTED32(EXTRACTED32(GPR[ra + 1], 8, 15), 16, 23) |
2077 
              INSERTED32(EXTRACTED32(GPR[ra + 1], 24, 31), 24, 31);
2078 
        STORE(rb + src, 4, mem);
2079 
 
2080 
_IMEM,10101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST4HB
2081 
"st4hb r, @(r, )":XX == 0
2082 
"st4hb r, @(r%s, r)"
2083 
        do_st4hb(_SD, RA, Rb, src);
2084 
        do_incr(_SD, XX, &GPR[RB], 4);
2085 
_IMEM,10101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST4HB long
2086 
"st4hb r, @(r, )"
2087 
        do_st4hb(_SD, RA, Rb, imm);
2088 
 
2089 
 
2090 
 
2091 
// STB
2092 
 
2093 
void::function::do_stb:unsigned32 ra, unsigned32 rb, unsigned32 src
2094 
        STORE(rb + src, 1, EXTRACTED32(ra, 24, 31));
2095 
 
2096 
_IMEM,10000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STB
2097 
"stb r, @(r, )":XX == 0
2098 
"stb r, @(r%s, r)"
2099 
        do_stb(_SD, val_Ra, Rb, src);
2100 
        do_incr(_SD, XX, &GPR[RB], 1);
2101 
_IMEM,10000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STB long
2102 
"stb r, @(r, )"
2103 
        do_stb(_SD, val_Ra, Rb, imm);
2104 
 
2105 
 
2106 
 
2107 
// STH
2108 
 
2109 
void::function::do_sth:unsigned32 ra, unsigned32 rb, unsigned32 src
2110 
        STORE(rb + src, 2, EXTRACTED32(ra, 16, 31));
2111 
 
2112 
_IMEM,10010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STH
2113 
"sth r, @(r, )":XX == 0
2114 
"sth r, @(r%s, r)"
2115 
        do_sth(_SD, val_Ra, Rb, src);
2116 
        do_incr(_SD, XX, &GPR[RB], 2);
2117 
_IMEM,10010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STH long
2118 
"sth r, @(r, )"
2119 
        do_sth(_SD, val_Ra, Rb, imm);
2120 
 
2121 
 
2122 
 
2123 
// STHH
2124 
 
2125 
void::function::do_sthh:unsigned32 ra, unsigned32 rb, unsigned32 src
2126 
        STORE(rb + src, 2, EXTRACTED32(ra, 0, 15));
2127 
 
2128 
_IMEM,10001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STHH
2129 
"sthh r, @(r, )":XX == 0
2130 
"sthh r, @(r%s, r)"
2131 
        do_sthh(_SD, val_Ra, Rb, src);
2132 
        do_incr(_SD, XX, &GPR[RB], 2);
2133 
_IMEM,10001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STHH long
2134 
"sthh r, @(r, )"
2135 
        do_sthh(_SD, val_Ra, Rb, imm);
2136 
 
2137 
 
2138 
 
2139 
// STW
2140 
 
2141 
void::function::do_stw:unsigned32 ra, unsigned32 rb, unsigned32 src
2142 
        STORE(rb + src, 4, ra);
2143 
 
2144 
_IMEM,10100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STW
2145 
"stw r, @(r, )":XX == 0
2146 
"stw r, @(r%s, r)"
2147 
        do_stw(_SD, val_Ra, Rb, src);
2148 
        do_incr(_SD, XX, &GPR[RB], 4);
2149 
_IMEM,10100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STW long
2150 
"stw r, @(r, )"
2151 
        do_stw(_SD, val_Ra, Rb, imm);
2152 
 
2153 
 
2154 
 
2155 
// SUB
2156 
 
2157 
void::function::do_sub:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2158 
        ALU_BEGIN(rb);
2159 
        ALU_SUBB(imm);
2160 
        ALU_END(ra);
2161 
 
2162 
_IALU1,00010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB
2163 
"sub r, r, r"
2164 
        do_sub (_SD, Ra, Rb, Rc);
2165 
_IALU1,00010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB imm
2166 
"sub r, r, "
2167 
        do_sub (_SD, Ra, Rb, imm);
2168 
_IALU1,00010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB imm long
2169 
"sub r, r, "
2170 
        do_sub (_SD, Ra, Rb, imm);
2171 
 
2172 
 
2173 
 
2174 
// SUB2H
2175 
 
2176 
void::function::do_sub2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2177 
        unsigned16 high = VH2_4(rb) - VH2_4(imm);
2178 
        unsigned16 low  = VL2_4(rb) - VL2_4(imm);
2179 
        WRITE32_QUEUE (ra, (high << 16) | low);
2180 
 
2181 
_IALU1,00011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB2H
2182 
"sub2h r, r, r"
2183 
        do_sub2h (_SD, Ra, Rb, Rc);
2184 
_IALU1,00011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB2H imm
2185 
"sub2h r, r, "
2186 
        do_sub2h (_SD, Ra, Rb, immHL);
2187 
_IALU1,00011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB2H imm long
2188 
"sub2h r, r, "
2189 
        do_sub2h (_SD, Ra, Rb, imm);
2190 
 
2191 
 
2192 
 
2193 
// SUBB
2194 
 
2195 
void::function::do_subb:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2196 
        ALU_BEGIN(rb);
2197 
        ALU_SUBB_B(imm, ALU_CARRY);
2198 
        ALU_END(ra);
2199 
 
2200 
_IALU1,00101,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBB
2201 
"subb r, r, r"
2202 
        do_subb (_SD, Ra, Rb, Rc);
2203 
_IALU1,00101,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBB imm
2204 
"subb r, r, "
2205 
        do_subb (_SD, Ra, Rb, imm);
2206 
_IALU1,00101,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBB imm long
2207 
"subb r, r, "
2208 
        do_subb (_SD, Ra, Rb, imm);
2209 
 
2210 
 
2211 
 
2212 
// SUBHppp
2213 
 
2214 
void::function::do_subh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
2215 
        switch (ppp) {
2216 
        case 0x0: /* LLL */
2217 
          {
2218 
          ALU16_BEGIN(VL2_4(rb));
2219 
          ALU16_SUBB(VL2_4(src));
2220 
          ALU16_END(ra, 0);
2221 
          }
2222 
          break;
2223 
        case 0x1: /* LLH */
2224 
          {
2225 
          ALU16_BEGIN(VL2_4(rb));
2226 
          ALU16_SUBB(VH2_4(src));
2227 
          ALU16_END(ra, 0);
2228 
          }
2229 
          break;
2230 
        case 0x2: /* LHL */
2231 
          {
2232 
          ALU16_BEGIN(VH2_4(rb));
2233 
          ALU16_SUBB(VL2_4(src));
2234 
          ALU16_END(ra, 0);
2235 
          }
2236 
          break;
2237 
        case 0x3: /* LHH */
2238 
          {
2239 
          ALU16_BEGIN(VH2_4(rb));
2240 
          ALU16_SUBB(VH2_4(src));
2241 
          ALU16_END(ra, 0);
2242 
          }
2243 
          break;
2244 
        case 0x4: /* HLL */
2245 
          {
2246 
          ALU16_BEGIN(VL2_4(rb));
2247 
          ALU16_SUBB(VL2_4(src));
2248 
          ALU16_END(ra, 1);
2249 
          }
2250 
          break;
2251 
        case 0x5: /* HLH */
2252 
          {
2253 
          ALU16_BEGIN(VL2_4(rb));
2254 
          ALU16_SUBB(VH2_4(src));
2255 
          ALU16_END(ra, 1);
2256 
          }
2257 
          break;
2258 
        case 0x6: /* HHL */
2259 
          {
2260 
          ALU16_BEGIN(VH2_4(rb));
2261 
          ALU16_SUBB(VL2_4(src));
2262 
          ALU16_END(ra, 1);
2263 
          }
2264 
          break;
2265 
        case 0x7: /* HHH */
2266 
          {
2267 
          ALU16_BEGIN(VH2_4(rb));
2268 
          ALU16_SUBB(VH2_4(src));
2269 
          ALU16_END(ra, 1);
2270 
          }
2271 
          break;
2272 
        default:
2273 
          sim_engine_abort (SD, CPU, cia, "do_subh_ppp - internal error - bad switch");
2274 
        }
2275 
 
2276 
_IALU1,11,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBHppp
2277 
"subh%s r, r, r"
2278 
        do_subh_ppp(_SD, ppp, Ra, Rb, Rc);
2279 
_IALU1,11,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBHppp imm
2280 
"subh%s r, r, "
2281 
        do_subh_ppp(_SD, ppp, Ra, Rb, immHL);
2282 
_IALU1,11,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBHppp imm long
2283 
"subh%s r, r, "
2284 
        do_subh_ppp(_SD, ppp, Ra, Rb, imm);
2285 
 
2286 
 
2287 
 
2288 
// TRAP
2289 
 
2290 
address_word::function::do_trap:address_word trap_vector, address_word nia
2291 
        /* Steal trap 31 for doing system calls */
2292 
        /* System calls are defined in libgloss/d30v/syscall.h.  */
2293 
        if (trap_vector == EIT_VB + 0x20 + (31 << 3))
2294 
          {
2295 
            enum { PARM1 = 2, PARM2, PARM3, PARM4, FUNC };
2296 
            if (GPR[FUNC] == 1)         /* exit */
2297 
              {
2298 
                sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, sim_exited,
2299 
                                 GPR[PARM1]);
2300 
                return -1; /* dummy */
2301 
              }
2302 
            else
2303 
              {
2304 
                CB_SYSCALL syscall;
2305 
 
2306 
                CB_SYSCALL_INIT (&syscall);
2307 
                syscall.arg1 = GPR[PARM1];
2308 
                syscall.arg2 = GPR[PARM2];
2309 
                syscall.arg3 = GPR[PARM3];
2310 
                syscall.arg4 = GPR[PARM4];
2311 
                syscall.func = GPR[FUNC];
2312 
                syscall.p1 = (PTR) SD;
2313 
                syscall.read_mem = d30v_read_mem;
2314 
                syscall.write_mem = d30v_write_mem;
2315 
 
2316 
                WRITE32_QUEUE (&GPR[PARM1],
2317 
                               ((cb_syscall (STATE_CALLBACK (SD), &syscall)
2318 
                                 == CB_RC_OK)
2319 
                                ? syscall.result
2320 
                                : -syscall.errcode));
2321 
                return nia;
2322 
              }
2323 
          }
2324 
        else if (TRACE_TRAP_P)
2325 
          {
2326 
            int reg, i;
2327 
            sim_io_eprintf (sd, "\nTrap %ld:\n", (long) ((trap_vector - (EIT_VB + 0x20)) >> 3));
2328 
            for (reg = 0; reg < NR_GENERAL_PURPOSE_REGISTERS; reg += 8)
2329 
              {
2330 
                sim_io_eprintf (sd, "r%.2d  - r%.2d: ", reg, reg+7);
2331 
                for (i = 0; i < 8; i++)
2332 
                  sim_io_eprintf (sd, " 0x%.8lx", (long) GPR[reg+i]);
2333 
                sim_io_eprintf (sd, "\n");
2334 
              }
2335 
 
2336 
            for (reg = 0; reg < 16; reg += 8)
2337 
              {
2338 
                sim_io_eprintf (sd, "cr%.2d - cr%.2d:", reg, reg+7);
2339 
                for (i = 0; i < 8; i++)
2340 
                  sim_io_eprintf (sd, " 0x%.8lx", (long) CREG[reg+i]);
2341 
                sim_io_eprintf (sd, "\n");
2342 
              }
2343 
 
2344 
            sim_io_eprintf (sd, "a0   - a1:  ");
2345 
            for (reg = 0; reg < NR_ACCUMULATORS; reg++)
2346 
              sim_io_eprintf (sd, " 0x%.8lx 0x%.8lx",
2347 
                              (long)EXTRACTED64(ACC[reg], 0, 31),
2348 
                              (long)EXTRACTED64(ACC[reg], 32, 63));
2349 
            sim_io_eprintf (sd, "\n");
2350 
 
2351 
            sim_io_eprintf (sd, "f0   - f7:  ");
2352 
            sim_io_eprintf (sd, "     (f0) %d", (int) PSW_VAL(PSW_F0));
2353 
            sim_io_eprintf (sd, "     (f1) %d", (int) PSW_VAL(PSW_F1));
2354 
            sim_io_eprintf (sd, "     (f2) %d", (int) PSW_VAL(PSW_F2));
2355 
            sim_io_eprintf (sd, "     (f3) %d", (int) PSW_VAL(PSW_F3));
2356 
            sim_io_eprintf (sd, "      (s) %d", (int) PSW_VAL(PSW_S));
2357 
            sim_io_eprintf (sd, "      (v) %d", (int) PSW_VAL(PSW_V));
2358 
            sim_io_eprintf (sd, "     (va) %d", (int) PSW_VAL(PSW_VA));
2359 
            sim_io_eprintf (sd, "      (c) %d\n", (int) PSW_VAL(PSW_C));
2360 
 
2361 
            sim_io_eprintf (sd, "pswh:       ");
2362 
            sim_io_eprintf (sd, "     (sm) %d", (int) PSW_VAL(PSW_SM));
2363 
            sim_io_eprintf (sd, "     (ea) %d", (int) PSW_VAL(PSW_EA));
2364 
            sim_io_eprintf (sd, "     (ie) %d", (int) PSW_VAL(PSW_IE));
2365 
            sim_io_eprintf (sd, "     (rp) %d", (int) PSW_VAL(PSW_RP));
2366 
            sim_io_eprintf (sd, "     (md) %d", (int) PSW_VAL(PSW_MD));
2367 
 
2368 
            if (PSW_VAL(PSW_DB))
2369 
              sim_io_eprintf (sd, "     (db) %d", (int) PSW_VAL(PSW_DB));
2370 
 
2371 
            if (PSW_VAL(PSW_DS))
2372 
              sim_io_eprintf (sd, "     (ds) %d", (int) PSW_VAL(PSW_DS));
2373 
 
2374 
            sim_io_eprintf (sd, "\n");
2375 
            return nia;
2376 
          }
2377 
        else
2378 
          {
2379 
            if(PSW_VAL(PSW_RP) && RPT_E == cia)
2380 
              {
2381 
                WRITE32_QUEUE (&bPC, RPT_S);
2382 
                if (RPT_C == 0)
2383 
                  PSW_SET (PSW_RP, 0);
2384 
              }
2385 
            else
2386 
              WRITE32_QUEUE (&bPC, cia + 8);
2387 
            DID_TRAP = 1;
2388 
            return trap_vector;
2389 
          }
2390 
 
2391 
_BRA,01001,00,6.**,6.**,6.RC:BRA:short:mu:TRAP
2392 
"trap r"
2393 
        nia = do_trap (_SD, EIT_VB + 0x20 + MASKED32(Rc, 24, 28), nia);
2394 
_BRA,01001,10,6.**,6.**,_IMM6:BRA:short:mu:TRAP imm
2395 
"trap "
2396 
        nia = do_trap (_SD, EIT_VB + 0x20 + (imm_5 << 3), nia);
2397 
 
2398 
 
2399 
 
2400 
// XOR
2401 
 
2402 
_LOGIC,11011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:XOR
2403 
"xor r, r, r"
2404 
        WRITE32_QUEUE (Ra, Rb ^ Rc);
2405 
_LOGIC,11011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:XOR imm
2406 
"xor r, r, "
2407 
        WRITE32_QUEUE (Ra, Rb ^ imm);
2408 
_LOGIC,11011,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:XOR imm long
2409 
"xor r, r, "
2410 
        WRITE32_QUEUE (Ra, Rb ^ imm);
2411 
 
2412 
 
2413 
 
2414 
// XORFG
2415 
 
2416 
_LOGIC,01011,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:XORFG
2417 
"xorfg f, f, f"
2418 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ PSW_FLAG_VAL(FC));
2419 
_LOGIC,01011,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:XORFG imm
2420 
"xorfg f, f, "
2421 
        PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ (imm_6 & 1));
2422 
 
2423 
 
2424 
 

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